| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 375286000 | MULTILEVEL | 80 |
| 20080212708 | Method and Apparatus for Carrier Recovery in a Communications System - A satellite communications system comprises a transmitter, a satellite transponder and a receiver. The transmitter transmits an uplink layered modulation signal having an upper layer and a lower layer to the satellite transponder, which broadcasts the layered modulation signal downlink to one, or more, receivers. The receiver receives the layered modulation signal (the received signal) and performs demodulation and decoding of the lower layer signal component thereof by using a recovered carrier to derotate the received signal, wherein the recovered carrier is developed by a carrier recovery process driven by soft decisions with respect to the upper layer signal component of the received signal. | 09-04-2008 |
| 20080212709 | Three phase and polarity encoded serial interface - A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval. | 09-04-2008 |
| 20090028266 | Compact encoding of arbitrary length binary objects - A method and apparatus for encoding data of arbitrary length. Data of arbitrary size is divided into one or more data blocks. One or more length blocks are generated that include length information identifying a quantity of the one or more data blocks into which the data is divided, wherein the length information can be determined by a number of reads of the length blocks and without examining the data blocks. The length blocks and the data blocks are transmitted. | 01-29-2009 |
| 20090060083 | RECEIVER CIRCUIT - A receiver circuit includes a voltage controller configured to output an offset voltage varied according to a control code; and a multilevel receiving block configured to be controlled by the offset voltage and to amplify and output input data signal having multilevels. | 03-05-2009 |
| 20090097587 | VECTOR CODING METHOD AND APPARATUS AND COMPUTER PROGRAM - A vector coding apparatus and method includes decomposing an initial vector to obtain a sign vector and an initial absolute vector. Coding the sign vector to obtain a sign code, performing multi-level permutation-based coding on the initial absolute vector to obtain an absolute vector code, and combining the sign code and the absolute vector code. Optionally determining, before decomposing the initial vector, a characteristic codebook to which the initial vector belongs, obtaining a characteristic value of the characteristic codebook, and combining a code of the initial vector to obtain a final code of the initial vector. The performing step can include removing from the initial absolute vector any element having a value which satisfies a preset condition, constructing a new absolute vector with elements not satisfying the preset condition, and coding positions of the elements not satisfying the preset condition in the initial absolute vector to obtain a position code. | 04-16-2009 |
| 20090122903 | Data Transmissiom System And Data Transmission Method - The present invention maps coded bits that have been output from a low density parity check coder | 05-14-2009 |
| 20090122904 | Apparatuses and method for multi-level communication - In one embodiment, the apparatus includes a driver circuit configured such that for each symbol in a set of possible symbols, the driver circuit generates at least one data signal at an associated voltage level. Here, adjacent voltage levels defme an associated voltage interval, and the driver circuit is configured to generate the voltage levels such that a central voltage interval is less than at least one of the voltage intervals adjacent to the central voltage interval. | 05-14-2009 |
| 20090122905 | METHODS AND APPARATUS FOR SIGNALING ON A DIFFERENTIAL LINK - Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link. | 05-14-2009 |
| 20090135946 | Tiled-building-block trellis decoders - A multi-level encoded signal is encoded according to at least an upper-level code and a lower-level code. In a receiver, a modified type of a multistage decoder is deployed. The upper-level code is decoded to produce a sequence of tentative upper-level coding decisions independently of the lower-level code. The lower-level code is next decoded in such a way that the decoding is conditioned upon at least one of the tentative upper-level decisions. The lower-level decoder thereby produces a sequence of lower-level decisions. The upper-level code is then decoded a second time, this time conditioned upon at least one of the lower-level decisions, to produce a second, more reliable sequence of upper-level coding decisions. The lower-level decision sequence and the second upper-level decision sequence are delivered from the decoder as output sequences. | 05-28-2009 |
| 20090154590 | MULTILEVEL QAM DEMODULATOR, MULTILEVEL QAM DEMODULATION METHOD, AND WIRELESS COMMUNICATION SYSTEM - A multilevel QAM demodulator includes a phase difference calculation unit calculating a phase difference signal based on the common phase signal and orthogonal signal after the phase rotation compensation, a phase shift amount calculation unit calculating a phase shift amount indicating a degree of a phase shift based on the common phase signal and orthogonal signal after the phase rotation compensation and phase noise compensation, and a correction unit correcting the phase difference signal based on the phase shift amount. A phase rotation is performed for the phase noise compensation based on the phase difference signal corrected by the correction unit. | 06-18-2009 |
| 20090161786 | DIGITAL RADIO COMMUNICATIONS METHOD USING MULTI-LEVEL MODULATION SCHEME AND TRANSMITTER AND RECEIVER - A transmitter for use in digital radio communications systems includes: a bit corrector controls bit arrangement in such a manner that a code having high significance, out of multiple codes obtained by coding, is allocated with high priority to a bit having a tendency that the likelihood enlarges at the time of symbol decision on a receiver; a multi-level modulator allocates the code to the multiple bits in accordance with a predetermined symbol arrangement; and a symbol arrangement controller controls the symbol arrangement from equal distance arrangement to another arrangement in accordance with a ratio of the codes different in significance. To control symbol arrangement increases the effect of bit correction and improves an error rate on the receiver. | 06-25-2009 |
| 20090168917 | MODULATION AND DEMODULATION METHOD, MODULATION APPARATUS AND DEMODULATION APPARATUS - The present invention relates to a modulation and demodulation method of minimizing an error rate and applying it to a differential operation modulo 4. A modulation apparatus includes a Gray coding circuit | 07-02-2009 |
| 20090274240 | COMMUNICATION SYSTEM - At the transmitter side, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into, two, first and second, data streams. The signal points are divided into signal point groups to which data of the first data stream are assigned. Also, data of the second data stream are assigned to the signal points of each signal point group. At the receiver side, the first and/or second data streams can be reconstructed from a received signal. Furthermore, a communication system based on an OFDM system is utilized for data transmission of a plurality of subchannels, wherein the subchannels are differentiated by changing the length of a guard time slot or a carrier wave interval of a symbol transmission time slot, or changing the transmission electric power of the carrier. | 11-05-2009 |
| 20090285326 | Generation and Detection of Non-Binary Digital Sequences - Method and apparatus for generating ternary and multi-valued Gold sequences, are disclosed. Also methods to detect ternary and multi-valued sequences are disclosed. The detection can be performed by a ternary or multi-valued LFSR descrambler when the sequences are generated by an LFSR based sequence generator. A wireless system which can assign additional sequences to designated users is also disclosed. The wireless system can also transfer information to user equipment that enables methods for sequence generation and sequence detection. | 11-19-2009 |
| 20090323852 | DATA RECEIVING APPARATUS - To provide a receiving apparatus which is capable of demodulating information data from a multi-level modulated signal, which is generated by using a Y-00 protocol, without using high-performance component parts. In the receiving apparatus, the soft decision section | 12-31-2009 |
| 20100014607 | AD CONVERTER, DATA RECEIVER AND DATA RECEPTION METHOD - An AD converter includes a first amplitude circuit, a second amplitude circuit, and a determination circuit. A control signal line controls a first amplitude gain of the first amplitude circuit and a second amplitude gain of the second amplitude circuit. | 01-21-2010 |
| 20100027708 | INFORMATION PROCESSING DEVICE AND SIGNAL PROCESSING METHOD - An information processing device is provided that includes a signal receiving portion, an absolute value conversion portion, and an input data decoding portion. The signal receiving portion receives a signal that is encoded such that mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the first and second bit values also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle. The absolute value conversion portion converts into absolute values the amplitude values of the signal that has been received by the signal receiving portion. The input data decoding portion decodes the first and second bit values based on the amplitude values in the signal that have been converted into absolute values by the absolute value conversion portion. | 02-04-2010 |
| 20100067611 | TRANSMISSION DEVICE WITH ENHANCED SIGNALS - A transmission device includes a first encoder, a plurality of current sources, a switch module, a second encoder, and a plurality of current enhanced circuits. The first encoder converts an input signal to a first control signal. The switch module is coupled between the plurality of current sources and a plurality of signal lines for controlling the connection of the current sources and the signal lines according to the first control signal to generate a current signal. The second encoder generates a second control signal according to the first control signal or the input signal. The plurality of current enhanced circuits is coupled to the plurality of current sources respectively. The plurality of current enhanced circuits provides an extra current in a predetermined duration to enhance the current signal. | 03-18-2010 |
| 20100150262 | APPARATUS AND METHOD FOR AMPLIFYING SIGNAL AND WIRELESS TRANSMITTER USING THE SAME - Provided are a signal amplifying apparatus and method and a wireless transmitter using the same. The signal amplifier includes a polar coordinate converter configured to output an envelope signal and a phase signal by converting a signal to a polar coordinate, a multilevel quantizer configured to output a multilevel quantized signal by quantizing the envelope signal to multiple levels, an amplification state controller configured to control an amplification state using the multilevel quantized signal, and a power amplifier configured to amplify the phase signal according to the controlled amplification state. | 06-17-2010 |
| 20100158153 | Transmission Method And Transmission Apparatus - A transmission apparatus obtains, for each transmission to a reception apparatus, information on a per-bit transmission of a transmission bit string, and controls a per-bit transmission condition for a current transmission bit string such that a per-bit transmission quality of the transmission bit string approaches evenly based on cumulative information on the transmissions up to the last transmission. | 06-24-2010 |
| 20100246708 | RADIO COMMUNICATION APPARATUS, RADIO COMMUNICATION METHOD, AND RADIO COMMUNICATION SYSTEM - A radio communication apparatus, a radio communication method, and a radio communication system, which are capable of improving receiving reliability of predetermined bits such as bits having a high degree of importance, and the like, are provided. A code length L is decided based on the modulation system and the coding rate being specified, and the bit length of S | 09-30-2010 |
| 20100254478 | ARRANGEMENT AND METHOD FOR SIGNAL TRANSMISSION BETWEEN DIFFERENT VOLTAGE DOMAINS - An arrangement and method for signal transmission between different voltage domains is disclosed. One embodiment provides a first signal processing unit receiving a first supply voltage. A second signal processing unit receives a second supply voltage, the first supply voltage and the second supply voltage overlap each other in a first overlap range. A third signal processing unit receives a third supply voltage, the second supply voltage and the third supply voltage overlap each other in a second voltage overlap range. A first information signal from the first signal processing unit is transmitted to the second signal processing unit. A second information signal dependent on the first information signal from the second signal processing is transmitted to the third signal processing unit. | 10-07-2010 |
| 20110044398 | Hard iterative decoder for multilevel codes - Two decoding algorithms are introduced for the decoding of multi-level coded modulation and other types of coded modulation involving component codes and interleaving operations. An improved hard iterative decoding (IHID) algorithm is presented that improves upon a hard iteration decoding technique by adding a stopping criterion. Also, a list Viterbi hard iteration decoding (LV-IHID) algorithm is presented that employs list decoding in conjunction with the IHID algorithm. Both of these decoding algorithms improve upon conventional multi-stage decoding by reducing the effective error multiplicity that is observed at the lowest coding level. It is demonstrated that the LV-IHID algorithm performs close to soft iterative decoding. The computational and delay complexity of the proposed decoding algorithms compare favorably with soft iterative decoding strategies. Also, a novel labeling strategy for MLC design is presented. | 02-24-2011 |
| 20110044399 | List-viterbi hard iterative decoder for multilevel codes - Two decoding algorithms are introduced for the decoding of multi-level coded modulation and other types of coded modulation involving component codes and interleaving operations. An improved hard iterative decoding (IHID) algorithm is presented that improves upon a hard iteration decoding technique by adding a stopping criterion. Also, a list Viterbi hard iteration decoding (LV-IHID) algorithm is presented that employs list decoding in conjunction with the IHID algorithm. Both of these decoding algorithms improve upon conventional multi-stage decoding by reducing the effective error multiplicity that is observed at the lowest coding level. It is demonstrated that the LV-IHID algorithm performs close to soft iterative decoding. The computational and delay complexity of the proposed decoding algorithms compare favorably with soft iterative decoding strategies. Also, a novel labeling strategy for MLC design is presented. | 02-24-2011 |
| 20110051838 | DRIVING A MIXER WITH A DIFFERENTIAL LO SIGNAL HAVING AT LEAST THREE SIGNAL LEVELS - The mixer of a transmit chain of a wireless transmitter (such as the transmitter of a cellular telephone handset) is driven with low third harmonic in-phase (I) and quadrature (Q) signals. The low third harmonic I and Q signals have three or more signal levels, and transition between the these three or more signal levels at times such that each of the I and Q signals approximates a sine wave and has minimal third harmonic spectral components. In one example, reducing the third harmonic components of the I and Q signals simplifies design of amplifier stages of the transmitter and helps reduce receive band noise. | 03-03-2011 |
| 20110058622 | METHOD AND APPARATUS FOR PROVIDING HIGH EFFICIENCY CARTESIAN MODULATION - The disclosure relates to a method and apparatus for providing efficient signal transmission. Conventional linear amplifiers are most efficient when operated in compressed mode. In the compressed mode, the digital power amplifier switches between the on and off modes. A digital power amplifier operates in compressed mode only if the incoming signal is an on-off constant envelop signal. In one embodiment, the disclosure provides a method and apparatus for converting a digital baseband signal to on-off constant envelop signals for processing through binary-weighted or thermometer-weighted amplifier which are operated in compressed mode. | 03-10-2011 |
| 20110135029 | TRANSMITTER, TRANSMISSION METHOD, RECEIVER, AND RECEPTION METHOD - Multi-level modulation is performed with a signal point constellation in which any three adjacent signal points on a phase plane form an equilateral triangle and at least a distance between a signal point closest to the origin of the phase plane and the origin is increased within a range that the transmission mean power remains unchanged. | 06-09-2011 |
| 20110235738 | SYSTEM AND METHOD FOR GENERATING TEST PATTERNS OF BASELINE WANDER - A system and method for generating test patterns of baseline wander, such as worst-case test patterns commonly referred to as killer packets. The number of steps required to cycle an output of a multi-level encoder in order to arrive at an anticipated level is determined. A test packet generator then generates the test patterns according to the determined steps and the state of a scrambler. | 09-29-2011 |
| 20110310992 | SYSTEMS, METHODS, AND COMPUTER READABLE MEDIA FOR FRACTIONAL PRE-EMPHASIS OF MULTI-MODE INTERCONNECT - Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect are disclosed. According to one aspect, the subject matter described herein includes a method for fractional pre-emphasis of multi-mode interconnect. Multiple bits of binary data are periodically received. For each period, the multiple bits of binary data are encoded into multiple scalar values, each value representing a level of an analog signal to be output over a multi-mode interconnect system during the current period. Multiple analog signal outputs are generated corresponding to multiple scalar values, each signal output being driven to a level according to its corresponding scalar value. For each representative scalar value, a difference between the scalar value generated during the current period and the scalar value generated during the previous period is determined, and a pre-emphasis signal that is proportional to the difference is generated. Pre-emphasize each analog signal output according to the respective pre-emphasis signal, where the analog signal is pre-emphasized for a fraction of a period that is less than the entire period. | 12-22-2011 |
| 20130235948 | MULTI-LEVEL SIGNALING - Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output. | 09-12-2013 |
| 20130243112 | WIRELESS DEVICE AND WIRELESS COMMUNICATION METHOD - A wireless device, including: an antenna configured to receive a reception signal, a processor configured to convert the reception signal into a first signal that includes a product of an upper triangular matrix and a transmission signal, to detect a first region, to which the first signal belongs, on an IQ plane, a memory configured to store a symbol ranking table that stores symbol candidates in an order of shorter distance from a region center, up to an order that is equal to a rank upper limit value that is set to be lower than a modulation multi-level number of the transmission signal, wherein the processor is further configured to select a first symbol candidate based on the first region and the symbol ranking table. | 09-19-2013 |
| 20130251060 | MULTILEVEL AMPLITUDE MODULATION DEVICE, MULTILEVEL AMPLITUDE DEMODULATION DEVICE, TRANSMISSION SYSTEM INCLUDING THESE, MULTILEVEL AMPLITUDE MODULATION METHOD, AND MULTILEVEL AMPLITUDE DEMODULATION METHOD - A multilevel amplitude modulation device for generating, from digital data, a multilevel amplitude modulation signal having four or more signal levels and outputting the generated signal, including: an average level calculator that selects one of a plurality of preliminarily prepared different candidates for a code word building method such that average level of a symbol array, obtained by adding a symbol for a code word of digital data to be transmitted to one or more already outputted symbols included in a multilevel amplitude modulation signal already outputted, is most approximate to voltage center of the four or more signal levels, and outputs a selection signal indicating the selected method; a signal converter that forms a codeword of the digital data in accordance with the method indicated by the selection signal; and a multilevel modulator that generates a multilevel amplitude modulation signal using the codeword and outputs the generated signal. | 09-26-2013 |
| 20130301750 | METHODS AND SYSTEMS FOR MULTI-LEVEL DATA TRANSMISSION - A method for multi-level data transmission includes encoding a data signal to be transmitted into N multi-level signals in accordance with an encoding table, where the data signal is characterized with a stream of binary data segments each of which has a data length of M bits, transmitting simultaneously the N multi-level signals through N data transmission channels, respectively; and decoding the N multi-level signals into the data signal by comparing each two of the N multi-level signals transmitted through the two data transmission channels to obtain a respective bit of the M bits of each binary data segment of the data signal based on comparison between the two corresponding multi-level signals. | 11-14-2013 |
| 20140003549 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR ASYMMETRIC MULTIMODE INTERCONNECT | 01-02-2014 |
| 20140301499 | METHODS FOR BYPASSING FAULTY CONNECTIONS - Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors. | 10-09-2014 |
| 20140307825 | DIGITAL POLAR MODULATOR FOR A SWITCH MODE RF POWER AMPLIFIER - A digital polar modulator (DPM) for transforming a baseband signal into a modulated digital modulator output signal comprises an input unit and two low-pass delta-sigma modulators, a first one being connected downstream from the first input part and configured to provide at its output a first pulse train in dependence on an amplitude- modulating baseband signal component, and a second one being connected downstream from the second input part and configured to provide at its output a multilevel quantized signal in dependence on a phase modulating baseband signal component; a multiphase generator, which is configured to provide a set of square-wave carrier signals having a common carrier frequency and exhibiting discrete phase shifts with respect to each other; a multiplexer, which is configured to provide a multiplexer output signal that is formed by switching, in dependence on a signal received at a select input as a function of time, between selected ones of the carrier signals; and a combiner unit. | 10-16-2014 |
| 20150016562 | MULTILEVEL SIGNAL TRANSMISSION SYSTEM CAPABLE OF ACCURATELY DETERMINING VOLTAGE LEVELS OF TRANSMITTED MULTILEVEL DATA SIGNAL - A multilevel signal transmitting apparatus transmits a multilevel data signal with M voltage levels, and a multilevel clock signal with (M−2) voltage levels, to a multilevel signal receiving apparatus, where M is an even number equal to or more than four. The voltage levels of the multilevel data signal include M/2 first voltage levels larger than a reference voltage level, and M/2 second voltage levels smaller than the reference voltage level. Between each pair of adjacent voltage levels among the first voltage levels, one voltage level of the multilevel clock signal is set. Between each pair of adjacent voltage levels among the second voltage levels, one voltage level of the multilevel clock signal is set. An average of the voltage levels of the multilevel clock signal has a value between a minimum of the first voltage levels, and a maximum of the second voltage levels. | 01-15-2015 |
| 20150092879 | APPARATUS AND METHOD FOR MULTILEVEL CODING IN COMMUNICATION SYSTEMS - A method includes receiving input blocks each having multiple bits to be transmitted. The method also includes applying a first encoding scheme to a first subset of the bits in the input blocks to generate first encoded bits and applying a second encoding scheme to a second subset of the bits in the input blocks to generate second encoded bits. The second encoding scheme has lower overhead than the first encoding scheme. The method further includes generating symbols using the first and second encoded bits. The first encoded bits include two or more first bits per symbol of each output block, and the second encoded bits include one or more second bits per symbol of each output block. | 04-02-2015 |
| 20150139350 | MULTI-LEVEL DIFFERENTIAL DECODING DEVICE AND METHOD FOR QUADRATURE AMPLITUDE MODULATION COMMUNICATION SYSTEM - Differential decoding processing applied to multilevel modulation is accomplished with the circuit scale kept small by including; an MSB coordinate rotating part for performing coordinate rotation based on information of the first two most significant bits of a signal received via a synchronous detection part; an MSB symbol likelihood generating part for generating likelihood with respect to the first two most significant bits after differential decoding, with the use of two sets of bit strings at different points in time for which coordinate rotation has been performed; an LSB symbol likelihood generating part for generating likelihood with respect to less significant bits; and a soft decision error correction decoding part for generating a decoded signal with the use of the likelihood of the first two most significant bits and the likelihood of the less significant bits. | 05-21-2015 |
| 20160043885 | MULTI-LEVEL SIGNALING - Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output. | 02-11-2016 |
| 20160072651 | METHOD AND SYSTEM FOR A MULTI-LEVEL ENCODED DATA PATH WITH DECODER - Methods and systems for a multi-level encoded data path with decoder are disclosed and may include, in a receiver on a chip: receiving a multi-level encoded signal, generating a plurality of copy signals offset from the multi-level encoded signal by a configurable offset voltage, comparing each copy signal against a different threshold level, and generating binary data based on the comparison. At least one of the plurality of copy signals may be compared using a clock data recovery module and/or using a retimer, which may comprise at least one D flip-flop. The multi-level encoded signal may comprise a pulse amplitude modulated-4 (PAM-4) signal. The multi-level encoded signal may be received from a photodiode on the chip. An optical signal may be communicated to the photodiode from a grating coupler on the chip. | 03-10-2016 |
| 375287000 | With threshold level | 12 |
| 20090238300 | MULTI-LEVEL SIGNALING FOR LOW POWER, SHORT CHANNEL APPLICATIONS - Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output. | 09-24-2009 |
| 20090279635 | DIFFERENTIAL DATA TRANSCEIVER AND METHOD WITH REVERSED-WIRE IMMUNITY - A polarity independent differential data transceiver receives a differential voltage signal and outputs a first logic state when the differential voltage signal is in a positive voltage differential range and/or when the differential voltage signal is in a corresponding negative differential voltage range. The differential data transceiver will output a second logic state in response to receiving a voltage differential signal that is in an intermediate differential voltage range near zero between the positive differential voltage range and the corresponding negative differential voltage range. | 11-12-2009 |
| 20100027709 | Method And System For Slicing A Communication Signal - A slicer can receive a communication signal having a level or amplitude that is between two discrete levels of a multilevel digital communication scheme. The slicer can compare the communication signal to a plurality of references such that multiple comparisons proceed essentially in parallel. A summation node can add the results of the comparisons to provide an output signal set to one of the discrete levels. The slicer can process the communication signal and provide the output signal on a symbol-by-symbol basis. A decision feedback equalizer (“DFE”) can comprise the slicer. A feedback circuit of the DFE can delay and scale the output signal and apply the delayed and scaled signal to the communication signal to reduce intersymbol interference (“ISI”). | 02-04-2010 |
| 20140269974 | Signal level decision device and method - The present invention discloses a signal level decision device to determine the level of a source signal. Said source signal comprises a plurality of source messages along a time axis; each source message corresponds to one of a plurality of normal levels; and each normal level is equivalent to at least one of a plurality of extension levels. The signal decision device comprises: a storage circuit to store the level information of the normal level(s) and the equivalent extension level(s) thereof in connection with some or all of the source messages; a transition parameter calculation circuit to calculate a plurality of transition parameters of the normal level and its equivalent extension level(s) in connection with each of the source messages according to the level information; and a decision circuit to determine the level of each of the source messages according to the plurality of transition parameters. | 09-18-2014 |
| 20140314171 | MISMATCHED DIFFERENTIAL CIRCUIT - A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator. | 10-23-2014 |
| 20140314172 | STACKED COMPARATOR TOPOLOGY FOR MULTI-LEVEL SIGNALING - A system and method for detecting signal levels in a multi-level signaling receiver. In one embodiment, a plurality of comparators, each including a differential pair, such as a differential pair of field-effect transistors (FETs) are assembled in a stacked configuration so that in some states current flows through FETs of the plurality of differential pairs in series, resulting in a reduction in power consumption. | 10-23-2014 |
| 20140314173 | PVT TOLERANT DIFFERENTIAL CIRCUIT - An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver. | 10-23-2014 |
| 20150049835 | MULTILEVEL SIGNAL TRANSMISSION SYSTEM CAPABLE OF TRANSMITTING MULTILEVEL DATA SIGNAL WITHOUT SIGNAL DISTORTION AND CORRECTLY DETERMINING VOLTAGE LEVEL - A multilevel signal transmitting apparatus determines a voltage level indicating an original data signal, and generates a multilevel data signal including a plurality of unit time intervals each having the determined voltage level. The multilevel signal transmitting apparatus assigns an even number of voltage levels to each unit time interval, assigns a smaller number of voltage levels than a maximum number of voltage levels, to a unit time interval next to a unit time interval to which the maximum number of voltage levels are assigned, and determines one of the assigned voltage levels, as the voltage level indicating the original data signal. A multilevel signal receiving apparatus detects the voltage level of the multilevel data signal, and reproduces the original data signal, based on the assigned voltage levels and the detected voltage level. | 02-19-2015 |
| 20150071371 | METHOD OF GENERATING DRIVING SIGNAL FOR DRIVING DUAL MODE SUPPLY MODULATOR FOR POWER AMPLIFIER AND DEVICE THEREOF - Provided is a method of generating a driving signal for driving a dual mode supply modulator for a power amplifier. The method includes obtaining an envelope of a complex baseband signal to be transmitted, comparing the envelope of the complex signal with a preset threshold value, when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; and when the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter. | 03-12-2015 |
| 20150303961 | MULTI-BRANCH OUTPHASING SYSTEM AND METHOD - A multi-level, multi-branch outphasing amplifier ( | 10-22-2015 |
| 20160013958 | DATA LINK POWER REDUCTION TECHNIQUE USING BIPOLAR PULSE AMPLITUDE MODULATION | 01-14-2016 |
| 20160065495 | Method and circuit for establishing network connection - The present invention discloses a network connection establishing method capable of preventing a link procedure from being strangled in a training state. An embodiment of the method comprises: a preceding step; a training step; and a following step. Said training step includes at least one of the following: counting a number, and returning to the preceding step if a local receiver is not yet ready after finishing counting the number; detecting a reception signal according to a signal detection level, and returning to the preceding step when none of the reception signal is detected; determining a number of level(s) of the reception signal, and returning to the preceding step if the number of level(s) is less than an expected level number; and comparing a signal-to-noise ratio of the reception signal with a signal-to-noise threshold, and returning to the preceding step when the signal-to-noise ratio fails to satisfy the signal-to-noise threshold. | 03-03-2016 |
| 375288000 | Transmission line | 11 |
| 20090034648 | Method and Apparatus for Sending DC-Balanced Signals Over a Transmission Line - A DC-balanced signal is imposed on the input of a transmission line. Prior to imposing the DC-balanced signal, the input of the transmission line is held at an intermediate DC level that intermediate between the maximum and minimum DC levels of the DC-balanced signal. Alternatively, a compensating pulse is additionally imposed on the input of the transmission line. The compensating pulse compensates for a change in the DC level at the output of the transmission line caused by the imposing of the DC-balanced signal on the input of the transmission line. | 02-05-2009 |
| 20100054359 | INFORMATION PROCESSING APPARATUS, DECODING PROCESSING METHOD AND SIGNAL TRANSMISSION METHOD - There is provided an information processing apparatus, including a signal receiving unit that receives a signal encoded in such a way that a signal containing a first bit value and a second bit value that are mutually different, wherein the first bit value is represented by a plurality of first amplitude values, the second bit value is represented by a second amplitude value that is different from the first amplitude values, a same amplitude value is not taken successively, and polarity of the amplitude value is reversed in each period, an amplitude square unit that squares an amplitude of the signal received by the signal receiving unit, and an input data decoding unit that decodes an input data by determining the first and second bit values based on the amplitude value of the signal output from the amplitude square unit. | 03-04-2010 |
| 20100220805 | Single-Wire Asynchronous Serial Interface - The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group. | 09-02-2010 |
| 20110280332 | PROVIDING DELIMITERS FOR LOW-OVERHEAD COMMUNICATION IN A NETWORK - Transmitting a waveform over a shared medium from a first station to at least one second station comprises: forming a first portion of the waveform comprising a symbol having a predetermined symbol length, the symbol comprising a first set of frequency components at predetermined carrier frequencies modulated with preamble information stored in the second station and a second set of frequency components at predetermined carrier frequencies modulated with information to be communicated to the second station, with the carrier frequencies of the first and second sets of frequency components being integral multiples of a frequency interval determined by the inverse of the symbol length; forming a second portion of the waveform, the second portion of the waveform comprising an segment that is correlated with at least an initial segment of the first portion of the waveform; and transmitting the waveform including the second portion followed in time by the first portion over the shared medium. | 11-17-2011 |
| 20120155565 | Three phase and polarity encoded serial interface - A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval. | 06-21-2012 |
| 20130215991 | THREE PHASE AND POLARITY ENCODED SERIAL INTERFACE - A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval. | 08-22-2013 |
| 20130223559 | Data tranmission driver, system and method - A system and method are provided for transmission of data bits across a data bus. To reduce power usage, noise, or some combination of the two, the data bus utilizes differential transmission using a three level signal in which a reference signal signifies no difference between input bits. Before the signals are transmitted an analysis is made to choose which one of a set of predetermined polarity reversal combinations is advantageous to encode the data bits. The data bits are so encoded and a formatting value F associated with the chosen polarity reversal is differentially transmitted with the encoded bits over the data bus. The three level differential signal is received at the far end of the bus, the encoded bits are recovered and decoded with use of F. The system and method achieves up to N bits transmitted per N data lines. | 08-29-2013 |
| 20140153665 | N-PHASE PHASE AND POLARITY ENCODED SERIAL INTERFACE - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector. | 06-05-2014 |
| 20150146816 | METHODS AND APPARATUS TO REDUCE SIGNALING POWER - System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state. | 05-28-2015 |
| 20160006587 | METHODS AND APPARATUS TO REDUCE SIGNALING POWER - System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state. | 01-07-2016 |
| 20160099817 | N-PHASE PHASE AND POLARITY ENCODED SERIAL INTERFACE - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector. | 04-07-2016 |
| 375289000 | Bipolar signal | 1 |
| 20150312025 | SINGLE-WIRE TRANSMISSION INTERFACE AND SINGLE-WIRE TRANSMISSION METHOD AND POWER SUPPLY SYSTEM ADOPTING SINGLE-WIRE TRANSMISSION METHOD - The present invention discloses a single-wire transmission method, which includes: providing a transmission signal including alternating high and low levels through a single-wire, wherein a period of one of the high and low levels defining a reference time and a period of the other of the high and low levels defining a content time; determining a relative relationship between the reference time and the content time; when the content time is smaller than a proportion of the reference time, defining the content time to express a first meaning; and when the content time is larger than the proportion of the reference time, defining the content time to express a second meaning. | 10-29-2015 |
| 375290000 | Partial response | 5 |
| 20140133596 | GENERATION OF MULTILEVEL SIGNALS USING CORRELATIVE CODING - Disclosed is a polybinary-signal generator in which correlative coding is applied to a plurality of fractional-bit-rate signals instead of being applied to a corresponding multiplexed full-bit-rate signal. The resulting coded fractional-bit-rate signals are variously delayed with respect to one another and then summed to generate a polybinary output signal. One beneficial feature of this architecture is that most circuit components of the polybinary-signal generator operate at the fractional bit rate, which helps to alleviate at least some of the technical difficulties associated with the design of radio-frequency circuits intended for relatively high bit rates. Another beneficial feature of this architecture is that the polybinary-signal generator also serves as a signal multiplexer. | 05-15-2014 |
| 375291000 | Duobinary | 4 |
| 20090190690 | COMMUNICATION SYSTEM - According to an aspect of an embodiment, a communication system includes a transmission apparatus with a coding section that generates multi-level-coded signals and transmits the multi-level-coded signals; and a deskew signal generation section that generates and transmits a deskew signal related to the multi-level-coded signals. The communication system also includes a receiving apparatus with a decoding section that decodes the multi-level-coded signals to generate decoded signals, and a deskew processing section that performs deskew processing for compensating skew among the decoded signals of the multiple channels. The deskew signal generation section generates the deskew signal that has been framed by extracting a part of the data from each of the channels of the input signals, adding framing data for enabling a receiving apparatus to recognize which channel the extracted data has been extracted from, and performing rate conversion. | 07-30-2009 |
| 20090232248 | DATA RECEIVING DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING SUCH DATA RECEIVING DEVICE - A data receiving device comprises amplifying circuit | 09-17-2009 |
| 20090238301 | MULTILEVEL SIGNAL RECEIVER - In the present multilevel signal receiver, an output signal of a comparator which judges a high-level of a multilevel signal and a signal obtained by inverting an output signal of a comparator which judges a low-level of the multilevel signal are input to an edge-triggered RS-FF, and an output signal of the edge-triggered RS-FF is fed back to the comparator on the high-level side via a LPF, so that a high-level threshold voltage is regulated. At the same time, a signal obtained by inverting the output signal of the comparator on the high-level side and the output signal of the comparator on the low-level side are input to an edge-triggered RS-FF, and an output signal of the edge-triggered RS-FF is fed back to the comparator on the low-level side via a LPF, so that a low-level threshold voltage is regulated. As a result, it becomes possible to provide a multilevel signal receiver of a simple circuit configuration, capable of controlling the thresholds used for level judgment of the multilevel signal of three or more levels to follow in real time a level change in the multilevel signal. | 09-24-2009 |
| 20100232541 | DATA TRANSMISSION SYSTEM, RECEIVING APPARATUS AND DATA TRANSMISSION METHOD USING THE SAME - Precoded data transmitted from transmitting apparatus ( | 09-16-2010 |
| 375292000 | Disparity reduction | 2 |
| 20100202555 | TRANSMISSION DEVICE - The present invention aims to provide a transmission device that, in a communication system using multilevel modulation with 2̂n levels (n being an integer greater than or equal to two), limits the run length to a predetermined value or less and guarantees DC balance. | 08-12-2010 |
| 20150078475 | COMMUNICATION SYSTEMS BASED ON HIGH-GAIN SIGNALING - Systems, methods and apparatus for transferring data at a high rate. Examples may provide transmitters and receivers that transfer data at a high rate by encoding the data to be transmitted such that the circuits of the transmitter and receiver operate in their high-gain states. The encoded signal may have an average value that is independent of the data that is conveyed by the transmitted signal. In other examples, the encoding may shape the data signal into a data signal having a high-pass characteristic. When the high-pass encoded signal is transmitted through a channel having a low-pass transfer function, the resulting output signal may have much lower ISI compared to a un-encoded input signal. Transmit and receive circuits, such as amplifiers, laser, and photo-diodes, are biased to operate in their high-gain regions when receiving the encoded data in order to provide high-bandwidth and shorter transition times. | 03-19-2015 |
| 375293000 | Synchronized | 8 |
| 20090028267 | Rapid re-synchronization of communication channels - A method of synchronizing a receiver with a transmitter. The method includes determining number of bits, j, for adjusting a bit stream, where the bit stream is generated from n tones and is dividable into codewords having a codeword length of N bytes, and the number of bits for adjusting the bit stream is determined based upon n and N. The method includes detecting a loss of synchronization indication. In response to detection of the loss of synchronization indication, the method includes adjusting the bit stream by j bits. The method includes determining whether synchronization has been regained. When synchronization has not been regained, the method includes adjusting the bit stream again by j bits. When synchronization has been regained, the method includes terminating adjustment of the bit stream. | 01-29-2009 |
| 20090041154 | APPARATUS FOR TRANSMITTING SIGNAL IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block. | 02-12-2009 |
| 20100027710 | INFORMATION PROCESSING DEVICE AND BIDIRECTIONAL TRANSMISSION METHOD - In a provided information processing device, a first information processing module, within its transmission time segment, transmits an encoded signal in which mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the same amplitude value not occurring consecutively and the amplitude value polarity being inverted with each cycle. Within a transmission time segment for a second information processing module, the first information processing module transmits a clock signal that corresponds to the cycle at which the polarity is inverted. The second information processing module extracts the clock signal by detecting the polarity inversions in the encoded signal, decodes the first and second bit values from the encoded signal using the clock signal, generates a transmission signal by controlling the amplitude values of the clock signal, and transmits the transmission signal in synchronization with the clock signal. | 02-04-2010 |
| 20100329381 | SIGNAL PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS, MULTILEVEL CODING METHOD, AND DATA TRANSMISSION METHOD - Provided is a signal processing apparatus including an encoder for encoding, according to respective specific coding schemes, a first bit string formed from bit values at odd-numbered positions and a second bit string formed from bit values at even-numbered positions that are obtained by alternately extracting bit values from a bit string that is expressed by mutually different first and second bit values, and generating first and second encoded signals that do not include a DC component, and a signal generation unit for generating a multilevel signal by respectively adding, to a clock signal having larger amplitude than the first and second encoded signals that are generated by the encoder, the first encoded signal in synchronization with a timing of the clock signal being at a positive amplitude value and the second encoded signal in synchronization with a timing of the clock signal being at a negative amplitude value. | 12-30-2010 |
| 20140307826 | SYSTEMS AND METHODS FOR FILTERING A RECEIVED SIGNAL TO REMOVE INTERSYMBOL INTERFERENCE - A communication device including circuitry configured to receive a signal transmitted to the communication device via a communication channel. A receiver is configured to generate a filter coefficient to be used for filtering the received signal, generate a gain coefficient, wherein the gain coefficient corresponds to a condition of the communication channel, adjust the filter coefficient using the gain coefficient, and filter the received signal using the filter coefficient, as adjusted using the gain coefficient, to remove intersymbol interference from the received signal. | 10-16-2014 |
| 375294000 | Phase locked loop | 3 |
| 20090141825 | Multiband PLL Arrangement and a Method of Controlling Such Arrangement - The present invention relates to a multiband PLL arrangement comprising a single loop PLL, with a phase/frequency detecting means ( | 06-04-2009 |
| 20090323853 | 4X OVER-SAMPLING DATA RECOVERY METHOD AND SYSTEM - A 4× over-sampling data recovery system consists of a charge pump PLL, a 4× over-sampler, a data regenerator and a digital PLL. The charge pump PLL receives a clock signal and generates a plurality of multiplicative clock signals in response to the clock signal. The 4× over-sampler samples a serial data to generate a M-bit signal according to the plurality of multiplicative clock signals, wherein each bit in the serial data is sampled for four times. The data regenerator sequentially receives and combines two M-bit signals to generate a (M+N)-bit signal. The digital PLL divides the (M+N)-bit signal into (N+1) groups of M-bit data and selects a designated M-bit data from the (N+1) groups of M-bit data to generate a P-bit recovery data. | 12-31-2009 |
| 20100067612 | Frequency synthesis system with self-calibrated loop stability and bandwidth - A frequency synthesis system with self-calibrated loop stability and bandwidth, which outputs an output signal based on an input signal and includes a detector, a charge pump, a filter, a controllable oscillator and a programmable frequency divider. The detector produces a detection signal based on a logic level difference between the input signal and a feedback signal. The charge pump is connected to the detector in order to produce a control signal based on the detection signal. The filter is connected to the charge pump in order to produce a tuning signal based on the control signal. The controllable oscillator is connected to the filter in order to produce the output signal based on the tuning signal. The programmable frequency divider is connected to the controllable oscillator in order to produce the feedback signal based on the output signal. The filter is a discrete time loop filter. | 03-18-2010 |
