| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 370516000 | Adjusting for phase or jitter | 70 |
| 20080219296 | Method of Transmitting Mpeg Streams Over Ip and Corresponding Device, Receiving Method and Receiver - The invention concerns a method of transmitting, via a sending device, a data stream made up of data packets, at least some of these packets including time references for synchronizing the clocks of the sender and the receiver. The method includes at least a correction of the time references by the sender so as the receiver can offset the jitter introduced by the transmission. The invention is used to offset these losses of accuracy. The invention concerns also the device and corresponding receiver and reception method. | 09-11-2008 |
| 20080240168 | PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING - Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed. | 10-02-2008 |
| 20080240169 | METHOD, SYSTEM AND DEVICE FOR CLOCK TRANSMISSION BETWEEN SENDER AND RECEIVER - Embodiments of the present invention provide a method, system and device for clock transmission between a sender and a receiver. The sender generates clock information of a clock to be sent relative to a system clock and sends a data packet containing the clock information to the receiver over a Packet-Switched Network (PSN). The receiver obtains the clock information in the data packet received and obtains the clock sent by the sender according to the clock information and the system clock. According to the embodiments of the present invention, after the clock of the sender is transmitted over the PSN, the receiver may obtain the clock of the sender without being affected by such damage as a network delay jitter and a packet loss. | 10-02-2008 |
| 20080267224 | METHOD AND APPARATUS FOR MODIFYING PLAYBACK TIMING OF TALKSPURTS WITHIN A SENTENCE WITHOUT AFFECTING INTELLIGIBILITY - Adaptive De-Jitter Buffer for Voice over IP (VoIP) for packet switched communications. The de-jitter buffer methods and apparatus presented modify the playback of packets dependent upon whether silence periods are detected inter-sentence or intra-sentence to optimize voice quality in a communication system. In one example, a de-jitter buffer determines the length of at least one silence period associated with a plurality of received packets and determines a time to transmit a portion of the packets based on the determined length of the silence period. In another example, a silence characterizer unit performs this function. | 10-30-2008 |
| 20080285598 | PHASE ROTATOR FOR DELAY LOCKED LOOP BASED SERDES - An apparatus comprising a first multiplexer circuit (MUX) to receive a plurality of clock phase signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a phase delay circuit to receive the output of the first MUX and to generate adjusted first and second clock signals that have reduced phase error with respect to detected edges of incoming data, an output MUX to receive the adjusted first and second clock signals and to output a recovered clock signal, and a control circuit coupled to output MUX select inputs. The control circuit includes logic circuitry to select the first adjusted clock signal as the recovered clock signal and to select the second adjusted clock signal as the recovered clock signal when the first adjusted clock signal nears a phase limit due to drift of the detected data edges. Other devices and methods are disclosed. | 11-20-2008 |
| 20080285599 | Control Mechanism for Adaptive Play-Out with State Recovery - A control logic means preferably for a receiver comprising a jitter buffer means adapted to receive and buffer incoming frames or packets and to extract data frames from the received packets, a decoder connected to the jitter buffer means adapted to decode the extracted data frames, and a time scaling means connected to the decoder adapted to play out decoded speech frames adaptively. The control logic means comprises knowledge of whether a state recovery function is available and is adapted to retrieve at least one parameter from at least one of the jitter buffer means, the time scaling means, and the decoder, to adaptively control at least one of an initial buffering time of said jitter buffer means, the knowledge of the availability of the state recovery function, and a time scaling amount of said time scaling means from the time scaling means or the decoder. | 11-20-2008 |
| 20090034560 | Generating And Operating A Double Temporal Descriptor For Transmitting A Synchronizing Signal In A Packet Network - The invention concerns device for transmitting packets in a packet communication network comprising at least two stations, including in particular means for generating a first temporal descriptor from a sampled value of a master counter, means for generating a second temporal descriptor from a sampled value of a second counter synchronized on all the network stations and means for transmitting jointly the two temporal descriptors in the network. The invention also concerns a device for receiving packets in a packet communication network, which uses the double temporal descriptor generated by the transmitter device. | 02-05-2009 |
| 20090074012 | BUFFERING A MEDIA STREAM - An apparatus and method of buffering a media stream is provided. The method may comprise receiving a plurality of IP packets of the media stream, each packet providing a fragment of a portion of the media stream. Thereafter, the portion of media stream may be buffered in a jitter buffer using the fragments provided by the received packets. Further, the portion of the media stream may be buffered in a replay buffer using the fragments provided by the received packets. The replay buffer may be larger than the jitter buffer and a first received fragment and a second received fragment may be combined. The second received fragment may have been discarded by the jitter buffer. A media stream may then be played back using media from the replay and/or jitter buffer. | 03-19-2009 |
| 20090097506 | Multiservice system and method for packet and time division multiplexed transport - A system and method are presented for providing packet and time division multiplex (TDM) services in a data communication interface. The method accepts packets at a first rate over a packet interface, and transfers time-sensitive data in the packets as packet data units (PDUs) having a smaller number of bits than a packet and a second rate, faster than the first rate. The method transforms the PDUs into frames in a first TDM protocol. Typically, the PDUs are transformed into units having a smaller number of bits than the PDU and a third rate, faster than the second rate. Then, the TDM frames are transmitted over a line interface. | 04-16-2009 |
| 20090190614 | JITTER BUFFER ADAPTATION BASED ON AUDIO CONTENT - A system and method for discarding or inserting audio frames in a jitter buffer is described. The system and method provides improved audio quality as compared to conventional jitter buffer management systems. In one embodiment, buffer control logic determines whether to discard audio frames to be stored in a jitter buffer or to insert audio frames among audio frames to be output from a jitter buffer based not only on the number of audio frames currently stored in the jitter buffer but also based on the power of the current audio frame to be stored in or output from the jitter buffer. The system and method is generally applicable to any wireless or wired communication system in which audio signals are transmitted between entities operating in different clock domains. | 07-30-2009 |
| 20090304032 | REAL-TIME JITTER CONTROL AND PACKET-LOSS CONCEALMENT IN AN AUDIO SIGNAL - An “adaptive audio playback controller” operates by decoding and reading received packets of an audio signal into a signal buffer. Samples of the decoded audio signal are then played out of the signal buffer according to the needs of a player device. Jitter control and packet loss concealment are accomplished by continuously analyzing buffer content in real-time, and determining whether to provide unmodified playback from the buffer contents, whether to compress buffer content, stretch buffer content, or whether to provide for packet loss concealment for overly delayed or lost packets as a function of buffer content. Further, the adaptive audio playback controller also determines where to stretch or compress particular frames or signal segments in the signal buffer, and how much to stretch or compress such segments in order to optimize perceived playback quality. | 12-10-2009 |
| 20100027567 | JITTER BUFFER CONTROL METHOD AND COMMUNICATION APPARATUS - Disclosed is an apparatus comprising a jitter buffer that writes and reads packets transmitted via a packet network from a transmission node, a clock correction unit that obtains an inter-packet jitter, based on difference information between time stamp information at the time of reception of the packet on a receiving side and time stamp information attached to the packet at the time of transmission of the packet by a transmission node with regards to packets received before and after and obtains a transmission frequency and a PLL unit that receives frequency information from the clock correction unit and generates a clock of the frequency. A scheduler uses a frequency from the PLL unit as a transmission frequency to transmit a packet from the jitter buffer unit. | 02-04-2010 |
| 20100040092 | RECEIVER FOR REDUCING PCR JITTER - A receiver receiving a transport stream to demodulate the transport stream into a final output stream, wherein the transport stream comprises a plurality of symbols at least one of which carrying at least one program clock reference (PCR) value, and the final output stream comprises a plurality of demodulated symbols each comprising a plurality of packets, is disclosed. The receiver can comprise a Reed-Solomon decoder configured to decode the transport stream to generate a MPEG (Motion Pictures Expert Group) packet, a MPEG memory configured to store the MPEG packet, and a descrambler configured to read the MPEG packet from the MPEG memory with a throughput rate and descramble the MPEG packet into one of the packets of the demodulated symbols of the final transport stream. The throughput rate is decreased to reduce bursts of the packets of the demodulated symbols of the final output stream. | 02-18-2010 |
| 20100195673 | METHOD AND DEVICE FOR AUTOMATICALLY COMPENSATING A PHASE SHIFT ON A SYNCHRONISATION SIGNAL RECEIVED BY AN ITEM OF REMOTE EQUIPMENT - The present invention relates to the domain of video equipment. In particular, the invention relates to a device able to receive packets in a network. The device comprises:
| 08-05-2010 |
| 20100195674 | REDUCTION IN THE ACQUISITION DURATION OF A PHASE-LOCKED LOOP ABLE TO RECONSTITUTE A SYNCHRONISATION SIGNAL TRANSMITTED OVER AN IP NETWORK - The present invention relates to the domain of video equipment. More specifically, it concerns a reception device that comprises the means for:
| 08-05-2010 |
| 20100246608 | Jitter buffering control for controlling storage locations of a jitter buffer, and a method therefor - A jitter buffer control apparatus has a buffer for storing data included in an input packet transmitted from a telecommunications network, and a jitter buffer controller for controlling the buffer to store the input data into the buffer and take out the stored data from the buffer on the basis of a sequence number included in the input packet in a processing period. When under-running occurs in the buffer, the jitter buffer controller stores input data into the buffer with a storage location skipped which corresponds to the processing period associated with packet loss due to the under-running. | 09-30-2010 |
| 20100296524 | MULTI INPUT TIMING RECOVERY OVER PACKET NETWORK - In a method of recovering timing information over packet networks, a receiver receives a plurality of packet streams over different paths from the same source. The raw delays experienced by the timing packets for each stream are filtered to provide a filtered delay for each stream. The filtered delays are weighted based on the quality of each stream, and the weighted filtered delays are then combined to form an aggregate delay estimate. Frequency adjustments for a local clock at the receiver are derived from the aggregate delay estimate. | 11-25-2010 |
| 20100296525 | Simple Adaptive Jitter Buffering Algorithm For Network Nodes - A method of dynamically adjusting the buffer delay of an adaptive jitter buffer of a network node receiving packets of a media stream from a packet switched network. The method comprises inserting packets arriving to the network node into the jitter buffer and executing a jitter buffering procedure once every Trep | 11-25-2010 |
| 20110044357 | SYSTEM AND METHOD FOR HIGH PRECISION CLOCK RECOVERY OVER PACKET NETWORKS - An improved system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter, such as noise jitter and other “singular” anomalies causing latency deviations. Minimum network delay is defined herein as the time delay in which a packet remains in the network under assumption that all transmission queues through which the packet passes are empty. The proposed system and method perform clock recovery by including an improvement in the form of dynamically varying thresholds. Reconstruction of the clock signal is performed in accordance with the minimum network delay estimation based on an adjustable threshold, i.e., the latency change threshold, which increases when the noise threshold increases and decreases when the noise threshold decreases. This allows detection of latency changes in accordance with the dynamically varying network conditions and avoids false latency change detections. | 02-24-2011 |
| 20110158264 | LOW-JITTER END-TO-END LATENCY CONTROL SCHEME FOR ISOCHRONOUS COMMUNICATIONS BASED ON TRANSMITTER TIMESTAMP INFORMATION - A latency control mechanism for a communication system provides a known constant end-to-end delay between an audio source and one or more end node destinations, even in the case where different paths are used to reach the end nodes. A very low jitter time on the end-to-end latency is obtained, and the latency is controllable within a given range in dependence on the constraints imposed by the implementation. A block RX DPLL and latency control unit adjusts the reading moment and position from the RX buffer so that a delay between the time stamp taken at the source side by the transmitter time stamp unit, and the time stamp taken at the receiver side by receiver time stamp unit is constant and equal to a given value. | 06-30-2011 |
| 20110164630 | ADAPTIVE CLOCK RECOVERY WITH STEP-DELAY PRE-COMPENSATION - An adaptive clock recovery (ACR) subsystem processes an input phase signal indicative of jittery packet arrival times to generate a relatively smooth and bounded output phase signal that can be used to generate a relatively stable recovered clock signal. The input phase signal is also processed to detect and measure step-delays corresponding, for example, to path changes in the network routing of the packets. Step-delay pre-compensation is performed, in which the input phase signal is phase-adjusted, upstream of the ACR subsystem, based on the sign and magnitude of each detected step-delay. As a result, the ACR subsystem is substantially oblivious to the existence of such step-delays. | 07-07-2011 |
| 20120057606 | MULTIPLEXER CIRCUIT - According to an example embodiment, a circuit may include a first pair of differential input transistors, each coupled between at least an associated first positive clock transistor and ground; the first positive clock transistors coupled between differential output nodes and the differential input transistors associated with the first positive clock transistors, the first positive clock transistors being configured to respond to a positive input from a clock; a first inductor coupled between the differential output nodes and a voltage source; a second pair of differential input transistors, each coupled between at least an associated first negative clock transistor and ground; the first negative clock transistors coupled between the differential output nodes and the differential input transistors associated with the first negative clock transistors, the first negative clock transistors being configured to respond to a negative input from the clock; and the differential output nodes coupled between the first inductor, the first positive clock transistors, and the first negative clock transistors. | 03-08-2012 |
| 20130028272 | COMMUNICATION APPARATUS, PACKETIZATION PERIOD CHANGE METHOD, AND PROGRAM - To provide a communication apparatus and a packetization period change method that allow a packetization period/TDM period to change during a service of a TDM-PW system without affecting the service traffic, there is provided a communication apparatus that receives packetized data converted from TDM data, including a period information detection unit, a jitter buffer that stores the packetized data for a certain period of time, and a jitter buffer capacity control unit. The period information detection unit extracts packetization period information indicating a period to packetize TDM data contained in the received packetized data and acquires a TDM period to time-division multiplex the packetized data based on the packetization period information. The jitter buffer capacity control unit receives the acquired TDM period and controls a capacity of the jitter buffer in accordance with the TDM period. | 01-31-2013 |
| 20130188657 | Automatic Synchronization of a Transmitter - An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module. | 07-25-2013 |
| 20130235889 | DIFFERENTIAL TIMING TRANSFER OVER SYNCHRONOUS ETHERNET USING DIGITAL FREQUENCY GENERATORS AND CONTROL WORD SIGNALING - Transfer of differential timing over a packet network is provided. A transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface. | 09-12-2013 |
| 20130279525 | Ring Based Precise Time Data Network Clock Phase Adjustments - Clock phase errors are detected and adjusted in a network with loop back connections for clock signals. In one embodiment, a method is performed in a ring network with slave clock nodes. A timing packet is sent from the master clock node to a first slave clock node of the ring. A timing packet is received from a last slave clock node of the ring. A phase alignment offset is determined by comparing a recovered time from the received timing packet with the time of the master clock node local clock and a phase correction value is determined for the slave clock nodes based on the determined phase alignment offset. A phase correction packet including the phase correction value is then sent from the master clock node to at least one of the slave clock nodes. | 10-24-2013 |
| 20130287049 | MEMORY DEVICE WITH INTERNAL SIGNAL PROCESSING UNIT - A communications network includes multiple distributed nodes that are coupled by a circuit-switched network. To improve efficiency, a plurality of the nodes are associated with a single source synchronization block that injects timing messages over circuits in the circuit-switched network to the plurality of nodes. Each of the plurality of nodes is associated with a timing extraction and recovery block that extracts information from the timing messages injected by the source synchronization block to synchronize a local clock in each node to the frequency and phase of a clock received by the source synchronization block. | 10-31-2013 |
| 20130294463 | NETWORK JITTER SMOOTHING WITH REDUCED DELAY - A method of compensating for jitter in a packet stream is described. The method comprises placing undecoded frames extracted from packets in the packet stream into a jitter buffer while decoding frames from the jitter buffer and placing the decoded frames into a sample buffer at a rate determined using an average playout delay. The average playout delay is the running average of the playout delay calculated for each packet as each packet becomes available. The playout delay for each packet is the sum of a sample buffer delay and a jitter buffer delay. As each packet is received, the average playout delay is adjusted based on a comparison of the playout delay associated with the received packet to the current average playout delay. | 11-07-2013 |
| 20130294464 | SIGNAL MULTIPLEXING DEVICE - A signal multiplexing device includes a selector ( | 11-07-2013 |
| 20130301659 | FLOW CONTROL IN A NETWORK DEVICE - “A process of scheduling stream packets for output from a multiplexing network device involves prioritizing the output of packets first according to stream priority, and within a particular priority, by stream ID.” | 11-14-2013 |
| 20130315265 | System And Method For Direct Passive Monitoring Of Packet Delay Variation And Time Error In Network Packet Communications - Systems and methods are disclosed for direct passive monitoring of packet delay variation and time error in network packet communications. Packets traversing between slave and master clocks are monitored to provide direct results of the actual conditions without the need to rely upon inference determinations. Certain embodiments provide tap configurations to monitor packet flows, while certain other embodiments provide in-line configurations to monitor packet flows. Certain further embodiments provide multiple monitoring devices that can be used for passive monitoring purposes, such as passive monitoring to test boundary clock. These multiple monitoring devices can be configured to be within a single or different test instruments. Other variations are also described. | 11-28-2013 |
| 20140016654 | CAN COMMUNICATION SYSTEM, CAN TRANSMISSION APPARATUS, CAN RECEPTION APPARATUS, AND CAN COMMUNICATION METHOD - A CAN communication system of the present invention includes: a transmission apparatus that transmits transmission data instead of the bit data protocol, the transmission data being data in which a stuff bit having an inverted value of the same logical value has been inserted next to the predetermined number of continuous bits having the same logical value in the bit data; a reception apparatus that synchronizes transmission and reception of the transmission data to and from the transmission apparatus according to detection of an edge from the second logical value to the first logical value in the transmission data transmitted from the transmission apparatus. The transmission apparatus has a transmission control unit that rewrites to the first logical value any of the predetermined number −1 of bits continuing from the predetermined number of continuous bits having the first logical value in the bit data. | 01-16-2014 |
| 20140072000 | ADAPTIVE JITTER BUFFER MANAGEMENT FOR NETWORKS WITH VARYING CONDITIONS - An apparatus and method for detecting and analyzing spikes in network jitter and the estimation of a jitter buffer target size is disclosed. Detected spikes may be classified as jump spikes or slope spikes, and a clipped size of detected spikes may be used in the estimation of the jitter buffer target. Network characteristics and conditions may also be used in the estimation of the jitter buffer target size. Samples may be modified during playback adaptation to improve audio quality and maintain low delay of a receive chain. | 03-13-2014 |
| 20140119391 | APPARATUS AND METHOD FOR SYNCHRONIZING CLOCKS AMONG COMMUNICATION DEVICES - A packet transmission device includes first and second clocks, a communication unit, and first and second synchronization processing units. The communication unit transmits and receives a synchronization packet to and from an external time source device. The first synchronization processing unit synchronizes the first clock with the external time source device in accordance with time information of the synchronization packet. The second synchronization processing unit synchronizes the second clock with the first clock. | 05-01-2014 |
| 20140126587 | INTERFACE CIRCUIT FOR TRANSMITTING AND RECEIVING DIGITAL SIGNALS BETWEEN DEVICES - A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit. | 05-08-2014 |
| 20140269782 | APPARATUS FOR COMPENSATING FOR SKEW BETWEEN DATA SIGNALS AND CLOCK SIGNAL - An apparatus for compensating for a skew is provided between data signals supplied through a plurality of data lines and a clock signal supplied through a clock line. A skew compensation apparatus includes a plurality of data receivers each configured to delay a data signal supplied through a corresponding data line based on associated phase difference data and to output the delayed data signal, a clock receiver configured to receive a clock signal supplied through a clock line, and a phase controller configured to select any one of the plurality of data receivers and to output, to the selected data receiver, a phase control signal configured to correct the phase difference data of the selected data receiver based on the phase difference between a data signal output from the selected data receiver and the clock signal. | 09-18-2014 |
| 20140286359 | APPARATUS AND CIRCUIT FOR PROCESSING CARRIER AGGREGATION - A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock. | 09-25-2014 |
| 20150071310 | RADIO MEASUREMENT METHOD AND RADIO MEASUREMENT APPARATUS USING MULTI-ANTENNA CHANNEL MULTIPLEX - A radio measurement apparatus comprising: an array antennal selection unit selecting array antennas corresponding to received signals; a reference path selection unit selecting a reference array antenna; a signal processing unit selecting a reference antenna channel through analysis of signal characteristics measured through two reception channels; a sequential channel multiplex unit determining sequentially inputting received signals of remaining array antennas to output the sequentially input signals to a receiver; and a correction signal input unit compensating amplitude and phase characteristics of the respective reception channels. | 03-12-2015 |
| 20150092796 | METHOD AND DEVICES FOR TIME AND FREQUENCY SYNCHRONIZATION - This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a recursive least squares mechanism for clock offset and skew estimation. A major potential advantage of such estimation is that it does not require knowledge of the statistics of the measurement noise and process noise. An implementation using a digital phase locked loop based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client) is also provided. | 04-02-2015 |
| 20150092797 | METHOD AND DEVICES FOR TIME AND FREQUENCY SYNCHRONIZATION USING A PHASE LOCKED LOOP - This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided. | 04-02-2015 |
| 20150110134 | Adapting a Jitter Buffer - A receiver receives a first data stream and a second data stream from a transmitting device over a packet-based communication network, the first data stream being of a first media type (e.g. audio) and the second data stream being of a second media type (e.g. video). The first jitter buffer will buffer each of a plurality of portions of the first data stream as they are received via the receiver, and apply a de-jittering delay before outputting each portion of the first data stream (e.g. audio stream) to be played out through the receiving device. The jitter buffer controller receives information on the second data stream (e.g. video stream), and adapts the de-jittering delay of the first jitter buffer (e.g. audio jitter buffer) in dependence on the information on the second data stream (e.g. information on the video stream). | 04-23-2015 |
| 20150117472 | METHOD AND SYSTEM FOR CLOCK SYNCHRONIZATION - A method and system is provided for clock synchronization between two devices comprising a clock. The method comprises the following steps: a step of determining a duration necessary for transmission of a data packet between the two devices, a step of sending by one of the devices a data packet containing a sending time of this packet, and a step of determining the time by the other device by adding the transmission duration to the sending time of the packet. | 04-30-2015 |
| 20150124843 | SHORTENED TRAINING FIELD PREAMBLE STRUCTURE FOR HIGH EFFICIENCY WI-FI ENVIRONMENT - The disclosure generally relates to a shortened training field preamble structure for high-efficiency Wi-Fi environments. In one embodiment, the disclosure relates to a communication system having a transmitter transmitting a Master-Sync packet received by stationary and mobile receivers. The Master-Sync packet contains information for communicating in a HEW environment. Upon receipt each receiver decodes the Master-Sync packet to (i) estimate a frequency offset and/or an automatic gain control (AGC) setting; (ii) select a transmission frequency consistent with the frequency offset; and/or (iii) determine a new transmission power consistent with the AGC; (iv) tune to a new frequency offset and gain control setting to receive subsequent packets from the transmitter. | 05-07-2015 |
| 20150139252 | DATA SERIALIZER - A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal. | 05-21-2015 |
| 20150381298 | System And Method For Direct Passive Monitoring Of Packet Delay Variation And Time Error In Network Packet Communications - Systems and methods are disclosed for direct passive monitoring of packet delay variation and time error in network packet communications. Packets traversing between slave and master clocks are monitored to provide direct results of the actual conditions without the need to rely upon inference determinations. Certain embodiments provide tap configurations to monitor packet flows, while certain other embodiments provide in-line configurations to monitor packet flows. Certain further embodiments provide multiple monitoring devices that can be used for passive monitoring purposes, such as passive monitoring to test boundary clock. These multiple monitoring devices can be configured to be within a single or different test instruments. Other variations are also described. | 12-31-2015 |
| 20150381323 | User Defined Protocol for Zero-Added-Jitter and Error Free Transmission of Layer-2 Datagrams Across Lossy Packet-Switched Network Links - A zero-added-jitter protocol for transmission of datagrams over packet-switched networks between two or more connected microprocessor devices with negligible packet delay variation and negative acknowledgment datagram recovery. A method for the analysis and preservation of the instantaneous bitrate and packet spacing provides for the output of the datagrams to a network facing provider edge device matching in timing and inter-packet spacing, that which was originally received, along with a pre-configured time-delay for error correction. Additional embodiments provide duplication of path for reduction of re-requests; the splitting of path for faster transport between transmitter and receiver; encryption for more secure transport between transmitter and receiver; compression for more efficient transport between transmitter and receiver; and encryption and compression, for more secure, efficient transport between transmitter and receiver. | 12-31-2015 |
| 20160056948 | COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS - A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component. | 02-25-2016 |
| 20160182215 | JITTER REMOVAL IN DETERMINISTIC NETWORKS | 06-23-2016 |
| 370517000 | Including delay device | 22 |
| 20080205455 | Wireless Communication System and Communication Apparatus - A data-transmission-side communication apparatus includes a mapping unit that executes a mapping for a data sub-carrier based on a multipath delay time in a transmission path and a guard-band adding unit that changes an amount of a guard band to be added to a signal on the data sub-carrier depending on information on the guard band obtained based on the multipath delay time. A data-reception-side communication apparatus includes an equalizing unit that suppresses a multipath exceeding a guard interval based on the information on the guard band and a demapping unit that executes a demapping for an equalized signal based on the multipath delay time. | 08-28-2008 |
| 20080240170 | Systems and methods for digital delayed array transmitter architecture with beam steering capability for high data rate - Embodiments include systems and methods for fine control of beam steering for wide band wireless applications using a phased array of antenna elements. In one embodiment, a digitally controlled delay line delays the signal output from a modulator in each branch of multiple branches feeding multiple antennas in an array. An output of the digital delay line is input to a digital to analog converter. A second digital delay line also delays the signal within the digital to analog converter. The manner of implementation of the delays enables accurate production of a steered beam at a high data rate. | 10-02-2008 |
| 20100085990 | Systems and methods for a network device to update timing packets to reflect delay - Systems and methods for a network device to update timing packets to reflect delay are provided. A timing packet processor is externally connected to the network device. All timing packets are processed by the timing packet processor. The timing packets are updated to reflect an estimate of delay introduced by the network device. | 04-08-2010 |
| 20120243560 | System, Apparatus, and Method for Time-Division Multiplexed Communication - A simplified bus arrangement using only three signal lines allows TDM data to be conveyed to or from a number of slave-only devices without the use of separate command line(s) and without any of the slave-only devices having to operate as a bus master or even support a master operating mode. | 09-27-2012 |
| 20130010815 | Apparatus and Method of Compensating for Clock Frequency and Phase Variations by Processing Packet Delay Values - An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated. | 01-10-2013 |
| 20130100968 | JITTER BUFFER - Method, transmitter and computer program product for transmitting data of a real-time communication event from the transmitter to a jitter buffer of a receiver. The method comprises jointly determining (i) at least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer, and (ii) jitter buffer control information for indicating to the receiver how to control a state of the jitter buffer. The jitter buffer control information is transmitted to the receiver. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. The processed data is transmitted from the transmitter to the jitter buffer of the receiver. | 04-25-2013 |
| 20130100969 | JITTER BUFFER - Methods, transmitter, receiver and computer program product for transmitting or receiving data of a real-time communication event, the data being transmitted from the transmitter to a jitter buffer of the receiver. At least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event is determined at the transmitter. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. Control information based on the determined at least one processing parameter is transmitted from the transmitter to the receiver, wherein the control information is for use by the receiver to control a state of the jitter buffer. The processed data is transmitted from the transmitter to the jitter buffer of the receiver in the real-time communication event. | 04-25-2013 |
| 20130100970 | JITTER BUFFER - Method, transmitter and computer program product for transmitting data of a real-time communication event from the transmitter to a jitter buffer of a receiver. Jitter buffer state information is received at the transmitter from the receiver, the jitter buffer state information indicating a state of the jitter buffer. At least one processing parameter is controlled based on the received jitter buffer state information, the at least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. The processed data is transmitted from the transmitter to the jitter buffer of the receiver in the real-time communication event. | 04-25-2013 |
| 20130315266 | SNR IMPROVEMENT CIRCUIT, SYNCHRONIZATION INFORMATION DETECTION CIRCUIT, COMMUNICATION DEVICE, SNR IMPROVEMENT METHOD, AND SYNCHRONIZATION INFORMATION DETECTION METHOD - A technique capable of improving a packet catch rate when applied to a communication device, for example. An SNR improvement circuit for improving an SNR of an input signal includes a delay unit for delaying the input signal to generate one or more delay signals, and an adder for adding the one or more delay signals and the input signal before being delayed. The input signal contains a periodic signal in which the same signal is repeated a predetermined number of times with a predetermined period. The delay unit generates the one or more delay signals with delay time which is α times (α is a natural number, and is set at different values with respect to two or more delay signals) longer than the predetermined period. | 11-28-2013 |
| 20140112356 | Hybrid Timing Recovery for Burst Mode Receiver in Passive Optical Networks - An apparatus for coarse phase alignment of an analog signal comprising: a tapped delay line, a coarse phase alignment logic circuit coupled to the tapped delay line, and a selector coupled to the tapped delay and the coarse phase alignment logic circuit. An apparatus for timing and data recovery for burst mode receivers comprising: a receiver, a coarse phase alignment circuit coupled to the receiver, at least one analog to digital converter (ADC) coupled to the coarse phase alignment circuit such that the coarse phase alignment circuit is positioned between the receiver and the ADC, and a fine phase alignment circuit coupled to the ADC such that the ADC is positioned between the coarse phase alignment circuit and the fine phase alignment circuit, wherein the fine phase alignment circuit produces a recovered data output. | 04-24-2014 |
| 20140153591 | Packet Delay Distribution Rate Filtering - To test the timing-recovery process of a receiving (i.e., slave) node in a packet-based network, a packet filter is configured in a test configuration that already contributes a natural delay distribution to the packet flow arriving at the slave node. The resulting delay distribution of the arriving packet flow is the combination of that natural delay distribution and the effects of the packet filter, which deterministically or statistically reduces the number of packets with delays within the anchor value window arriving at the slave node (i.e., received packets having packet delays within the slave node's anchor value window). The packet filter can be adjusted to test the slave node's timing-recovery process for a wide variety of packet-flow conditions (e.g., different rates of packets with delays within the anchor value window). | 06-05-2014 |
| 20140185633 | FLEXIBLE THRESHOLD COUNTER FOR CLOCK-AND-DATA RECOVERY - One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two. | 07-03-2014 |
| 20140269783 | LOW-POWER AND ALL-DIGITAL PHASE INTERPOLATOR-BASED CLOCK AND DATA RECOVERY ARCHITECTURE - The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required. | 09-18-2014 |
| 20150063376 | DATA PROCESSING - In a telecommunications network including at least a user device and a network node separated by at least a packet-switched part of the telecommunications network, the user device including a primary jitter buffer having a constant packet play-out rate, the network node including a secondary jitter buffer, incoming packets destined for the user device are received and passed through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device. The departure times of packets passing through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device are monitored. On the basis of the monitoring and one or more known characteristics of the primary jitter buffer, an estimate of a current state of the primary jitter buffer is maintained. Operation of the secondary jitter buffer is dynamically controlled according to the maintained estimate. | 03-05-2015 |
| 20150063377 | CONFIGURABLE CLOCK TREE - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A configurable clock tree includes a delay matrix that may be configured such that each the timing of clocks for each of a plurality of data lanes can be optimized for minimum skew. Selections between different versions of a base clock signal and different paths available to the selected version may provide a root clock used for transmitting data on a communications link. The versions of the one or more clock signals may include three versions of a first clock signal. Each version of the first clock signal may be subject to a different delay with respect to the clock signal. | 03-05-2015 |
| 20150110135 | Jitter Buffer - Methods, transmitter, receiver and computer program product for transmitting or receiving data of a real-time communication event, the data being transmitted from the transmitter to a jitter buffer of the receiver. At least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event is determined at the transmitter. Data is processed for transmission from the transmitter to the jitter buffer in accordance with the determined at least one processing parameter. Control information based on the determined at least one processing parameter is transmitted from the transmitter to the receiver, wherein the control information is for use by the receiver to control a state of the jitter buffer. The processed data is transmitted from the transmitter to the jitter buffer of the receiver in the real-time communication event. | 04-23-2015 |
| 20160013926 | APPARATUSES AND METHODS FOR REDUCING SWITCHING JITTER | 01-14-2016 |
| 370518000 | Provide plural phases of a clocking signal | 3 |
| 20130308660 | METHOD OF ADJUSTING A LOCAL CLOCK IN ASYNCHRONOUS PACKET NETWORKS - In a computer-implemented method of adjusting a local clock at a receiver in a packet network, the local clock is generated by a phase locked loop locked to a master clock with the aid of time-stamped timing packets arriving over the network from the master clock with a packet delay distribution about a nominal delay. The timing packets are filtered to adjust for the packet delay distribution. A control input for the phase locked loop is derived from the timing packets. The amount of skew in the packet delay distribution about the nominal delay is determined, and the arrival times of timing packets are then selectively modified to correct for the amount of skew in the packet delay variation distribution prior to filtering the timing packets. | 11-21-2013 |
| 20150381338 | LATENCY-OPTIMIZED PHYSICAL CODING SUBLAYER - Method and apparatus for reducing latency in a networking application comprises receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, wherein the MAC sublayer utilizes a first clock domain operating at a first clock frequency. The method further comprises performing one or more functions in the PCS on the data in the first clock domain. The method also includes transmitting the data on one or more physical medium attachment (PMA) lanes, wherein the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio. The method also comprises performing one or more functions in the PCS on the data in the second clock domain. | 12-31-2015 |
| 20150381339 | LATENCY-OPTIMIZED PHYSICAL CODING SUBLAYER - Method and apparatus for reducing latency in a networking application comprises receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, wherein the MAC sublayer utilizes a first clock domain operating at a first clock frequency. The method further comprises performing one or more functions in the PCS on the data in the first clock domain. The method also includes transmitting the data on one or more physical medium attachment (PMA) lanes, wherein the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio. The method also comprises performing one or more functions in the PCS on the data in the second clock domain. | 12-31-2015 |
| 370519000 | Delay based upon propagation delay time | 2 |
| 20130301660 | Apparatus and Method of Compensating for Clock Frequency and Phase Variations by Processing Packet Delay Values - An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated. | 11-14-2013 |
| 20150124844 | CLOCK SYNCHRONIZATION SYSTEM, CLOCK SYNCHRONIZATION METHOD, AND STORAGE MEDIUM WHEREUPON CLOCK SYNCHRONIZATION PROGRAM IS STORED - A slave node ( | 05-07-2015 |
