| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365208000 | Semiconductors | 29 |
| 20080205180 | Semiconductor memory device having bit-line sense amplifier - A semiconductor memory device including a bit-line sense amplifier is not affected by variation in manufacturing process and has a stable driving scheme. The semiconductor memory device includes: a unit memory cell for storing a data; a sense amplification unit including a bit-line sense amplifier (BLSA) for sensing and amplifying a voltage difference of a bit-line pair receiving the data of the unit memory cell; a variation detection unit for detecting a variation of a manufacturing process to output a detecting signal; and a sense amplifier controlling unit for controlling the BLSA to be activated after a predetermined time from an activation of unit memory cell in response to the detecting signal. | 08-28-2008 |
| 20080259707 | Semiconductor storage device - A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and one side of bit lines and switching a connecting state between the other row of sense amplifiers and the other side of bit lines; a control means which sets at least one row of sense amplifiers as a cache memory, and when performing refresh operation of the unit block where row of sense amplifiers to be used as cache memory holds data, controls switch means so that the row of sense amplifiers used as cache memory is disconnected from bit lines and only the row of sense amplifiers not used as said cache memory is used in refresh operation. | 10-23-2008 |
| 20090027986 | Semiconductor memory device - The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened. | 01-29-2009 |
| 20090180343 | SEMICONDUCTOR MEMORY DEVICE - A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation. | 07-16-2009 |
| 20090268538 | Current sensing circuit and semiconductor memory device including the same - To provide a current sensing circuit that detects a difference between a cell current and a reference current. The current sensing circuit includes: current mirror circuits of which the input terminal is connected with a reference current source; a differential amplifier of which the one input terminal is supplied with a potential of an electrical connection point between an output terminal of the current mirror circuit and a memory cell and of which the other input terminal is supplied with a reference potential; and an equalizing circuit that short-circuits the both input terminals of the differential amplifier in response to an equalizing signal. Thereby, the both input terminals can be kept at the same potential immediately before a sensing operation starts, and thus, even when the cell current is weak, a highly sensitive sensing operation can be performed at high speed. | 10-29-2009 |
| 20090279372 | SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER - In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for supplying a precharge signal to a gate of the transistor. The gate electrode of the plurality of sense amplifier portions is provided as one piece as a whole and extends in a direction parallel to a row direction in the memory cell array. A gate electrode portion which is a connected portion between the gate electrode in a k-th sense amplifier portion and the gate electrode in a (k+1)-th sense amplifier portion is ring-shaped, where k is an odd number. | 11-12-2009 |
| 20090323448 | Bias Sensing in Dram Sense Amplifiers Through Voltage-Coupling/Decoupling Device - Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased. | 12-31-2009 |
| 20100067318 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER - A sense amplifier comprises: a differential amplifier circuit configured to generate an amplified signal depending on a difference in voltage between bit lines; an output circuit receiving the amplified signal; and a load. The differential amplifier circuit comprises: a first output node supplying the amplified signal to the output circuit; and a second output node symmetrically placed with respect to the first output node and connected to the load. The output circuit comprises an output terminal for outputting an output signal generated based on the amplified signal. In response to a control signal, the load switches between a first capacitance value with which an offset voltage at the output terminal becomes a first voltage and a second capacitance value with which the offset voltage becomes a second voltage | 03-18-2010 |
| 20100182861 | SENSE AMPLIFIER WITH A COMPENSATING CIRCUIT - A sense amplifier for a memory includes a transistor, an operational amplifier, and a compensating circuit. The negative input end of the operational amplifier is coupled to the compensating circuit. The positive input end of the operational amplifier is coupled to the drain of the transistor. The output end of the operational amplifier is coupled to the gate of the transistor. The compensating circuit is coupled between the negative input end and the output end of the operational amplifier. The compensating circuit generates a compensating voltage to the negative input end of the operational amplifier according to the voltage of the gate of the transistor. | 07-22-2010 |
| 20100232244 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality of memory cells; a plurality of replica bit lines formed in the same manner as the first and second bit lines; a write buffer circuit operative to drive the first or second bit line to the ground voltage; a replica write buffer circuit operative to drive the replica bit lines to the ground voltage; and a boot strap circuit operative to drive the first or second bit line currently driven to the ground voltage further to a negative potential at a timing when the potential on the replica bit lines reaches a certain value. | 09-16-2010 |
| 20110176379 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF - A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line. | 07-21-2011 |
| 20110188333 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change. | 08-04-2011 |
| 20110267914 | SEMICONDUCTOR MEMORY DEVICE - Characteristics of both a memory cell and a peripheral circuit are degraded due to random variations, and a defective characteristic occurs in a combination of components having a substantially worst characteristic at a macro level. To solve this problem, a selector is provided between the memory cell and the peripheral circuit so that a positive phase and a negative phase of bit lines are switched at a portion where the defective characteristic occurs. Alternatively, the combination of a bit line and a sense amplifier is switched between adjacent data input/output sections, for example. In other words, the defective characteristic is repaired or corrected by canceling the combination of worst components. | 11-03-2011 |
| 20120134227 | SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER - For example, four driver transistors are arranged in wells so as to adjoin both sides of each of two element isolation regions. Two pairs of cross-coupled sense transistors are arranged in the wells at positions farther from the element isolation regions than the driver transistors are. Such an arrangement provides more than a certain distance between the sense transistors and the respective corresponding element isolation regions. This reduces the effect of a phenomenon that threshold of a transistor varies according to a distance from an element isolation region. As a result, it is possible to exactly match the characteristics of each pair of cross-coupled transistors. | 05-31-2012 |
| 20120147687 | SEMICONDUCTOR MEMORY DEVICE - A row decoder is disposed on a side of a memory cell array in a column direction and supplies one of word lines with a first drive signal for selecting one of memory cells. A dummy word line is formed extending in the column direction. A dummy bit line is formed extending in a row direction. At least one of the dummy word line and the dummy bit line is disposed outside of the memory cell array. The row decoder outputs a second drive signal toward a sense amplifier circuit via the dummy bit line and the dummy word line. | 06-14-2012 |
| 20130155798 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively. | 06-20-2013 |
| 20130163363 | SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES - Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. | 06-27-2013 |
| 20130229887 | SEMICONDUCTOR MEMORY DEVICE - In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced. | 09-05-2013 |
| 20140022857 | SEMICONDUCTOR DEVICE - A semiconductor device including a sense amplifier that includes a first transistor and a second transistor. The first transistor includes a first gate electrode formed over a first channel region and connected to a first bit line, a first diffusion region connected to a second bit line with a first side edge defining the first channel region, and a second diffusion region connected to a power line and includes a second side edge defining the first channel region. The second transistor includes a second gate electrode formed over a second channel region and connected to the second bit line, a third diffusion region connected to the first bit line and includes a third side edge defining the second channel region, and a fourth diffusion region connected to the power line with a fourth side edge defining the second channel region. Directions of the bit lines and diffusion side edges are prescribed. | 01-23-2014 |
| 20140043928 | Sense Amplifier Circuit for Nonvolatile Memory - A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the SABL node depending on the state of the sensing enable signal, a current mirror that sinks current on the SABL node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the SABL node as a data signal. | 02-13-2014 |
| 20140064007 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DIFFERENTIAL SIGNAL TRANSMISSION STRUCTURE AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal. | 03-06-2014 |
| 20140146628 | TECHNIQUE FOR IMPROVING STATIC RANDOM-ACCESS MEMORY SENSE AMPLIFIER VOLTAGE DIFFERENTIAL - A static random-access memory (SRAM) module includes a column select (RSEL) driver coupled to an input/output (I/O) circuit by an RSEL line. The I/O circuit is configured to read bit line signals from a bit cell within the SRAM module. During a read operation, the RSEL driver pulls the RSEL line to zero in order to cause p-type metal-oxide-semiconductors (PMOSs) within the I/O circuit to sample the bit line signals output by the bit cell. In response, an aggressor driver drives the RSEL line to a negative voltage, thereby reducing the resistance of the PMOSs within the I/O circuit. | 05-29-2014 |
| 20140198596 | CIRCUIT FOR CONTROLLING SENSE AMPLIFIER SOURCE NODE IN SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD THEREOF - Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level. The sense amplifier source node control circuit may also include: a floating circuit for floating the sense amplifier driving signal line in a set operating mode; and a controller connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, for controlling a level of the sense amplifier driving signal line in the set operating mode. | 07-17-2014 |
| 20140269131 | MEMORY WITH POWER SAVINGS FOR UNNECESSARY READS - A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers. | 09-18-2014 |
| 20150085593 | NON-VOLATILE MEMORY (NVM) WITH DYNAMICALLY ADJUSTED REFERENCE CURRENT - A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation. | 03-26-2015 |
| 20160163375 | MEMORY DEVICE - A memory device may include: first to Nth cell blocks; first to (N−1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein drivability for driving the first node is different from drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein drivability for driving the second node is different from drivability for driving the bit line of the Nth cell block. | 06-09-2016 |
| 20160189756 | SEMICONDUCTOR STORAGE DEVICE AND SENSE AMPLIFIER CIRCUIT - A cross-coupled circuit provided between first and second bit lines that form a bit line pair includes first to fourth fin transistors of p-channel type. The first transistor has its source connected to a first power supply and its gate connected to the second bit line. The second transistor has its source connected to the first power supply and its gate connected to the first bit line. The third transistor has its source connected to the first transistor's drain and its drain connected to the first bit line. The fourth transistor has its source connected to the second transistor's drain and its drain connected to the second bit line. | 06-30-2016 |
| 20160379704 | PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry. | 12-29-2016 |
| 20180025768 | UTILIZATION OF DATA STORED IN AN EDGE SECTION OF AN ARRAY | 01-25-2018 |
