| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365100000 | Resistive | 20 |
| 20080225567 | METHOD AND STRUCTURE FOR INCREASING EFFECTIVE TRANSISTOR WIDTH IN MEMORY ARRAYS WITH DUAL BITLINES - A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more. | 09-18-2008 |
| 20090080233 | METHOD AND APPARATUS FOR PRINTED RESISTIVE READ ONLY MEMORY - A printed read only memory (ROM) device that consists of an array of memory resistors, a reference resistor, and analog-to-digital circuit is disclosed. Resistance values are dependent on the data to be stored in the read only memory. During read operation, a resistor in the array is powered, activating a voltage divider between the powered resistor and the reference resistor. The analog-to-digital circuit will read the divided voltage level between the two resistors, compare the voltage supply level and interpret it into bits of memory data. During the manufacturing of the ROM circuit, an array of memory resistors is printed as the means for storage of the data. Resistive inks of specific resistance values are selected and printed in a preferred layout that includes a reference resistor coupled to the determined array of memory resistors and an analog to digital converter so as to form a read only memory with the received data. | 03-26-2009 |
| 20090086527 | Non-volatile memory device having threshold switching resistor, memory array including the non-volatile memory device and methods of manufacturing the same - Provided are a non-volatile memory device having a threshold switching resistor, a memory array including the non-volatile memory device, and methods of manufacturing the same. A non-volatile memory device having a threshold switching resistor may include a first resistor having threshold switching characteristics, an intermediate electrode on the first resistor, and a second resistor having at least two resistance characteristics on the intermediate electrode. | 04-02-2009 |
| 20090168486 | Large capacity one-time programmable memory cell using metal oxides - A method of programming a nonvolatile memory device includes (i) providing a nonvolatile memory cell comprising a diode in series with at least one metal oxide, (ii) applying a first forward bias to change a resistivity state of the metal oxide from a first state to a second state; (iii) applying a second forward bias to change a resistivity state of the metal oxide from a second state to a third state; and (iv) applying a third forward bias to change a resistivity state of the metal oxide from a third state to a fourth state. The fourth resistivity state is higher than the third resistivity state, the third resistivity state is lower than the second resistivity state, and the second resistivity state is lower than the first resistivity state. | 07-02-2009 |
| 20100046270 | RESISTANCE VARIABLE MEMORY APPARATUS - A resistance variable memory apparatus ( | 02-25-2010 |
| 20100110751 | SEMICONDUCTOR STORAGE DEVICE - In a configuration having a nonvolatile memory and a volatile memory, when storage information of the nonvolatile memory is changed and an abnormal operation occurs due to temporary blackout, α-ray or others, the abnormal operation is recovered to a normal operation regardless of the presence of the detection of the abnormal operation. A reset to be inputted to the nonvolatile memory is collectively transmitted for each 1 bit, each 1 word or each predetermined arbitrary bit, and the collectively transmitted reset serving as one unit is periodically transmitted, so that the abnormal operation is recovered to a normal operation without input signals from outside even if the storage information of the nonvolatile memory is changed due to temporary blackout, α-ray or others. | 05-06-2010 |
| 20100135060 | MEMORY DEVICE AND STORAGE APPARATUS - A memory device | 06-03-2010 |
| 20100177550 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory according to an aspect of the invention includes a memory cell array and a power supply circuit. The memory cell array includes memory cells each having an insulating film and being programmed to store information by inflicting an electric stress on the insulating film to break the insulating film. The power supply circuit supplies to the memory cell a program voltage for the electric stress depending on a negative temperature coefficient the electric stress. | 07-15-2010 |
| 20110149631 | Rewritable Memory Device with Multi-Level, Write-Once Memory Cells - The embodiments described herein are directed to a memory device with multi-level, write-once memory cells. In one embodiment, a memory device has a memory array comprising a plurality of multi-level write-once memory cells, wherein each memory cell is programmable to one of a plurality of resistivity levels. The memory device also contains circuitry configured to select a group of memory cells from the memory array, and read a set of flag bits associated with the group of memory cells. The set of flag bits indicate a number of times the group of memory cells has been written to. The circuitry is also configured to select a threshold read level appropriate for the number of times the group of memory cells has been written to, and for each memory cell in the group, read the memory cell as an unprogrammed single-bit memory cell or as a programmed single-bit memory cell based on the selected threshold read level. | 06-23-2011 |
| 20110222330 | NONVOLATILE MEMORY DEVICE COMPRISING ONE-TIME-PROGRAMMABLE LOCK BIT REGISTER - A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state. | 09-15-2011 |
| 20120063191 | Performing Data Operations Using Non Volatile Third Dimension Memory - Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive. | 03-15-2012 |
| 20120069621 | Integrated Circuits Using Non Volatile Resistivity Sensitive Memory For Emulation Of Embedded Flash Memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 03-22-2012 |
| 20120140543 | One Time Programming Memory and Method of Storage and Manufacture of the Same - The present invention relates to a one time programming memory and method of storage and manufacture of the same. It belongs to microelectronic memory technology and manufacture field. The one time programming memory comprises a diode ( | 06-07-2012 |
| 20130003436 | AMORPHOUS SILICON RRAM WITH NON-LINEAR DEVICE AND OPERATION - A non-volatile memory device includes a resistive switching device having a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least a metal material physically and electrically in contact with the resistive switching material, wherein the resistive switching element is characterized by a resistance depending on an electric field in the resistive switching element, and a non-linear device coupled between the first electrode and the resistive switching element, wherein the non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode, wherein the resistive switching device is configured to change from a first state to a second state in response to the first voltage. | 01-03-2013 |
| 20130201748 | Circuit and System of Protective Mechanisms for Programmable Resistive Memories - Programmable resistive memory using at least one diodes as program selectors can be data protected by programming protection bits in a non-volatile protection bit register. The data stored in the protection bit register can be used to enable or disable reading or writing in part or the whole programmable resistive memory. The data stored in the protection bit register can also be used to enable or enable scrambling the addresses to allow accessing the programmable resistive memory array. Similarly, the data stored in the protection bit register can be used to scramble data when writing into and descramble data when reading from the programmable resistive memory. Keys can be provided for address or data scrambling. The non-volatile protection bit register can be built with the kind of cells as the main array and/or integrated with the main array in the programmable resistive memory. | 08-08-2013 |
| 20130208526 | CIRCUIT AND SYSTEM OF USING JUNCTION DIODE AS PROGRAM SELECTOR AND MOS AS READ SELECTOR FOR ONE-TIME PROGRAMMABLE DEVICES - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP cell can have a MOS in series with the OTP element as a read selector. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal-0, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof. | 08-15-2013 |
| 20130215663 | Circuit and System of Using Junction Diode as Porgram Selector for One-Time Programmable Devices with Heat Sink - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof. | 08-22-2013 |
| 20130314970 | PILLAR-SHAPED NONVOLATILE MEMORY AND METHOD OF FABRICATION - A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided. | 11-28-2013 |
| 20160093398 | MEMORY DEVICE INCLUDING NONVOLATILE MEMORY CELL - A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state. | 03-31-2016 |
| 20160180931 | APPARATUSES AND/OR METHODS FOR OPERATING A MEMORY CELL AS AN ANTI-FUSE | 06-23-2016 |
