| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365066000 | Magnetic | 30 |
| 20120044736 | MEMORY DEVICES USING A PLURALITY OF DIODES AS PROGRAM SELECTORS FOR MEMORY CELLS - At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations. | 02-23-2012 |
| 20120099358 | Reference cell architectures for small memory array block activation - Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read. | 04-26-2012 |
| 20120163061 | MEMORY ARRAY HAVING LOCAL SOURCE LINES - A memory is provided that simplifies a fabrication process and structure by reducing the number of source lines and bitlines accessible to circuitry outside of the memory array. The memory has first and second row groups comprising a plurality of memory elements each coupled to one each of a plurality of M bit lines; first and second local source lines and first and second word lines, each coupled to each of the plurality of memory elements; and circuitry coupled to the first and second word lines and configured to select one of the first and second row groups, and coupled to the plurality of M bit lines and configured to apply current of magnitude N through the memory element in the selected row group coupled to one of the plurality of M bit lines by applying current of magnitude less than N to two or more of the remaining M-1 bit lines. | 06-28-2012 |
| 20120188812 | HYBRID MRAM ARRAY STRUCTURE AND OPERATION - This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor | 07-26-2012 |
| 20120243286 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series. | 09-27-2012 |
| 20120287696 | STORAGE ELEMENT AND STORAGE DEVICE - A storage element includes a storage layer having a magnetization perpendicular to a layer surface and storing information according to a magnetization state of a magnetic material; a fixed magnetization layer having the magnetization as a reference of the information of the storage layer and perpendicular to the layer surface; an interlayer formed of a nonmagnetic material and interposed between the storage layer and the fixed magnetization layer; a coercive force enhancement layer adjacent to the storage layer, opposite to the interlayer, and formed of Cr, Ru, W, Si, or Mn; and a spin barrier layer formed of an oxide, adjacent to the coercive force enhancement layer, and opposite to the storage layer. The storage layer magnetization is reversed using spin torque magnetization reversal caused by a current in a lamination direction of a layer structure including the storage layer, the interlayer, and the fixed magnetization layer, thereby storing information | 11-15-2012 |
| 20120314468 | Memory array with local bitlines and local-to-global bitline pass gates and gain stages - A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. | 12-13-2012 |
| 20130294136 | GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS - A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation. | 11-07-2013 |
| 20140063891 | SEMICONDUCTOR MEMORY DEVICE - According to one or more embodiments of the present invention, the semiconductor memory device of this disclosure includes the first bit line and the second bit line. Each of the multiple memory cells includes a memory element and a transistor, which are connected in series between the first and the second bit lines. Multiple memory cells are connected in parallel between the first and the second bit lines. In the first memory cell, its memory element is connected to the first bit line, and its transistor is connected to the second bit line. In the second memory cell, its memory element is connected to the second bit line, and its transistor is connected to the first bit line. | 03-06-2014 |
| 20140104920 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps. | 04-17-2014 |
| 20140153311 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series. | 06-05-2014 |
| 20140233294 | Memory Cell with Decoupled Read/Write Path - A memory cell with a decoupled read/write path includes a switch comprising a first terminal connected to a first line and a second terminal connected to a second line, a resistive switching device connected between a gate of the switch and a third line, and a conductive path between the gate of the switch and the second line. | 08-21-2014 |
| 20140286075 | RESISTANCE CHANGE MEMORY - According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array. | 09-25-2014 |
| 20150023085 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series. | 01-22-2015 |
| 20150036409 | SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL USING MAGNETIC TUNNEL JUNCTION CELLS - An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. | 02-05-2015 |
| 20150070961 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a first bit line and a second bit line. A nonvolatile memory element and a first cell transistor are connected in series between the first bit line and the second bit line. A sense transistor has a gate connected to a sense node which is provided between the first bit line and the memory element. A read bit line is connected to a source or a drain of the sense transistor. The read bit line is configured to transmit data of the memory element. A sense amplifier is configured to detect the logic of data transmitted from the read bit line. | 03-12-2015 |
| 20150109846 | MEMORY APPARATUS AND MEMORY DEVICE - To provide a memory apparatus capable of operating at high speed with less current and inhibiting a decrease in an amplitude of a readout signal. | 04-23-2015 |
| 20150117081 | MEMORY CELL WITH DECOUPLED READ/WRITE PATH - A memory cell with a decoupled read/write path, the memory cell includes a switch comprising a gate, a first terminal and a second terminal, a resistive switching device connected to the gate of the switch, and a conductive path between the gate of the switch and the second terminal. | 04-30-2015 |
| 20150364178 | MEMORY CORES OF RESISTIVE TYPE MEMORY DEVICES, RESISTIVE TYPE MEMORY DEVICES AND METHOD OF SENSING DATA IN THE SAME - A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal. | 12-17-2015 |
| 20160042778 | MTJ SPIN HALL MRAM BIT-CELL AND ARRAY - Described is an apparatus 1T-1 Magnetic Tunnel Junction (MTJ) Spin Hall Magnetic Random Access Memory (MRAM) bit-cell and array, and method of forming such. The apparatus comprises: a select line; an interconnect with Spin Hall Effect (SHE) material, the interconnect coupled to a write bit line; a transistor coupled to the select line and the interconnect, the transistor controllable by a word line; and a MTJ device having a free magnetic layer coupled to the interconnect. | 02-11-2016 |
| 20160042781 | CIRCUIT AND METHOD FOR ACCESSING A BIT CELL IN A SPIN-TORQUE MRAM - Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations. | 02-11-2016 |
| 20160055892 | Magnetic Memory Element and Magnetic Memory - According to one embodiment, a magnetic memory element includes a first magnetic unit, a second magnetic unit, a third magnetic unit, a read/write unit, a first electrode, a second electrode, a third electrode, a first current source, the second current source. The third magnetic unit is connected to one end in the first direction of the first magnetic unit and one end in the first direction of the second magnetic unit. The read/write unit includes a nonmagnetic layer and a pinned layer. The nonmagnetic layer is connected to the third magnetic unit. The pinned layer is connected to the nonmagnetic layer. The first current source causes a current to flow between the third electrode and at least one of the first electrode or the second electrode. The second current source causes a current to flow between the first electrode and the second electrode. | 02-25-2016 |
| 20160078913 | MAGNETIC MEMORY, SPIN ELEMENT, AND SPIN MOS TRANSISTOR - A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage. | 03-17-2016 |
| 20160086647 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a first bit line and a second bit line. A nonvolatile memory element and a first cell transistor are connected in series between the first bit line and the second bit line. A sense transistor has a gate connected to a sense node which is provided between the first bit line and the memory element. A read bit line is connected to a source or a drain of the sense transistor. The read bit line is configured to transmit data of the memory element. A sense amplifier is configured to detect the logic of data transmitted from the read bit line. | 03-24-2016 |
| 20160155486 | RESISTANCE CHANGE MEMORY | 06-02-2016 |
| 20160172036 | MEMORY CELL WITH RETENTION USING RESISTIVE MEMORY | 06-16-2016 |
| 20160203865 | APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE | 07-14-2016 |
| 20160379697 | VARIABLE CHANGE MEMORY AND THE WRITING METHOD OF THE SAME - According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line. | 12-29-2016 |
| 365067000 | Plural diagonal | 1 |
| 20130265814 | MAGNETIC RAMDOM ACCESS MEMORY - A magnetic random access memory includes multiple gate lines that are divided into a first gate line group and a second gate line group and arranged to be parallel to one another; multiple magnetic random access memory cells that are bonded to the gate lines in a direction intersected with the gate lines, respectively; multiple source lines that are bonded to one ends of switching devices included in the magnetic random access memory cells and arranged to be parallel to one another; and multiple bit lines that are bonded to one ends of magnetic tunnel junction devices included in the magnetic random access memory cells and arranged to be parallel to one another. | 10-10-2013 |
| 365069000 | Crossover | 1 |
| 20130343113 | SEMICONDUCTOR DEVICE - A semiconductor device in which noise is reduced without an increase in chip area. The device is used as an MRAM in which a memory mat is formed on a silicon substrate surface and the central area of the memory mat is used as a memory array and the area around the memory array is used as a dummy memory array. In the dummy memory array, a capacitor is formed between each bit line, each digit line and a supply voltage line, and a grounding voltage line. Therefore the peak value of a current flowing in each of the bit lines, digit lines and supply voltage line is decreased. | 12-26-2013 |
