Entries |
Document | Title | Date |
20080198640 | Data Storage Device - In a non-volatile electric memory system a card-like memory unit ( | 08-21-2008 |
20080205111 | Semiconductor memory device and defect remedying method thereof - A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays. | 08-28-2008 |
20080212351 | Pin configuration changing circuit, base chip and system in package including the same - A pin configuration changing circuit of a base chip includes pin configuration changing register (PCCR) and a pin configuration changing logic unit (PCCLU). The PCCR stores and provides a pin connection assignment value indicating a first connection order of a plurality of pins included in a memory connected to the base chip, based on a type of the memory when the memory is changed. The PCCLU receives the pin connection assignment value and changes a second connection order of a plurality of inner pins of the base chip. Various memories can be connected to the base chip without extra wiring or a printed circuit board (PCB). | 09-04-2008 |
20080212352 | MULTI-LAYER SEMICONDUCTOR MEMORY DEVICE COMPRISING ERROR CHECKING AND CORRECTION (ECC) ENGINE AND RELATED ECC METHOD - Embodiments of the invention provide a multi-layer semiconductor memory device and a related error checking and correction (ECC) method. The multi-layer semiconductor memory device includes first and second memory cell array layers, wherein the first memory cell array layer stores first payload data. The multi-layer semiconductor memory device also includes an ECC engine selectively connected to the second memory cell array layer and configured to receive the first payload data, generate first parity data corresponding to the first payload data, and store the first parity data exclusively in the second memory cell array layer. | 09-04-2008 |
20080239780 | SEMICONDUCTOR DEVICE - A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches. | 10-02-2008 |
20080239781 | Semiconductor memory device and method of forming a layout of the same - A semiconductor memory device having a double-patterned memory cell array that includes a plurality of first bit lines spaced apart from each other and having a first pattern, a plurality of second bit lines spaced apart from each other and having a second pattern, the second bit lines being between the first bit lines to define an alternating array of first and second bit lines, the first and second patterns being different from each other, a first main memory cell array defined by a first portion of the alternating array, a second main memory cell array defined by a second portion of the alternating array, bit lines in the first main memory cell array having a substantially same regularity as bit lines in the second main memory cell array, and a dummy array between the first main memory cell array and the second main memory cell array. | 10-02-2008 |
20080253159 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises word lines, global bit lines intersecting with the word lines; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; global sense amplifiers for amplifying the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line and for selectively coupling the signal to an external data line. | 10-16-2008 |
20080259668 | Layout structure of bit line sense amplifiers for a semiconductor memory device - A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier. | 10-23-2008 |
20080259669 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF OPTIMIZING SIGNAL TRANSMISSION POWER AND POWER INITIALIZING METHOD THEREOF - A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first chip, checking whether the test signal provided to the first chip has an error, providing the checking result to the signal-providing chip, setting the power of a first signal provided to the first chip according to the checking result, and setting the power of a signal provided to a second chip adjacent to the first chip and close to the signal-providing chip using the power of the first signal. | 10-23-2008 |
20080259670 | Memory Module - A memory module having a board and a plurality of memory elements on the board which belong to different memory ranks, each memory rank being addressable via a respective selection signal. The memory module additionally includes a memory buffer having a memory rank interface coupled to the memory elements of each memory rank, and a selection signal output for the selection signal of each memory rank, the memory elements being arranged in rows on the board and the memory elements of a memory rank extending only over half of the rows. | 10-23-2008 |
20080259671 | 3-DIMENSIONAL INTEGRATED CIRCUIT ARCHITECTURE, STRUCTURE AND METHOD FOR FABRICATION THEREOF - An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement. | 10-23-2008 |
20080266924 | NAND INTERFACE - A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin. | 10-30-2008 |
20080266925 | Array Split Across Three-Dimensional Interconnected Chips - A design structure including a semiconductor storage array having a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines. | 10-30-2008 |
20080273363 | Semiconductor Constructions, Electronic Systems, And Methods of Forming Cross-Point Memory Arrays - Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode. | 11-06-2008 |
20080273364 | MEMORY STRUCTURE WITH EMBEDED MULTI-TYPE MEMORY - A memory includes a first-type memory; and a second-type memory, formed on the first-type memory, wherein the first-type memory is a nonvolatile memory with a stack of conductor/storage/conductor, and the second-type memory is a nonvolatile memory, a flash memory or another memory with a stack of conductor/storage/conductor. In addition, the nonvolatile memory can include a storage element for each memory cell, including a bottom electrode layer; a memory material layer, disposed over the bottom electrode layer, wherein the memory material has at least two physical states under different electric operation condition; and a top electrode layer, disposed over the memory material layer. | 11-06-2008 |
20080273365 | NONVOLATILE MEMORY DEVICE HAVING TWIN MEMORY CELLS - A nonvolatile memory device includes multiple first bit lines extending in a first direction, multiple word lines formed on the first bit lines and extending in a second direction different from the first direction, and multiple second bit lines, formed on the word lines and extending in the first direction. The nonvoliative memory device also includes multiple twin memory cells, each of which includes a first memory cell coupled between a first bit line and a word line and a second memory cell coupled between the word line and a second bit line. The first and second memory cells store different data. | 11-06-2008 |
20080285324 | SEMICONDUCTOR MEMORY DEVICE - Shunt regions are formed at certain intervals in a memory cell array region as extending in a second direction. The shunt regions each include a contact formed to connect a word line or a signal line wired in the same direction to another metal wire. Extension regions are each formed of an extension of the shunt region in the data cache array region. Data input/output lines extend in a first direction and transfer data on bit lines simultaneously via a data cache array. Sense circuits are arranged around the data cache array and connected to the data input/output lines respectively. The data input/output lines are divided at a certain interval in the first direction. The divided portions are connected to respective leads formed in the extension region in the longitudinal direction thereof and connected to the sense circuits via the leads. | 11-20-2008 |
20080285325 | Semiconductor Memory Device - In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell. | 11-20-2008 |
20080298111 | Semiconductor memory device - A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line. | 12-04-2008 |
20080304307 | USE OF A SYMMETRIC RESISTIVE MEMORY MATERIAL AS A DIODE TO DRIVE SYMMETRIC OR ASYMMETRIC RESISTIVE MEMORY - A symmetrically resistive memory material (such as a phase change material) is described for use as a rectifying element for driving symmetric or asymmetric resistive memory elements in a crosspoint memory architecture. The crosspoint architecture has a plurality of electrodes and a plurality of crossbar elements, with each crossbar element being disposed between a first and a second electrode. The crossbar element is made of a symmetric resistive memory element used as a rectifier in series with a symmetric or asymmetric resistive memory element. | 12-11-2008 |
20080304308 | UNIPOLAR RESISTANCE RANDOM ACCESS MEMORY (RRAM) DEVICE AND VERTICALLY STACKED ARCHITECTURE - One embodiment of the present invention includes a low-cost unipolar rewritable variable-resistance memory device, made of cross-point arrays of memory cells, vertically stacked on top of one another and compatible with a polycrystalline silicon diode. | 12-11-2008 |
20080310207 | 3-D SRAM ARRAY TO IMPROVE STABILITY AND PERFORMANCE - A design structure for a three-dimensional memory circuit provides reduction in memory cell instability due to half-select operation by reduction of the number of memory cells sharing a sense amplifier and, potentially, avoidance of half-select operation by placing some or all peripheral circuits including local evaluation circuits functioning as a type of sense amplifier on an additional chips or chips overlying the memory array. Freedom of placement of such peripheral circuits is provided with minimal increase in connection length since word line decoders may be placed is general registration with ant location along the word lines while local evaluation circuits and/or sense amplifiers can be placed at any location generally in registration with the bit line(s) to which they correspond. | 12-18-2008 |
20080316788 | Semiconductor memory device and method for operating semiconductor memory device - A semiconductor memory device includes a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and the memory array section. The memory array section and the interface section are sealed in a package. The interface section has a plurality of interface modules corresponding to a plurality of memory types on a one-to-one basis. The method includes the steps of: selecting one of the plurality of interface modules in accordance with the memory type complying with specifications of the external memory controller being connected; and causing the selected interface module to access the memory array section for either a write or a read operation in response to either a write or a read request issued by the external memory controller. | 12-25-2008 |
20090003025 | DUAL BIT LINE METAL LAYERS FOR NON-VOLATILE MEMORY - Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4 f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer. | 01-01-2009 |
20090003026 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip. | 01-01-2009 |
20090003027 | PRODUCTION METHOD FOR SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE - A pair of power supply lines that are orthogonal to the border with the cell array are placed, for each one-bit processing circuit of the data processing unit, in a semiconductor storage device such as SRAM or the like comprising a data processing unit for writing data to memory cells and reading it therefrom, a row decode unit for driving the word lines of the memory cells, and a timing control unit for generating a control pulse for the data processing unit, all of which are arranged around the circumference of a cell array in which memory cells are arrayed in a grid-like fashion. MOS transistors are placed between the power supply lines in such a position that the principal axis direction of the gate pattern is orthogonal to the two aforementioned wirings, and are closely arrayed in the longitudinal direction of the power supply lines. | 01-01-2009 |
20090010036 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a memory cell array area having a memory cell, a word line contact area adjacent to the memory cell array area, a word line arranged straddling the memory cell array area and the word line contact area, a contact hole provided on the word line in the word line contact area, and a word line driver connected to the word line via the contact hole. A size of the contact hole is larger than a width of the word line, and the lowest parts of the contact hole exist on a position lower than a top surface of the word line and higher than a bottom surface of the word line. | 01-08-2009 |
20090016092 | SEMICONDUCTOR MEMORY DEVICE AND LOCAL INPUT/OUTPUT DIVISION METHOD - A semiconductor memory device includes: a memory cell array that is arrayed on a plurality of mats; an even number of redundancy Y-switch (YS) signal lines that are provided in three mat units and arranged in the bit line direction on the mat that is positioned in the middle among the three mats disposed continuously in the word line direction; a local input/output (LIO) line that is connected to a sense amplifier portion of the three mats, extends in the word line direction, and is divided in two in a redundancy area that is a part of the even number of redundancy Y switch signal lines; and a plurality of bit line selecting Y switch signal lines that connect bit line output of the memory cell array on the three mats to the local input/output line; wherein 8-bit data prefetch is performed from the three mats by selecting the plurality of bit line selecting Y switch signal lines and turning them ON simultaneously so as to connect the selected bit line output to each local input/output line divided in two. | 01-15-2009 |
20090027938 | METHOD AND APPARATUS PROVIDING MULTI-PLANED ARRAY MEMORY DEVICE - A three dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes. | 01-29-2009 |
20090027939 | MULTI-CHIP PACKAGE REDUCING POWER-UP PEAK CURRENT - Disclosed is a multi-chip package having a plurality of memory chips. Each memory chip includes a memory cell array storing e-fuse data, a read-out control circuit reading e-fuse data in response to a read signal, a first internal pad receiving a first control signal, a read-out controller generating the read signal to define a read period, and to generate a second control signal following the read period, and a second internal pad receiving the second control signal, wherein the plurality of memory chips is connected series and each respective read-out control circuit and read-out controller in each one of the plurality of memory chips cooperate to implement a sequential read of e-fuse data across the plurality of memory chips. | 01-29-2009 |
20090027940 | Memory Module - A memory module with a module board is disclosed, on the front side of which a plurality of first memory devices are arranged in rows. A plurality of second memory devices are arranged in rows on the back side. The first and second memory devices have a single chip each. Further, a first register device for providing first control signals to first rows of first memory devices and to first rows of second memory devices is provided. A second register device serves to provide first control signals to second rows of first memory devices and to second rows of second memory devices. | 01-29-2009 |
20090034312 | SINGLE-EVENT UPSET IMMUNE STATIC RANDOM ACCESS MEMORY CELL CIRCUIT, SYSTEM, AND METHOD - A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell. | 02-05-2009 |
20090034313 | SEMICONDUCTOR MEMORY DEVICE AND LAYOUT STRUCTURE OF SUB-WORD LINE CONTROL SIGNAL GENERATOR - A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance. | 02-05-2009 |
20090034314 | SEMICONDUCTOR MEMORY DEVICE - To secure a sufficient read-out voltage even when lines are arranged at a fine pitch, a semiconductor memory device including: a memory array in which a plurality of memory cells are arranged in rows and columns; and a plurality of bit lines associated with the respective columns of the memory cells is provided. The bit lines include main bit lines and sub bit lines to have a hierarchical structure, the main bit lines are divided among a plurality of interconnection layers, and a distance between the main bit lines in one of the interconnection layers is larger than a distance between the sub bit lines. | 02-05-2009 |
20090034315 | Memory core and semiconductor memory device having the same - A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device. | 02-05-2009 |
20090040802 | SEMICONDUCTOR MEMORY DEVICE, MEMORY-MOUNTED LSI AND FABRICATION METHOD FOR SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device includes a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines. A plurality of MOS transistor blocks are provided which are same in the configuration of circuit elements and include MOS transistors as one kind of the circuit elements. In part of the plurality MOS transistor blocks, the MOS transistors are used for drive of the word lines or the bit lines, while in at least part of the remaining MOS transistor blocks, the MOS transistors are used as MOS capacitors. | 02-12-2009 |
20090040803 | Semiconductor Memory and Method for Operating a Semiconductor Memory - A semiconductor memory having read amplifier strips having a plurality of read amplifiers and having memory cell fields which have a plurality of memory cells connected to bit lines is disclosed. The read amplifier strips include at least two outer read amplifier strips between which the remaining read amplifier strips and the memory cell fields are arranged, wherein adjacent to at least one of the outer read amplifier strips, a reference circuit field is arranged, which has reference lines and reference circuit elements connected thereto, and wherein the reference lines are shorter than the bit lines of the memory cell fields. | 02-12-2009 |
20090052218 | SEMICONDUCTOR PACKAGE HAVING MEMORY DEVICES STACKED ON LOGIC DEVICE - A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes. | 02-26-2009 |
20090052219 | MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF - A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line. | 02-26-2009 |
20090059640 | SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY - A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed in a matrix shape, each word line is disposed in the order like WLA | 03-05-2009 |
20090073736 | SEMICONDUCTOR DEVICE HAVING STORAGE NODES ON ACTIVE REGIONS AND METHOD OF FABRICATING THE SAME - A semiconductor device includes an active region in a semiconductor substrate, having first, second and third regions sequentially arranged in the active region. An inactive region in the semiconductor substrate defines the active region. Gate patterns, partially buried in the active and inactive regions, are positioned between the first and second regions or between the second and third regions, intersecting the active region at right angles. A bit line pattern intersects the gate patterns at right angles and overlaps the inactive region, the bit line pattern including a region electrically connected to the second region of the active region. An interlayer insulating layer covers the gate patterns. Storage nodes on the interlayer insulating layer are electrically connected to the active region. A first storage node overlaps the first region and the inactive region and a second storage node overlaps the third region, the inactive region and the bit line pattern. | 03-19-2009 |
20090091962 | MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY - A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips. | 04-09-2009 |
20090097295 | Nonvolatile Semiconductor Memory Device - A nonvolatile semiconductor memory device can prevent memory characteristics from deteriorating due to IR drop on word or bit lines in a cross-point type memory cell array. The device comprises a word line selection circuit selecting a selected word line from word lines and applying selected and unselected word line voltages to the selected and unselected word lines, respectively, a bit line selection circuit selecting a selected bit line from bit lines and applying selected and unselected bit line voltages to the selected and unselected bit lines, respectively, and voltage control circuits preventing voltage fluctuation of at least either one of the word and bit lines, wherein at least either one of the word and bit lines are connected to the voltage control circuits at a voltage control point positioned at a farthest point from a drive point connected to the word line selection circuit or bit line selection circuit. | 04-16-2009 |
20090097296 | REDUCED SIZE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is described that includes memory banks having memory cells and are laid out as a matrix on a semiconductor chip body. The semiconductor memory device includes a first pad group having first pads that are arranged in a line between two adjoining memory banks and a second pad group having second pads that are also arranged in a line between the two adjoining memory banks parallel to the first pad group. At least one third pad group is also formed interposed between the first and second pad groups having at least one third pad allowing for a reduction in size of the semiconductor memory device. | 04-16-2009 |
20090097297 | Memory module having star-type topology and method of fabricating the same - A memory module having a start-type topology and a method of fabricating the same are provided. The memory module includes a substrate. Memory devices are mounted on the substrate in at least two rows and at least two columns. A star-type topology is disposed to be electrically connected to the memory devices. One or more pairs of adjacent ones of the memory devices have a point-symmetric structure. | 04-16-2009 |
20090103343 | Semiconductor memory device comprising transistor having vertical channel structure - A semiconductor memory device including a transistor having a vertical channel structure is provided. The device comprises a first sub memory cell array comprising a first memory cell connected to a first bit lines and comprising a transistor having a vertical channel structure, a second sub memory cell array comprising a second memory cell connected to a first inverted bit lines and comprising a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line. | 04-23-2009 |
20090103344 | MEMORY MODULE, SYSTEM AND METHOD OF MAKING SAME - A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices. The first and second portions of memory devices are grouped into a plurality of memory device stacks, wherein each of the plurality of memory device stacks includes at least one of the plurality of memory devices coupled to a first portion of the plurality of DQ signals and at least another one of the plurality of memory devices coupled to a different second portion of the plurality of DQ signals. | 04-23-2009 |
20090109720 | Memory Structure - The subject matter of this specification can be embodied in, among other things, a method for manufacturing and a structure of a byte-addressable electrically erasable programmable read-only memory (EEPROM). In a first aspect, a byte-addressable EEPROM integrated circuit includes isolation means, in each of a plurality of memory bytes, for electrically isolating the EEPROM byte select transistor from an EEPROM memory bit disposed closest to the byte select transistor. In one example, the isolation means precludes the need to use a wide STI oxide for isolation, and thereby avoids the process variation of active area of memory bits. | 04-30-2009 |
20090116270 | Floating Body Memory Cell System and Method of Manufacture - A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc. | 05-07-2009 |
20090116271 | MEMORY - A memory is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blocks respectively are different from each other. | 05-07-2009 |
20090122586 | METHOD AND APPARATUS FOR AN INTEGRATED CIRCUIT WITH PROGRAMMABLE MEMORY CELLS, DATA SYSTEM - A method and apparatus for an integrated circuit with programmable memory cells which are arranged between a first and a second conductor for supplying first and second voltage is provided. A control circuit is arranged between the memory cells and the second conductor. The control circuit controls a change time during which at least one of the memory cells is supplied with a changing current from the second supply changing a state of the memory cell. The control circuit senses the state of the memory cell and stops the erasing current when the memory cell is in a changed state. Furthermore an embodiment refers to a data system with a programmable memory and a method of operating an integrated circuit. Another embodiment refers to a method of operating an integrated circuit. | 05-14-2009 |
20090122587 | MEMORY SYSTEM AND DATA TRANSMISSION METHOD - A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks. | 05-14-2009 |
20090129135 | Semiconductor devices having sense amplifiers and electronic systems employing the same - A semiconductor device having sense amplifiers and an electronic system employing the same are provided. The semiconductor device includes first sense amplifier blocks arranged in a row direction on a substrate and spaced apart from each other by a first distance. A second sense amplifier block spaced apart from the first sense amplifier blocks by a second distance greater than the first distance is provided. A plurality of cell array blocks arranged in the row direction on the substrate is provided. Each of the first and second sense amplifier blocks is disposed between the cell array blocks, and each of the cell array blocks includes a plurality of memory cells. | 05-21-2009 |
20090129136 | SEMICONDUCTOR MEMORY DEVICE - If memory cell blocks are laid out in a conventional manner to create a memory chip with a capacity of an odd power of 2 by using memory cells whose aspect ratio is 1:2, the chip will take a 1:1 shape and become difficult to enclose in a package of a 1:2 shape. In addition, such conventional layout of memory cell blocks to form the 1:2 shape causes the area of a peripheral circuit region to be limited by the memory blocks, pads to be arranged collectively in the central section of the chip, and wiring to become dense during the enclosure of the chip in the package. | 05-21-2009 |
20090135637 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state. | 05-28-2009 |
20090135638 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IDENTIFYING A PLURALITY OF MEMORY CHIPS STACKED IN THE SAME PACKAGE - A semiconductor memory device is configured to vertically stack a plurality of memory chips using a resistance-change memory element as a memory cell in one package. The memory chips each have first and second memory position detection pads connected via chip top and bottom electrodes facing each other. Of the vertically stacked memory chips, the lowermost memory chip is provided with the connected chip bottom electrodes of the first and second memory position detection pads. The memory chips each control the variable resistance element, and in a state that the first memory position detection pad has a higher resistance than the second memory position detection pad, compare a voltage applied to the first memory position detection pad with the chip position detection signal using the comparator when a voltage is applied between the first and second memory position detection pads provided on the uppermost layer memory chip. | 05-28-2009 |
20090141532 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other. | 06-04-2009 |
20090147557 | 3D CHIP ARRANGEMENT INCLUDING MEMORY MANAGER - Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface. | 06-11-2009 |
20090154211 | Placement and routing of ECC memory devices for improved signal timing - Various exemplary embodiments are a printed circuit board and related method of manufacturing, the printed circuit board including a memory controller, a plurality of synchronous data memory devices, each synchronous memory device including at least one data pin and at least one address/command pin, an ECC memory device including at least one ECC data pin and at least one ECC address/command pin, and at least one surface. In various exemplary embodiments, the plurality of synchronous data memory devices are arranged around a central location on the at least one surface and each synchronous data memory device is oriented such that the at least one data pin is further from the memory controller than the at least one address/command pin. | 06-18-2009 |
20090154212 | Memory module - A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to receive second signals to commonly control the memory devices. Each of the memory devices includes a plurality of first signal input units configured to receive the first signals through one or more first input pins, a plurality of second signal input units configured to receive the second signals through one or more second input pins, and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more third input pins and to compensate for a signal line load. | 06-18-2009 |
20090154213 | SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE - A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size. | 06-18-2009 |
20090154214 | SEMICONDUCTOR MEMORY - Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AA | 06-18-2009 |
20090161401 | Multi-die Memory, Apparatus and Multi-die Memory Stack - The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection. | 06-25-2009 |
20090161402 | DATA STORAGE AND STACKABLE CONFIGURATIONS - A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through he memory devices. | 06-25-2009 |
20090161403 | SEMICONDUCTOR MEMORY DEVICE HAVING A PLURALITY OF CHIPS AND CAPABILITY OF OUTPUTTING A BUSY SIGNAL - One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips. | 06-25-2009 |
20090168480 | Three dimensional hexagonal matrix memory array - A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer. | 07-02-2009 |
20090168481 | Tree-structure memory device - A tree-structure memory device. A tree-structure memory device comprises a plurality of bit lines formed on a substrate and arranged in at least one plane substantially parallel to a substrate surface and extending substantially in a first direction. A plurality of layers having a plurality of memory cells is arranged in a first array. At least one tree structure corresponds to a plurality of layers and a bit line, and has a trunk portion and at least one branch portion that corresponds to one of the layers. A word-line group includes at least one word line crossing with the branch portion of the tree structure at a first intersection region. A memory cell of the first array is located at the first intersection region in a layer of the layers. The first array of memory cells includes at least one memory cell comprising a phase-change-material layer disposed between the word line and the branch portion of the tree structure at the first intersection region without an intervening current-steering element. | 07-02-2009 |
20090168482 | THREE-DIMENSIONAL MEMORY DEVICE - A three-dimensional memory device includes a base layer having a memory array and peripheral circuits formed on a bulk silicon substrate, and N circuit layers each having a memory array formed on a silicon-on-insulator (SOI) substrate. The N circuit layers are vertically stacked one on top of the other on the base layer and the uppermost Nth circuit layer additionally includes passive elements | 07-02-2009 |
20090185407 | Semiconductor Memory Device Having Transistors of Stacked Structure - Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines, and a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively, wherein a plurality of word lines are disposed on a first layer, and a plurality of drivers are disposed on at least two second layers. | 07-23-2009 |
20090196083 | Integrated circuits to control access to multiple layers of memory - Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. | 08-06-2009 |
20090196084 | Memory chip array - Provided is a memory chip array comprising a plurality of cell arrays and at least one predecoder commonly connected to the plurality of cell arrays, wherein the memory chip array promotes an efficient arrangement structure of the memory chip array and is minimized in area. | 08-06-2009 |
20090196085 | SRAM MEMORY CELL PROTECTED AGAINST CURRENT OR VOLTAGE SPIKES - A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell. | 08-06-2009 |
20090201710 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of cell arrays, each cell array including a plurality of mutually parallel word lines, a plurality of mutually parallel bit lines disposed to cross these word lines, and a plurality of cells connected to the intersections of these word lines and bit lines, respectively, one portion of the cell arrays forming a memory cell array that has the cells as memory cells, and another portion of the cell arrays forming a reference cell array that has the cells as reference cells. A cell selection circuit is operative to select from the memory cell array a memory cell whose data is to be read, and to select from the reference cell array a reference cell at a position corresponding to a position of the memory cell selected in the memory cell array. A sense amplifier circuit is operative to detect and compare a current or a voltage of the selected memory cell with a current or a voltage of the selected reference cell, and thereby read data of the memory cell. | 08-13-2009 |
20090201711 | MEMORY MODULE WITH A CIRCUIT PROVIDING LOAD ISOLATION AND MEMORY DOMAIN TRANSLATION - A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module. | 08-13-2009 |
20090207641 | NOVEL TRANSMISSION LINES FOR CMOS INTEGRATED CIRCUITS - Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application. | 08-20-2009 |
20090213633 | Four vertically stacked memory layers in a non-volatile re-writeable memory device - A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array. | 08-27-2009 |
20090213634 | STACKED MEMORY AND FUSE CHIP - A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells. The fuse chip has a fuse unit including a plurality of fuse elements whose electrical cut state corresponding to a replacement with the spare memory cells can be set. Also the fuse chip has a redundancy cell control circuit for controlling a redundancy cell operation of the defective memory cells based on state information of the fuse unit. | 08-27-2009 |
20090219740 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs. | 09-03-2009 |
20090219741 | DIAGONAL CONNECTION STORAGE ARRAY - In one aspect, an electronic memory array includes overlapping, generally parallel sets of conductors, and includes storage elements near each point of overlap. One set of conductors has a non-negligible resistance. An address path for each storage element traverses a portion of one each of the first and second sets of conductors and a selectable resistance element. All storage element address paths have substantially equivalent voltage drops across the corresponding storage elements. | 09-03-2009 |
20090219742 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 09-03-2009 |
20090219743 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 09-03-2009 |
20090219744 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 09-03-2009 |
20090219745 | MEMORY MODULE AND MEMORY DEVICE - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 09-03-2009 |
20090231897 | MULTI-CHIP PACKAGE - A multi-chip package includes a plurality of memory chips and a control chip. The control chip stores information about whether the memory chips are operating normally and selects chips that are operating normally according to an address signal. | 09-17-2009 |
20090231898 | Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same - An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line. | 09-17-2009 |
20090237970 | PROCESS VARIATION COMPENSATED MULTI-CHIP MEMORY PACKAGE - A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal. | 09-24-2009 |
20090237971 | SEMICONDUCTOR MEMORY DEVICES WITH INTERFACE CHIPS HAVING MEMORY CHIPS STACKED THEREON - A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed. The interface chips may forward the command signal from one end of the sequence of the stacked memories on one of the substrates to the selected stacked memory, and forward a response signal from the selected stacked memory through the remaining stacked memories in the sequence on the substrate back to the controller or through the same sequence of stacked memories that was taken by the command signal. | 09-24-2009 |
20090244948 | EMBEDDED MEMORY APPARATUS WITH REDUCED POWER RING AREA - An embedded memory apparatus with reduced power ring area is disclosed. In order to save the area consumption of a chip, a scheme for removing the power rings originally disposed in a memory core, or another scheme for sharing the power rings with other adjacent memory cores is provided. According to the preferred embodiment of the routing, the power strips originally bridging the inner elements and the outer power serve as the power source (VDD) and ground (VSS) respectively since the peripheral power ring surrounded the core is removed. Thus the area consumption is reduced as if the surrounded power ring shrinks inwardly. The shared power ring for the adjacent memory cores can also be another aspect for reducing the area. | 10-01-2009 |
20090251940 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE USING A VARIABLE RESISTANCE FILM AND METHOD OF MANUFACTURING THE SAME - A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes. | 10-08-2009 |
20090262563 | Memory device capable of one-time data writing and repeated data reproduction, and method and display apparatus for operating the memory device - Provided are a memory device where data may be recorded one time and/or reproduced repeatedly, and a method and display apparatus for operating the memory device. The memory device may include a program area having a plurality of memory cells and a spare area having a plurality of memory cells. The memory device may include a memory cell layer having the program area and the spare area. The memory cell layer may include a plurality of vertically stacked memory cell layers. Each of the plurality of memory cell layers may include the program area and the spare area. The program area and the spare area may be either vertical or horizontal to one another. | 10-22-2009 |
20090262564 | CIRCUIT WIRING LAYOUT IN SEMICONDUCTOR MEMORY DEVICE AND LAYOUT METHOD - An improved circuit wiring layout provides smooth circuit wiring in a peripheral circuit region adjacent to a memory cell region of a semiconductor memory device, and eliminates a write-speed limiting factor. Forming a metal (instead of a metal silicided polysilicon) wiring layer to be connected to a gate layer, to transmit an electrical signal to the gates of FET (e.g., MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors formed in the peripheral circuit region; the metal wiring layer is formed (e.g., using one metal damascene process), on a layer different from a word line layer formed on the gate layer (e.g., using another metal damascene process), thereby obtaining a layout of a peripheral circuit region having a reduced area and without using a silicide process. | 10-22-2009 |
20090268498 | Semiconductor memory device and method of performing data reduction test - A semiconductor device includes a plurality of package terminals included in a package, a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals, and a plurality of data line control switch disposed between the plurality of package terminals and the plurality of data input/output terminals. The plurality of data line control switches of each of the chips connects the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode. The plurality of data line control switches connects different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode. The respective groups of the data input/output terminals belong to the plurality of data input/output terminals. The respective groups of the package terminals are different between different ones of the chips. | 10-29-2009 |
20090268499 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor. | 10-29-2009 |
20090273960 | SYSTEM FOR PROVIDING ON-DIE TERMINATION OF A CONTROL SIGNAL BUS - A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT is in communication with the control bus connector, and the ODT provides a level of termination resistance to a control bus connected to the control bus connector. The mechanism latches data received via the data bus connectors in response to a signal received via one or both of the load signal connector and the reset signal connector. The data is utilized to set the level of termination resistance provided by the ODT. | 11-05-2009 |
20090273961 | SEMICONDUCTOR DEVICE - A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously. | 11-05-2009 |
20090290401 | PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS - A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells. | 11-26-2009 |
20090290402 | Semiconductor memory devices and methods of arranging memory cell arrays thereof - A semiconductor memory device and a method of arranging a memory cell array of the semiconductor device are provided. The semiconductor memory device has a memory cell array including a word line pair including a first word line and a second word line that are arranged in a first direction, a source line arranged in the first direction between the first word line and the second word line, a bit line pair including a first bit line and a second bit line arranged in a second direction perpendicular to the first direction, a first memory cell including a gate connected to the first word line and first and second regions respectively connected to the second bit line and the source line, and arranged in a third direction between the first direction and the second direction, and a second memory cell including a gate connected to the second word line, a third region and the second region respectively connected to the first bit line and the source line, and arranged in the third direction. The first word line and the second word line are simultaneously activated. Therefore, disturbance that may be generated between adjacent memory cells in the semiconductor memory cell can be prevented, integration density of the semiconductor memory device can be enhanced, and the number of word lines to be driven may be reduced to employ a sub-word line structure. | 11-26-2009 |
20090290403 | SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device including: first and second blocks that each includes a word line group of first to N-th word lines, the word lines extending in a given direction, the word lines having a first width, the first and second blocks being adjacent to and in parallel with each other in a crossing direction so that an inter-block area is interposed therebetween and so that the word line groups are symmetrical with respect to the inter-block area; and a first wirings that are formed in a first wiring layer positioned above the word lines to have a second width wider than the first width and that connect a k-th word line of the first block and a k-th word line of the second block. | 11-26-2009 |
20090296443 | MEMORY DEVICE HAVING DATA PATHS - Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of the master data lines extends in a space between one of the port pads and a respective one of the memory arrays. Each of the master data lines is electrically connectable to the contacts of a respective one of the port pads. The apparatus further includes a plurality of local data lines, each of which extends over a respective one of the memory arrays. Each of the local data lines is electrically connectable to a respective one of the master data lines. At least one of the local data lines extends over at least two of the memory arrays. This configuration allows memory array consolidation and/or swapping without increasing die space for additional routing and adversely affecting performance of the apparatus. | 12-03-2009 |
20090296444 | MEMORY MODULE AND METHOD FOR ACCESSING MEMORY MODULE - A memory module includes a plurality of memory sub-modules and a plurality of groups of input pins, where each memory module includes a plurality of memory chips and the memory chips are series-connected. In addition, the plurality of groups of input pins are connected to the plurality of memory modules, respectively, and are utilized to receive the same input signals, where each group of input pins includes a plurality of input pins which are utilized to transmit the input signals to a corresponding memory module. | 12-03-2009 |
20090296445 | DIODE DECODER ARRAY WITH NON-SEQUENTIAL LAYOUT AND METHODS OF FORMING THE SAME - In various embodiments, an electronic circuit includes an array of locations each corresponding to an intersection of a row and a column, and a plurality of devices each disposed proximate one of the locations, wherein no more than ten contiguous locations lack a proximate device. | 12-03-2009 |
20090303768 | MEMORY MODULE, METHOD FOR USING SAME AND MEMORY SYSTEM - In a multi-rank memory module having a terminal resistance of a data input/output pad | 12-10-2009 |
20090323385 | Method for fabricating high density pillar structures by double patterning using positive photoresist - A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern. | 12-31-2009 |
20090323386 | Methods and Systems for Reducing Heat Flux in Memory Systems - The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus. | 12-31-2009 |
20100002485 | CONFIGURABLE INPUTS AND OUTPUTS FOR MEMORY STACKING SYSTEM AND METHOD - Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin. | 01-07-2010 |
20100008120 | SEMICONDUCTOR MEMORY - Dummy memory cells are disposed on an outside of real memory cells positioned on a peripheral part of a matrix. First contacts coupling between two wiring layers laminated on a semiconductor substrate are disposed around each of the real and dummy memory cells, and are shared by an adjacent real or dummy memory cell. Number of the first contacts disposed in each of the dummy memory cells is set to be smaller than number of the first contacts disposed in each of the real memory cells. Accordingly, even when a well region is not formed normally due to a variation in manufacturing conditions, it is possible to prevent an abnormal power supply current from being flown into the dummy memory cells, and an occurrence of latch up can be prevented. | 01-14-2010 |
20100014339 | Semiconductor memory device and memory access method - A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input output lines, third and fourth local input output lines coupled to the second memory mat via a second amplifier circuit; a third amplifier circuit coupled between the first local input output line and a first main input output line; a fourth amplifier circuit coupled between the third local input output line and a second main input output line different from the first main input output line; and a first switch coupled between the second and third local input output lines and connecting the second local input output line to the fourth amplifier circuit when the first memory mat is activated and the second memory mat is not activated. | 01-21-2010 |
20100020583 | Stacked memory module and system - A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system. | 01-28-2010 |
20100027307 | MEMORY DETECTING CIRCUIT - A memory detecting circuit includes five switch elements and two indication devices. A first switch element is connected to a standby power, and also connected to memory sockets of a first channel to receive a first memory detecting signal. A second switch element is connected to the first switch element and the standby power. A third switch element is connected to the second switch element and the standby power, and also connected to memory sockets of a second channel to receive a second memory detecting signal. A fourth switch element is connected to the third switch element and the standby power. A fifth switch element is connected to the fourth switch element and the standby power. When there are memories installed into the memory sockets of the first channel and the second channel, the second indication device indicates that the memories run in a dual channel mode. | 02-04-2010 |
20100027308 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series, and a control circuit selectively driving the first and second wirings. The control circuit applies a first voltage to the selected first wiring and applies a second voltage to the selected second wiring to apply a certain potential difference to a selected memory cell positioned at a intersection between the selected first and second wirings, and brings at least one of nonselected first wirings into a floating state. | 02-04-2010 |
20100034004 | SEMICONDUCTOR MEMORY DEVICE OF OPEN BIT LINE TYPE - There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell; a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat. | 02-11-2010 |
20100039845 | INTEGRATED CIRCUIT WITH BIT LINES POSITIONED IN DIFFERENT PLANES - An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells. | 02-18-2010 |
20100039846 | Method and Apparatus for Non-Volatile Multi-Bit Memory - A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer. | 02-18-2010 |
20100039847 | METHOD OF MANUFACTURING A SINGLE CHIP SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A MASK ROM IN A SHORT TIME - In a state of a first semiconductor integrated circuit device on which a first semiconductor integrated circuit board including a first mask ROM and a programmable ROM are mounted, an ultimate program determined by using the programmable ROM is stored in a second ROM of a second semiconductor integrated circuit board which is substantially similar in structure to the first semiconductor integrated circuit board, thereby manufacturing a second semiconductor integrated circuit device as an ultimate product. | 02-18-2010 |
20100046266 | High Speed Memory Architecture - Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks. | 02-25-2010 |
20100046267 | MEMORY SYSTEM WITH SECTIONAL DATA LINES - A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay. | 02-25-2010 |
20100061131 | Circuit Arrangement Comprising a Memory Cell Field and Method for Operation Thereof - A circuit arrangement comprises a memory cell array ( | 03-11-2010 |
20100061132 | SEMICONDUCTOR STORAGE DEVICE - In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film | 03-11-2010 |
20100067278 | MASS DATA STORAGE SYSTEM WITH NON-VOLATILE MEMORY MODULES - A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to the controller; and at least one non-volatile memory module comprising a second connector electrically connected to a chain of non-volatile memory devices, wherein mating of the second connector with a given one of the at least one first connector causes the chain of non-volatile memory devices to be inserted into the ring, thereby to allow the controller to carry out the memory operations on the non-volatile memory devices in the chain. | 03-18-2010 |
20100067279 | SEMICONDUCTOR MEMORY DEVICE USING VARIABLE RESISTOR - Example embodiments relate to a variable resistance semiconductor memory device including: a plurality of memory blocks belonging to different memory sectors and alternately arranged in a memory bank including the memory sectors so as to be adjacent to each other; and a line selecting unit simultaneously selecting word lines of the plurality of memory blocks and simultaneously selecting bit lines of the memory blocks belonging to the same memory sector among the plurality of memory blocks in an access operation mode. | 03-18-2010 |
20100073982 | Semiconductor device and method for designing the same - Disclosed herewith is a semiconductor device having an SRAM cell array capable of easily evaluating the performance of transistors and the systematic fluctuation of wiring capacity/resistance. In order to form an inversion circuit required to form a ring oscillator, a test cell is disposed at each of the four corners of the SRAM cell array and the ring oscillator is operated while charging/discharging the subject bit line. Concretely, the ring oscillator is formed on a memory cell array and the ring oscillator includes test cells disposed at least at the four corners of the memory cell array respectively. At this time, a wiring that is equivalent to a bit line is used to connect the test cells to each another. | 03-25-2010 |
20100073983 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD OF THE SAME - A nonvolatile semiconductor memory device comprises a memory cell array composed of a plurality of memory cells each including a variable resistance element in which a resistance characteristic is changed by applying a voltage to the both ends, and information related to the resistance characteristic can be stored; a load circuit connected to one terminal of the variable resistance element in series; and a voltage generation circuit for applying a voltage to both ends of a series circuit. The variable resistance element selectively transits to one resistance characteristic selected from at least three different resistance characteristics when the voltage generated from the voltage generation circuit is applied under the transition condition set by changing any one or both of the load resistance characteristic of the load circuit and the voltage generation condition from the voltage generation circuit, and can store information having at least three values. | 03-25-2010 |
20100080032 | SEMICONDUCTOR DEVICE - A semiconductor device is provided in which two adjacent cell lines extending in a word line direction are connected by one word line. Additionally, A semiconductor device comprising: word lines; bit lines which are disposed to cross the word lines; a plurality of cell lines extending in a word line direction; and a word line provided to share one cell line and the other cell line, of a pair of cell lines comprising two adjacent cell lines, wherein a distance between two adjacent cell lines in the pair of cell lines is smaller than a distance between two adjacent cell lines between one pair of cell lines and the other pair of cell lines. | 04-01-2010 |
20100091536 | COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto. | 04-15-2010 |
20100091537 | MULTI-DIE MEMORY DEVICE - An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission. | 04-15-2010 |
20100091538 | BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM - Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device. | 04-15-2010 |
20100091539 | SOLID STATE DEVICE PRODUCTS, INTERMEDIATE SOLID STATE DEVICES, AND METHODS OF MANUFACTURING AND TESTING THE SAME - Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test terminals, which may permit in situ testing of one or more components of the solid state device products. | 04-15-2010 |
20100091540 | MEMORY MODULE DECODER - A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element configurable to receive a set of input signals from the computer system. The circuit further comprising a register and a phase-lock loop circuit, the phase-lock loop circuit configurable to be operatively coupled to the plurality of memory devices, the logic element, and the register. The set of input signals corresponds to a second number of memory devices smaller than the first number of memory devices. | 04-15-2010 |
20100091541 | Stacked memory device and method thereof - A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit. | 04-15-2010 |
20100097832 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array. | 04-22-2010 |
20100097833 | PHASE CHANGE MEMORY DEVICE - A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage. | 04-22-2010 |
20100097834 | TREE-STRUCTURE MEMORY DEVICE - A tree-structure memory device including a plurality of bit lines formed on a substrate and arranged in at least one plane substantially parallel to a substrate surface and extending substantially in a first direction, a plurality of layers having a plurality of memory cells arranged in a first array, a tree structure corresponding to a plurality of layers and a bit line; and a word-line group including at least one word line crossing with the tree structure, a memory cell of the first array being located at the first intersection region in a layer of said layers. | 04-22-2010 |
20100103713 | ADJUSTABLE WIDTH STROBE INTERFACE - A memory system comprises a circuit board | 04-29-2010 |
20100103714 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively driving the first and second wirings. The plurality of first wirings that are specified and selectively driven at the same time by one of a plurality of address signals are separately arranged with other first wirings interposed therebetween within the memory cell array when a certain potential difference is applied to a selected memory cell positioned at an intersection between the first and second wirings by the control circuit. | 04-29-2010 |
20100110745 | SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated. | 05-06-2010 |
20100110746 | MEMORY CELL WITH ALIGNMENT STRUCTURE - A memory cell that includes a memory element configured for switching from a first data state to a second data state by passage of current therethrough. The memory cell includes a top electrode and a bottom electrode for providing the current through the memory cell, and an alignment element positioned at least between the top electrode and the top surface of the memory element, the alignment element having an electrically conductive body tapering from the top electrode to the top surface of the memory element. Methods for forming the memory cell are also described. | 05-06-2010 |
20100110747 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device proposed in the present invention comprises memory cells disposed in the row direction and the column direction, a plurality of first lines by which supply voltages are supplied in order to select memory cells disposed in the row direction among the plurality of cells, a plurality of second lines by which supply voltages are supplied in order to select memory cells disposed in the column direction among the plurality of cells, the data lines which input and output the data to the selected memory cells, the first power voltage supply circuit which supplies the predetermined supply voltages to the first lines corresponding with the externally input row address synchronizing with an act command, and the second power voltage supply circuit which supplies the predetermined supply voltages to the second lines corresponding with the externally input column address synchronizing with an act command. It also comprises m pieces of memory banks (m is a natural number larger than 2) which write or read the data into or from the memory cells which are selected one after another in the row or column directions, data input circuits in which multiple bits of serial data which is larger than 512 bits to be written in the m pieces of memory banks, data output circuits which reads the data from the m pieces of memory banks and output in a form of multiple bits of serial data which is larger than 512 bits, and data conversion circuits which convert the serial data input in the data input circuits to parallel data so that it can be written in each memory bank or to convert each parallel data read from each memory bank to serial data so that such data are supplied to the data output circuits. | 05-06-2010 |
20100110748 | HYBRID VOLATILE AND NON-VOLATILE MEMORY DEVICE - A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice. | 05-06-2010 |
20100118579 | Nand Based Resistive Sense Memory Cell Architecture - Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor. | 05-13-2010 |
20100118580 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first positive and negative data lines driven with voltage levels contrary to each other in response to first data and second positive and negative data lines driven with voltage levels contrary to each other in response to second data, wherein one of the second positive and negative data lines is disposed between the first positive and negative data lines. | 05-13-2010 |
20100118581 | MAGNETIC MEMORY DEVICE - The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed. | 05-13-2010 |
20100124090 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - To provide data lines connected via column switches to a plurality of sense amplifiers and an input/output circuit that, in response to a write request, supplies pre-write data through the data line to selected phase change memory cells and then write data through the data line to the selected phase change memory cells. Thus, a pre-write operation and an actual write operation according to the write data can be performed at high speed. Because only the memory cells selected by a column address are subject to write, consumption power is reduced and lives of the memory cells are not shortened. | 05-20-2010 |
20100128506 | MEMORY - A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states in a standby time. | 05-27-2010 |
20100128507 | CIRCUIT PROVIDING LOAD ISOLATION AND MEMORY DOMAIN TRANSLATION FOR MEMORY MODULE - A circuit is configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module. The circuit includes a logic element, a register, and a phase-lock loop device. The circuit is configurable to respond to a set of input signals from a computer system to selectively isolate one or more loads of the plurality of DDR memory devices from the computer system and to translate between a system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices. | 05-27-2010 |
20100142243 | DATA STORAGE SYSTEM WITH REMOVABLE MEMORY MODULE HAVING PARALLEL CHANNELS OF DRAM MEMORY AND FLASH MEMORY - A data storage system | 06-10-2010 |
20100142244 | MEMORY MODULE AND DATA INPUT/OUTPUT SYSTEM - A memory module is configured to include a first rank installed with a first memory chip and a second rank installed with a second memory chip. When the first and second memory chips are in a first data output mode, the first memory chip is configured to externally output lower order data of a plurality of data via lower data output pins. Also, when the first and second memory chips are in the first data output mode, the second memory chip is configured to externally output data that has the same order as the lower order data output by the first memory chip via upper data output pins. | 06-10-2010 |
20100142245 | Semiconductor device - A semiconductor device includes: a memory cell array having a plurality of memory cells arranged in arrays; a plurality of bit lines formed correspondingly to a column arrangement of the memory cells; a plurality of word lines formed correspondingly to a row arrangement of the memory cells; a plate line having one of a configuration in which the first electrodes of the respective memory cells are included in the plate line and a configuration in which the first electrodes are connected to the plate line; a column switch used to connect a selected bit line and a data access line; and a pre-charge portion that performs a pre-charge operation to pre-charge a non-selected bit line not selected by the column switch to potential of the plate line. | 06-10-2010 |
20100142246 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cell mats, a plurality of sub-word driver regions and a plurality of sense amplifier regions, a plurality of intersection regions, a sub-amplifier, and a start signal (a control signal) supply circuit (a sub-amplifier control circuit). A plurality of sub-word driver regions and a plurality of sense amplifier regions are disposed adjacent to the plurality of memory cell mats. A plurality of intersection regions are intersection regions between the plurality of sub-word driver regions and the plurality of sense amplifier regions. The sub-amplifier is disposed in a first intersection region among the plurality of intersection regions. The start signal supply circuit is disposed in a second intersection region among the plurality of intersection regions, and supplies a start signal (a control signal) of the sub-amplifier to the sub-amplifier based on a sub-amplifier timing signal supplied from the extending direction of the sub-word driver region. | 06-10-2010 |
20100142247 | MEMORY MODULES AND METHODS FOR MODIFYING MEMORY SUBSYSTEM PERFORMANCE - Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component. | 06-10-2010 |
20100142248 | Buffering systems for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 06-10-2010 |
20100149849 | MEMORY ARRAY ON MORE THAN ONE DIE - For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed. | 06-17-2010 |
20100157642 | MITIGATION OF CHARGE SHARING IN MEMORY DEVICES - One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed. | 06-24-2010 |
20100157643 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes non-inversion repeaters that non-invert data and output the inverted data; and inversion repeaters that invert data and output the inverted data. The non-inversion repeaters or the inversion repeaters are arranged on a first data line and a second data line at a predetermined distance, respectively, which are parallel with each other and the most adjacent to each other and the non-inversion repeater or the inversion repeater is arranged at first positions corresponding to the first data line and the second data line, respectively. The non-inversion repeaters are arranged on one of the first data line and the second data line while the inversion repeaters are arranged on the other first data line and the second data line, at second positions except for the first arrangement positions of positions corresponding to the first data line and the second data line, respectively. | 06-24-2010 |
20100157644 | Configurable memory interface to provide serial and parallel access to memories - The invention relates to an interface for providing multiple modes of accessing data, including serial and parallel modes. Controllable non-volatile memory interfaces are described, including a serial module configured to provide a serial connection between a non-volatile memory array and another non-volatile memory array. The serial module can provide access to the non-volatile memory array. A mode module can be configured to determine which type of interface operation (i.e., serial mode or parallel mode) will be used for the non-volatile memory array and the another non-volatile memory array. In some cases, a controller can be configured to select the serial module independent of the mode module. Circuitry for performing data operations on the non-volatile memories can be fabricated FEOL on a substrate and the non-volatile memories can be fabricated BEOL directly on top of the substrate in one or more layers of memory. | 06-24-2010 |
20100157645 | MEMORY MODULE AND LAYOUT METHOD THEREFOR - The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector. | 06-24-2010 |
20100157646 | METHODS AND APPARATUS FOR DISABLING A MEMORY-ARRAY PORTION - A memory device having a plurality of storage locations disposed along a plurality of generally parallel lines includes, connected to the lines, a decoder circuit for selecting one line, and, connected to each line, a line-disabling circuit for selectively preventing the line from being energized during line selection. | 06-24-2010 |
20100157647 | Memory access circuits and layout of the same for cross-point memory arrays - An integrated circuit includes a substrate including active circuitry fabricated on the substrate and a cross-point memory array formed above the substrate. The cross-point memory array can include conductive array lines arranged in different directions, and re-writable memory cells. Further, the integrated circuit can also include a memory access circuit configured to perform data operations on the cross-point memory array. The integrated circuit can include a cross-point memory array interface layer positioned between the substrate and the cross-point array and including conductive paths configured to electrically couple portions of the memory access circuit with a subset of the conductive array lines. At least one layer of cross-point memory arrays can be formed over the substrate. The memory cells can be two-terminal memory cells that store data as a plurality of conductivity profiles (e.g., resistive states) that can be non-destructively determined by applying a read voltage across the terminals. | 06-24-2010 |
20100165692 | VARIABLE MEMORY REFRESH DEVICES AND METHODS - Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate. | 07-01-2010 |
20100165693 | SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE - A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats. | 07-01-2010 |
20100177544 | Generating ROM bit cell arrays - A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area. Thus the system designer can reuse an existing memory architecture, yet still retain an advantageous degree of flexibility with regard to performance characteristic selection of the final ROM bit cell array. | 07-15-2010 |
20100177545 | MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF - A memory circuit includes at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. The memory circuit includes a first conductive layer, a second conductive layer coupled with the first conductive layer, a third conductive layer coupled with the second conductive layer. The third conductive layer is routed for the word line and is free from including the bit line, the bit line bar, the first voltage line, and the second voltage line within the memory cell. | 07-15-2010 |
20100182817 | Memory system, semiconductor memory device, and wiring substrate - A memory system includes a plurality of semiconductor memory devices each including a termination resistance circuit that can be controlled to be turned on or off from an outside by a termination resistance control signal, and a memory controller. The memory controller includes a termination resistance control unit that outputs the termination resistance control signal so that when a read command or a write command is executed on one of the semiconductor memory devices, termination resistances of all of the semiconductor memory devices are turned on, and when any of the semiconductor memory devices does not execute the read command or the write command, the termination resistances of all of the semiconductor memory devices are turned off. The termination resistance circuit of one of the semiconductor memory devices is turned off, irrespective of the level of the termination resistance control signal when the one of the semiconductor memory devices outputs data in response to the read command. | 07-22-2010 |
20100195362 | Non-volatile dual port third dimensional memory - Non-volatile dual port memory with third dimension memory is described, including a non-volatile third dimensional memory array comprising a memory element, the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage, a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, the transceiver gate is configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being coupled to the memory element and configured to provide the another voltage, and a plurality of word lines coupled to the memory element, the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports. | 08-05-2010 |
20100195363 | Multiple layers of memory implemented as different memory technology - Circuits and methods that use third dimension memory as a different memory technology are described. The third dimension memory can be used for application specific data storage and/or to emulate conventional memory types such as DRAM, FLASH, SRAM, and ROM or new memory types as they become available. A processor-memory system implements a memory operable as different memory technologies. The processor-memory system includes a logic subsystem and a memory subsystem, which includes third dimension memory cells. The logic subsystem implements memory technology-specific signals to interact with the third dimension memory cells as memory cells of a different memory technology. As such, the memory subsystem can emulate different memory technologies. The logic subsystem can be fabricated FEOL on a substrate and the memory subsystem can be fabricated BEOL directly on top of the substrate. An interlayer interconnect structure can electrically couple the logic subsystem with the memory subsystem. | 08-05-2010 |
20100202179 | MEMORY DEVICE - A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line. | 08-12-2010 |
20100202180 | MEMORY MODULE CUTTING OFF DM PAD LEAKAGE CURRENT - A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode. | 08-12-2010 |
20100208503 | THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A three-dimensional (3D) semiconductor structure with high density and method of fabricating the same are disclosed. The 3D semiconductor structure comprises at least a first memory cell and a second memory cell stacked on the first memory cell. The first memory cell comprises a first conductive line and a second conductive line. The second memory cell comprises another first conductive line opposite to the first conductive line of the first memory cell, and the second conductive line formed between said two first conductive lines of the first and second memory cells. The first and second memory cells share the second conductive line when the 3D semiconductor structure is programming and erasing, and each of the first and second memory cells has a diode. | 08-19-2010 |
20100214812 | STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE - A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). | 08-26-2010 |
20100214813 | Memory module having a plurality of phase change memories, buffer RAM and nand flash memory - A memory module comprises a plurality of main memories; a buffer RAM configured to temporarily store data being provided to or read from the main memories and to perform a buffer function between an external device and the main memories; and a NAND flash memory configured to store data of the buffer RAM during an interruption of power being supplied to the buffer RAM. | 08-26-2010 |
20100232196 | MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE PROVIDING ACTIVE TERMINATION CONTROL - A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated. | 09-16-2010 |
20100232197 | DATA STORAGE DEVICE - A device to selectively activate memory chips includes a memory unit including n memory chips activated in response to n memory chip activation signals (n is a natural number), a controller to generate m control signals (m is a natural number), and a memory chip activation signal generator to combine m chip enable (CE) signals to generate the n memory chip activation signals. | 09-16-2010 |
20100232198 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic element and a variable resistance element; a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit from a low resistance state to a high resistance state, to the memory cells through the first wirings and the second wirings; and a bias voltage application circuit configured to apply a bias voltage, which suppresses a potential variation caused by the transition of the variable resistance element from the low resistance state to the high resistance state, to one end of the variable resistance element. | 09-16-2010 |
20100232199 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array including memory cells, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit a resistance state, to a selected memory cell. When applying the control voltage plural times, the control circuit operates to set a value of the control voltage applied in a first control voltage application operation to be substantially equal to a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element from a high resistance state to a low resistance state. The control circuit operates to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value. | 09-16-2010 |
20100232200 | VERTICAL SWITCH THREE-DIMENSIONAL MEMORY ARRAY - A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6F | 09-16-2010 |
20100232201 | STACKED SEMICONDUCTOR MEMORY DEVICE - A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes. | 09-16-2010 |
20100238693 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 09-23-2010 |
20100238694 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is configured to reduce data read time. In the semiconductor storage device, an input/output control circuit is formed along one side of a memory cell array disposed between a data input pad and a data output pad. The input/output control circuit is disposed between a hold command input pad and a clock input pad. Accordingly, it is possible to minimize the distances of the wirings from the input/output control circuit to the pads and to make the distances of the wirings equal and thus to minimize the read time of the memory cell array. In addition, since it is also possible to make equal wiring distances from the input/output control circuit to the address decoder and output multiplexer, it is possible to minimize the read time of the memory cell array. | 09-23-2010 |
20100238695 | MEMORY MODULE INCLUDING MEMORY CHIPS - To provide a module substrate, memory chips mounted on the module substrate, and data input/output wirings that are connected respectively to the memory chips and read data or write data is transmitted thereto. The number of memory chips is equal to the number of bits of read data or write data transmitted through the data input/output wirings at the same time. Because a plurality of data input/output wirings are connected to different memory chips, the load exerted upon each channel can be reduced without using memory buffers. | 09-23-2010 |
20100238696 | MULTI-CHIP PACKAGES INCLUDING EXTRA MEMORY CHIPS TO DEFINE ADDITIONAL LOGICAL PACKAGES AND RELATED DEVICES - A packaged integrated circuit device includes a primary chip stack and a secondary chip stack. The primary chip stack includes memory chips therein that define a logical package addressable by a memory controller. The secondary chip stack includes fewer memory chips than the primary chip stack. The memory chips of the secondary chip stack are configured to be electrically connected to memory chips of at least one external device package to define an additional logical package addressable by the memory controller. For example, the additional logical package may include a same number of memory chips as the primary chip stack. Related devices are also discussed. | 09-23-2010 |
20100246234 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers. | 09-30-2010 |
20100259960 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 10-14-2010 |
20100259961 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Double-Global-Bit-Line Architecture - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A double-global-bit-line architecture provides a pair of global bit lines for each bit lines for accessing a row of memory elements in parallel. A first one of each pair allows the local bit lines of the row to be sensed while a second one of each pair allows local bit lines in an adjacent row to be set to a definite voltage so as to eliminate leakage currents between adjacent rows of local bit lines. | 10-14-2010 |
20100259962 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line. | 10-14-2010 |
20100265749 | THREE DIMENSIONALLY STACKED NON VOLATILE MEMORY UNITS - A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region. | 10-21-2010 |
20100265750 | MEMORY SYSTEM WITH DATA LINE SWITCHING SCHEME - A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group. | 10-21-2010 |
20100265751 | MULTI-CHIP PACKAGES PROVIDING REDUCED SIGNAL SKEW AND RELATED METHODS OF OPERATION - A packaged integrated circuit device includes a substrate including a conductive pad thereon, and a chip stack including a plurality of chips on the substrate. A primary conductive line electrically connects the pad on the substrate to a conductive pad on one of the plurality of chips in the chip stack. Secondary conductive lines electrically connect the pad on the one of the plurality of chips to respective conductive pads on ones of the plurality of chips above and below the one of the plurality of chips in the chip stack. The primary conductive line may be configured to transmit a signal from the pad on the substrate to the pad on the one of the plurality of chips in the chip stack. After receiving the signal at the one of the plurality of chips, the secondary conductive lines may be configured to transmit the signal from the one of the plurality of chips to the ones of the plurality of chips above and below the one of the plurality of chips in the chip stack at a same time. Related methods of operation are also discussed. | 10-21-2010 |
20100265752 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element | 10-21-2010 |
20100265753 | SYSTEMS, METHODS AND DEVICES FOR ARBITRATING DIE STACK POSITION IN A MULTI-DIE STACK DEVICE - Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked dies are arbitrated to select one of the dies as the primary die and the other as secondary. Each die includes an input/output buffer that drives an output signal to a commonly shared output terminal in response to receiving a die identification data bit as the input signal. Each die also includes an arbitration circuit that generates a control signal in response to the identification bit of one die being mismatched to a corresponding identification bit of the other die. The control signal programs a stack enable fuse in accordance with the arbitration to designate one of the dies as the secondary die. | 10-21-2010 |
20100271855 | MEMORY CELL ARRANGEMENTS - In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell, and a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line. | 10-28-2010 |
20100271856 | SEMICONDUCTOR MEMORY DEVICE HAVING HIERARCHICALLY-CONSTRUCTED I/O LINES - To provide main I/O lines(MIOX) arranged along an X direction; a plurality of I/O nodes(ND) arranged along the X direction; an amplifier circuit area(AMPA) including a plurality of amplifier circuits(AMP); a plurality of main I/O lines(MIOY) arranged along a Y direction, which respectively connect each of the main I/O lines(MIOX) and each of the corresponding I/O nodes(ND). Among the main I/O lines(MIOY) allocated to the amplifier circuits different from one another, that having a longer wire length is connected more closely to a center of the corresponding main I/O line(MIOX); and that having a shorter wire length is connected more closely to an end of the corresponding main I/O line(MIOX). Accordingly, the difference in wire length for each signal route becomes smaller, and also the wire length of the longest wire route is reduced. | 10-28-2010 |
20100277962 | Media player with non-volatile memory - A media player is provided that includes a processor configured to execute a media player program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device, and an analog/digital module electrically coupled with the processor and the non-volatile memory, the analog/digital module configured to output a media signal. The input/output module may be in electrical communication with the input/output device (e.g., electrically coupled) and/or signal communication with the input/output device (e.g., wireless and/or optical communication). | 11-04-2010 |
20100277963 | IC CARD - An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip ( | 11-04-2010 |
20100277964 | MULTI-BANK MEMORY - A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed. | 11-04-2010 |
20100290262 | Three dimensional hexagonal matrix memory array - A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer. | 11-18-2010 |
20100302829 | SEMICONDUCTOR MODULE AND DATA MEMORY MODULE HAVING THE SAME - A semiconductor module and a data memory module having the same are provided. The semiconductor module includes a substrate having a semiconductor device, a ground terminal, a protection pattern, and a switching element. The ground terminal and the protection pattern are formed on the substrate. The switching element connects the ground terminal and the protection pattern in series. The switching element electrically connects the protection pattern and the ground terminal when a voltage applied to the substrate is beyond a set voltage range. | 12-02-2010 |
20100309704 | In-pakage microelectronic apparatus, and methods of using same - A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s. | 12-09-2010 |
20100309705 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups. | 12-09-2010 |
20100309706 | Load reduced memory module and memory system including the same - A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
20100309707 | PCB CIRCUIT MODIFICATION FROM MULTIPLE TO INDIVIDUAL CHIP ENABLE SIGNALS - A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die. | 12-09-2010 |
20100315852 | MEMORY AND STORAGE DEVICE UTILIZING THE SAME - A storage device including a memory and a reading circuit is disclosed. The memory includes a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the third bit lines are sequentially disposed in parallel and vertical with the word lines. Each cell corresponds to one word line and one bit line. The word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The read circuit is coupled to the memory for reading the data stored in the memory. | 12-16-2010 |
20100328983 | Memory System with Multi-Level Status Signaling and Method for Operating the Same - A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level. | 12-30-2010 |
20110002152 | SYSTEMS, MEMORIES, AND METHODS FOR REPAIR IN OPEN DIGIT MEMORY ARCHITECTURES - Memories, systems, and methods for repairing are provided. A memory with extra digit lines in end arrays with an open digit architecture can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group four adjacent digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. To repair memories including folded digit end arrays, a row in a core array that includes a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO. | 01-06-2011 |
20110002153 | MANUFACTURING METHOD FOR STACKING MEMORY CIRCUITS AND FOR ADDRESSING A MEMORY CIRCUIT, CORRESPONDING STACKING AND DEVICE - The invention relates to a method for making a stack of memory circuits, wherein the method includes the step of testing the validity of at least two memory circuits. According to the invention, the method includes the phase of configuring each memory circuit, the configuration phase including the step of writing, within a configuration device of each memory circuit included in the stack, a piece of information on an identifier allocated to the memory circuit in the stack, and a piece of information on the results of the validity test of the memory circuit. The invention also relates to a method for addressing a memory circuit, to a stack of memory circuits, and to an electronic device including such a stack. | 01-06-2011 |
20110007538 | SYSTEMS AND METHODS OF CELL SELECTION IN CROSS-POINT ARRAY MEMORY DEVICES - The disclosure is related to three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). | 01-13-2011 |
20110007539 | TEST MODE FOR MULTI-CHIP INTEGRATED CIRCUIT PACKAGES - When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to signal lines of one of the integrated circuit devices of the multi-chip integrated circuit package to permit direct testing of the integrated circuit device. | 01-13-2011 |
20110019455 | LOW COST HIGH DENSITY RECTIFIER MATRIX MEMORY - A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers. | 01-27-2011 |
20110026289 | CELL STRUCTURE FOR DUAL PORT SRAM - A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the data storage node and a second pass gate transistor coupled to the data bar storage node, each pass gate transistor being coupled to a respective bit line conductor, wherein the pull down transistors of the first inverter are formed in a first active region, the pull down transistors of the second inverter are formed in a second active region, the pass gate transistors coupled to the data storage node are formed in a third active region and the pass gate transistors coupled to the data bar storage node are formed in a fourth active region. | 02-03-2011 |
20110026290 | SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS - A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated. | 02-03-2011 |
20110026291 | System using non-volatile resistivity-sensitive memory for emulation of embedded flash memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 02-03-2011 |
20110032740 | MEMORY SYSTEM HAVING IMPROVED SIGNAL INTEGRITY - A memory system having improved signal integrity includes a printed circuit board for use in a memory device, N memory semiconductor packages mounted on the printed circuit board, a first switch mounted on the printed circuit board, a controller mounted on the printed circuit board, N first signal lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to-1 correspondence, a second signal line connecting the first switch to the controller, and N selection lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to-1 correspondence. The N selection lines connect the semiconductor packages to the controller and transmit an enable signal. N is a natural number. | 02-10-2011 |
20110044084 | MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY - A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips. | 02-24-2011 |
20110051487 | Read only memory cell for storing a multiple bit value - A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a single one of the three output lines and a voltage source. The switching device provides an electrical connection between the voltage source and the single one of the three output lines in response to a switching signal, a voltage of the connected output line switching value in response to connection to the predetermined voltage and the multiple bit value represented by the output line is thereby selected. There is also an output device provided for outputting the selected multiple bit value. | 03-03-2011 |
20110069522 | VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS - A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations. | 03-24-2011 |
20110075466 | METHODS AND APPARATUS FOR USING A CONFIGURATION ARRAY SIMILAR TO AN ASSOCIATED DATA ARRAY - Methods, apparatus, and systems in accordance with this invention include memories that include a data array and a configuration array adapted to store configuration information for configuring the data array. The data array and the configuration array include a plurality of wordlines and a plurality of bitlines. The plurality of wordlines in the data array extend in the same direction as the plurality of wordlines in the configuration array. Likewise, the plurality of bitlines in the data array extend in the same direction as the plurality of bitlines in the configuration array. Numerous other aspects are disclosed. | 03-31-2011 |
20110080763 | METHOD FOR CONTEMPORANEOUS MARGIN VERIFICATION AND MEMORY ACCESS FOR MEMORY CELLS IN CROSS-POINT MEMORY ARRAYS - Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory cells. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory cells substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory cells may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state). | 04-07-2011 |
20110085365 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a cell area and a sense amplifier area, a first bit line connected to a bit line contact of the cell area and a first contact of the sense amplifier area, and a second bit line located on the first bit line to overlap with the first bit line on a plan view and connected to a second contact of the sense amplifier area. The semiconductor device applies a folded bit line structure to a 6F2 structure so as to promote competitiveness of a net die, resulting in reduction of production costs. The semiconductor device implements various test patterns for defect analysis, wherein a conventional 6F2-layout open bit line has difficulty in using the test patterns, resulting in an increased production yield. The semiconductor device reduces noise of a sense amplifier, and performs mat-basis repairing, resulting in an increased production yield. | 04-14-2011 |
20110085366 | DEVICE - A device includes first to N-th (N is an integer of 2 or more) semiconductor chips stacked. These semiconductor chips have substantially the same configuration, and each includes an identification flag memory circuit including first to N-th memory units and a plurality of through electrodes connected to the identification flag memory circuit. Each of the through electrodes is connected to or masked with respect to the corresponding one of the through electrodes of the underlying semiconductor chip, such that an identification flag is stored in n-th (n indicates 1, 2, . . . , and N) memory units of the n-th semiconductor chips sequentially in the stacking order in response to a clock signal input in common to the first to N-th semiconductor chips, and the storage of the identification flag in the N-th memory unit of the N-th semiconductor chip can be detected from the lower side of the first semiconductor chip. | 04-14-2011 |
20110090727 | Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at Synchronous Memory Devices - A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line. | 04-21-2011 |
20110090728 | MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device. | 04-21-2011 |
20110096583 | Semiconductor modules and signal line layout methods thereof - A memory module and a layout method of the memory module. The memory module includes memory devices connected to corresponding tabs through corresponding damping resistors formed on a printed circuit board and includes a first signal line group in a first region between the memory devices and the damping resistors and a second signal line group in a second region between the corresponding damping resistors and the connecting terminals. | 04-28-2011 |
20110103121 | STACKED SEMICONDUCTOR DEVICE AND AUTOMATIC CHIP RECOGNITION SELECTION CIRCUIT - A semiconductor device includes a plurality of stacked chips which are allocated with different self-chip addresses. Each of the plurality of stacked chips includes a frequency change circuit, a self-address storing circuit and a determination circuit. The frequency change circuit changes a first frequency of a signal into a second frequency of the signal. The self-address storing circuit stores a chip select address that is supplied to other chips, in a period of time when the signal as input to the frequency change circuit is different in logic level from the signals as input to the frequency change circuits in the other chips. The determination circuit determines whether the chip select address is identical to the self-chip address. | 05-05-2011 |
20110103122 | SYSTEM AND METHOD FOR OPTIMIZING INTERCONNECTIONS OF COMPONENTS IN A MULTICHIP MEMORY MODULE - An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub. | 05-05-2011 |
20110116296 | Non-volatile semiconductor memory device - A non-volatile semiconductor memory device includes: a memory component in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one of the electrodes of the memory component is connected with a reference electric potential; and a load capacitance changing unit that changes load capacitance of a sense node of the sense amplifier to which the discharge electric potential is input or both the load capacitance of the sense node and load capacitance of a reference node of the sense amplifier to which the reference electric potential is input in accordance with the logic of the information read out by the memory component. | 05-19-2011 |
20110116297 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 05-19-2011 |
20110116298 | Memory emulation using resistivity-sensitive memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as HDD, DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 05-19-2011 |
20110128764 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes a first amplifier circuit, a second amplifier circuit, first and second bit lines coupled to the first amplifier circuit, third and fourth bit lines coupled to the second amplifier circuit, a first equalizer circuit being coupled to the first and second bit lines, and a second equalizer circuit being coupled between the second and third bit lines. The second equalizer circuit being closer to the second amplifier circuit than the first equalizer circuit, the first equalizer circuit being closer to the first amplifier circuit than the second equalizer circuit. | 06-02-2011 |
20110141788 | PAGE REGISTER OUTSIDE ARRAY AND SENSE AMPLIFIER INTERFACE - A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits. | 06-16-2011 |
20110141789 | MEMORY MODULE AND MEMORY SYSTEM - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 06-16-2011 |
20110149628 | Programming Phase Change Memories Using Ovonic Threshold Switches - A phase change memory using an ovonic threshold switch selection device may be programmed from one state to another by first turning on the ovonic threshold switch. After the voltage across the cell has fallen, the cell may then be biased to program the cell to the desired state. | 06-23-2011 |
20110164444 | RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory includes a stacked layer structure stacked on a semiconductor substrate in order of a first conductive line, a first variable resistance element, a second conductive line, a second variable resistance element, . . . a n-th conductive line, a n-th variable resistance element and a (n+ | 07-07-2011 |
20110164445 | SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS - A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips | 07-07-2011 |
20110176345 | ELECTRONIC APPARATUS - An electronic apparatus is provided. A PCB has first and second signal paths therein. First and second fingers are disposed on the first and second signal paths, respectively. A controller is coupled to a first memory via the first finger and a second memory via the second finger, and accesses the first and second memories through the first and second signal paths, respectively. The first and second signal paths share a common segment between the controller and a branch point. First and second components are disposed between the first finger and the branch point and between the second finger and the branch point, respectively. The distances between the first component and the branch point and between the second component and the branch point are smaller than or equal to the distance between the first component and the first finger and between the second component and the second finger, respectively. | 07-21-2011 |
20110176346 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, semiconductor memory device including: a circuit substrate in which a circuit pattern is formed; a plurality of semiconductor memories mounted via a solder on both surfaces of the circuit substrate; a connector disposed at one end part of the circuit substrate for connection with a host device; and a resin mold part that seals the both surfaces of the circuit substrate. The resin mold part does not seal a region in which the connector is disposed and collectively seals regions in which the plurality of semiconductor memories are disposed. | 07-21-2011 |
20110182098 | INTEGRATED CIRCUITS AND METHODS FOR FORMING THE SAME - An integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along a direction a first longitudinal direction. | 07-28-2011 |
20110182099 | SEMICONDUCTOR MEMORY DEVICE FOR REDUCING BIT LINE COUPLING NOISE - A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines. | 07-28-2011 |
20110182100 | SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY - A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed in a matrix shape, each word line is disposed in the order like WLA | 07-28-2011 |
20110188281 | Local bit lines and methods of selecting the same to access memory elements in cross-point arrays - Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements. | 08-04-2011 |
20110188282 | Memory architectures and techniques to enhance throughput for cross-point arrays - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement. | 08-04-2011 |
20110188283 | Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter. | 08-04-2011 |
20110188284 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory. | 08-04-2011 |
20110194326 | MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS - Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node. | 08-11-2011 |
20110199803 | Semiconductor device with a selection circuit selecting a specific pad - A semiconductor device includes a selection circuit for selecting a specific pad of a semiconductor memory. The semiconductor device is configured to produce a signal determined by a pin array by the selection circuit. | 08-18-2011 |
20110199804 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND RELATED METHOD OF OPERATION - A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate. | 08-18-2011 |
20110222328 | DISTRIBUTED SEMICONDUCTOR DEVICE METHODS, APPARATUS, AND SYSTEMS - Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice. | 09-15-2011 |
20110228581 | STACKED MEMORY DEVICE AND METHOD OF REPAIRING SAME - A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield. | 09-22-2011 |
20110228582 | STACKED MEMORY DEVICE AND METHOD OF FABRICATING SAME - A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit. | 09-22-2011 |
20110235385 | SEMICONDUCTOR MEMORY APPARATUS WITH POWER-MESHED STRUCTURE - A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines. | 09-29-2011 |
20110235386 | Semiconductor Memory Device and Manufacturing Method of the Same - The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor. | 09-29-2011 |
20110242869 | THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF - A three-dimensional stacked semiconductor integrated circuit including a plurality of stacked chips. The semiconductor integrated circuit is configured to simultaneously select the plurality of chips in response to an external command and an address, and to activate one of memory banks which are aligned on the same line in a vertical direction, among a plurality of memory banks included in the plurality of chips. | 10-06-2011 |
20110242870 | STACKED MEMORY AND DEVICES INCLUDING THE SAME - In one embodiment, the stacked memory includes a first group of stacked memory chips, a second group of stacked memory chips, and connection terminals configured to electrically connect a first memory chip among the stacked memory chips in the first group to a second memory chip among the stacked memory chips in the second group. | 10-06-2011 |
20110242871 | Vertically stacked third-dimensional embedded re-writeable non-volatile memory and registers - A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations. | 10-06-2011 |
20110242872 | SEMICONDUCTOR DEVICE - A highly-reliable, highly-integrated large-capacity phase-change memory is achieved. For this purpose, for example, memory tiles MT | 10-06-2011 |
20110249481 | Generating ROM bit cell arrays - A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area. Thus the system designer can reuse an existing memory architecture, yet still retain an advantageous degree of flexibility with regard to performance characteristic selection of the final ROM bit cell array. | 10-13-2011 |
20110267864 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a first memory chip, a second memory chip, and a control chip. The first chip includes a first inductor configured to transmit/receive a signal, and a memory cell. The second chip is disposed on the first chip and includes a second inductor configured to transmit/receive a signal, and a memory cell. The control chip includes a control circuit configured to control the first and second chips, and a third inductor configured to transmit/receive a signal to/from the first and second inductors. The outer peripheries of the first and second inductors are included in a closed space produced by extending the outer periphery of the third inductor in a direction perpendicular to a plane that includes the third inductor. The inductance of the third inductor is greater than at least one of the inductances of the first and second inductors. | 11-03-2011 |
20110267865 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 11-03-2011 |
20110286254 | Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein - A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard. | 11-24-2011 |
20110292707 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines. | 12-01-2011 |
20110299314 | Non-Volatile Memory Having 3d Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines - A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array. | 12-08-2011 |
20110299315 | COMMUNICATION CIRCUIT FOR DRIVING A PLURALITY OF DEVICES - A system and method is provided for transmitting a signal to a plurality of slave devices (e.g., memory devices, etc.) via a communication circuit having a plurality of segments that are substantially equal in length and/or impedance. Specifically, according to one embodiment of the invention, an electronic system includes a processor, a plurality of memory devices, and a communication circuit (i.e., a bus) having a central node and a plurality of segments. Specifically, the plurality of segments are used to connect the plurality of devices (e.g., the processor, the plurality of memory devices) to the central node. For example, the processor is connected to the central node via a primary segment, the first memory device (M | 12-08-2011 |
20110305057 | SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND DATA PROCESSING SYSTEM INCLUDING THESE - In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened. | 12-15-2011 |
20110310649 | Stacked Memory Module and System - A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system. | 12-22-2011 |
20110317463 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing the first lines, and a plurality of memory cells arranged at intersections of the first lines and the second lines, each memory cell having one end connected to the first line and the other end connected to the second line; a first control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the first line to select and drive the first line; and a second control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the second line to select and drive the second line. | 12-29-2011 |
20120002455 | MINITURIZATION TECHNIQUES, SYSTEMS, AND APPARATUS RELATNG TO POWER SUPPLIES, MEMORY, INTERCONNECTIONS, AND LEDS - Miniaturization techniques, systems, and apparatus relating to power supplies, memory, interconnections, and LEDS are described herein. Specifically, some aspects of the invention relate to techniques for miniaturization of power supplies. Other aspects relate to systems and methods for optimizing memory performance in a computer device or system. Still further, some aspects relate to systems and methods for miniaturizing and optimizing memory layout on a circuit board. Other aspects relate to systems and methods for attaching an integrated circuit, which comprises an array of pins, to a circuit board through the use of an adaptor that comprises a BGA, and which is configured to electrically and physically attach to the circuit board. Furthermore, some aspects relate to systems and methods for achieving activation of at least one multi-color LED, such as a bi-color or tri-color LED, using multiple electrical ground outputs or signals intended to activate only a single unicolor LED. | 01-05-2012 |
20120014156 | DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME - A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal. | 01-19-2012 |
20120026772 | MEMORY MODULE AND LAYOUT METHOD THEREFOR - The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector. | 02-02-2012 |
20120044733 | Single Device Driver Circuit to Control Three-Dimensional Memory Element Array - A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal. | 02-23-2012 |
20120063190 | COMPLEX SEMICONDUCTOR DEVICE FOR USE IN MOBILE EQUIPMENT - Provided is a complex semiconductor device. The complex semiconductor device includes first memory chips in a first package, second memory chips in a second package configured for mass storage of data, and a controller packaged with either the first package or the second package in a complex package. The controller is connected to the first package via a first internal bus and to the second package via a second internal bus, and the first package, second package and controller are commonly packaged within a single complex package. | 03-15-2012 |
20120069620 | System Including Vertically Stacked Embedded Non Flash Re Writable Non Volatile Memory - A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 03-22-2012 |
20120081940 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type. | 04-05-2012 |
20120106225 | Array-Based Integrated Circuit with Reduced Proximity Effects - An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array. | 05-03-2012 |
20120106226 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor. | 05-03-2012 |
20120113704 | IN-PACKAGE MICROELECTRONIC APPARATUS, AND METHODS OF USING SAME - A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s. | 05-10-2012 |
20120120703 | MEMORY DEVICE WITH ASYMMETRICAL BIT CELL ARRAYS AND BALANCED RESISTANCE AND CAPACITANCE - An SRAM or other semiconductor integrated circuit device includes a memory cell array having a layout portion in which a plurality of cell arrays extend along a substantially parallel pair of bit lines. Each cell array is separated from an adjacent cell array by a strap cell. As the cell arrays extend along the bit line pair, they form an alternating sequence of first and second cell arrays in which the first cell array is asymmetric with respect to the second cell array. In each first cell array, the bit line is coupled to a greater number of contacts and in each second cell array, the complementary bit line is coupled to a greater number of contacts. The first cell arrays may all include the same layout and orientation. | 05-17-2012 |
20120134192 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device includes: a plurality of mats; a plurality of sense amplifier regions disposed on a side of the plurality of mats; and a plurality of main bit lines overlapping with a plurality of secondary bit lines, respectively, in regions for the plurality of mats, wherein the plurality of main bit lines and the plurality of secondary bit lines are formed in regions for the plurality of mats and the plurality of sense amplifier regions. | 05-31-2012 |
20120134193 | SEMICONDUCTOR DEVICE HAVING PLURAL MEMORY CHIP - A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions. | 05-31-2012 |
20120140542 | Arrays of Nonvolatile Memory Cells - Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F | 06-07-2012 |
20120147644 | CONTINUOUS MESH THREE DIMENSIONAL NON-VOLATILE STORAGE WITH VERTICAL SELECT DEVICES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 06-14-2012 |
20120147645 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH DUAL GATED VERTICAL SELECT DEVICES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 06-14-2012 |
20120147646 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH CONNECTED WORD LINES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 06-14-2012 |
20120147647 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH THREE DEVICE DRIVER FOR ROW SELECT - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 06-14-2012 |
20120147648 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH DUAL GATE SELECTION OF VERTICAL BIT LINES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 06-14-2012 |
20120147649 | Non-Volatile Memory Having 3d Array of Read/Write Elements with Low Current Structures and Methods Thereof - A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size. | 06-14-2012 |
20120147650 | Non-Volatile Memory Having 3D Array of Read/Write Elements with Vertical Bit Lines and Select Devices and Methods Thereof - A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate. | 06-14-2012 |
20120163060 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing the first lines, and a plurality of memory cells arranged at intersections of the first lines and the second lines, each memory cell having one end connected to the first line and the other end connected to the second line; a first control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the first line to select and drive the first line; and a second control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the second line to select and drive the second line. | 06-28-2012 |
20120170345 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The stacked semiconductor device including a first chip, a second chip positioned on the first chip, the second chip being connected to a plurality of first penetration electrodes and including a first memory and a memory controller that are each controlled by the first chip, and a second memory positioned on the second chip and connected to a plurality of second penetration electrodes and controlled by the memory controller. | 07-05-2012 |
20120170346 | MEMORY SYSTEM WITH SECTIONAL DATA LINES - The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay. | 07-05-2012 |
20120170347 | MEMORY SYSTEM WITH SECTIONAL DATA LINES - The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay. | 07-05-2012 |
20120182776 | DRAM DEVICE WITH BUILT-IN SELF-TEST CIRCUITRY - A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells. | 07-19-2012 |
20120182777 | MEMORY MODULE CUTTING OFF DM PAD LEAKAGE CURRENT - A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode. | 07-19-2012 |
20120206952 | SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY - A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA | 08-16-2012 |
20120212988 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. | 08-23-2012 |
20120212989 | MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors. | 08-23-2012 |
20120218803 | MEMEORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems may include an interface chip, a first memory die having at least one memory array disposed on the interface chip, and a second memory die having at least one memory array disposed on the first memory die. The first memory die can include a plurality of vias configure allow a first plurality of through wafer interconnects (TWIs) to couple the interface chip with the second memory die, and the interface chip can be configured to communicatively couple the first memory die and the second memory die. Other apparatus, systems, and methods are disclosed. | 08-30-2012 |
20120218804 | MAGNETIC MEMORY DEVICE - The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed. | 08-30-2012 |
20120250386 | CIRCUIT PROVIDING LOAD ISOLATION AND NOISE REDUCTION - Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports. | 10-04-2012 |
20120250387 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - Disclosed herein is a device that includes a plurality of stacked core chips and an interface chip that controls the core chips. Each of the core chips includes a memory cell array, a penetration electrode, and an output circuit that outputs read data that are read from the memory cell array to the penetration electrode. The penetration electrode respectively provided in the core chips are commonly connected with each other, and the output circuits respectively provided in the core chips are activated in response to a read clock signal supplied from the interface chip. | 10-04-2012 |
20120257433 | MEMORY SYSTEM WITH DATA LINE SWITCHING SCHEME - A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other. | 10-11-2012 |
20120257434 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 10-11-2012 |
20120262973 | Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells - An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed. | 10-18-2012 |
20120262974 | MEMORY MODULE AND MEMORY SYSTEM - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 10-18-2012 |
20120262975 | SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS - A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips | 10-18-2012 |
20120294058 | MULTI-DIE MEMORY DEVICE - A multi-die memory device includes a first die of a first type and configured to electrically interface with an external processor via a first synchronous interface operating at a first clock rate, and at least one second die of a second type and configured for data storage. Each second die transacts data with the first die via a second synchronous interface operating at a second clock rate, where the first clock rate is an integer multiple of the second clock rate, and where a timing reference associated with the second synchronous interface is transmitted by the first die to the second die. | 11-22-2012 |
20120300527 | NONVOLATILE MEMORY INCLUDING PLURAL MEMORY CELLS STACKED ON SUBSTRATE - According to example embodiments, a nonvolatile memory device includes a memory cell array including a plurality of memory cells stacked on a substrate, a plurality of word lines connected with the memory cell array, a plurality of pass voltage generators, and a voltage control circuit. The pass voltage generators each include a plurality of current paths and are configured to generate pass driving signals applied to unselected word lines of the plurality of word lines. The voltage control circuit is configured to control rising slopes of the pass driving signals generated from the plurality of pass voltage generators, based on adjusting the number of current paths in each pass voltage generator used to generate each driving signal. | 11-29-2012 |
20120300528 | Stacked Memory Module and System - A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system. | 11-29-2012 |
20120307542 | LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCESS MEMORY ELEMENTS IN CROSS-POINT ARRAYS - Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements. | 12-06-2012 |
20120320651 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a semiconductor substrate; a memory cell array provided above the semiconductor substrate and including a plurality of memory cells that are stacked; a plurality of bit lines connected electrically to the plurality of memory cells; and a plurality of sense amplifiers connected to the bit lines via bit line connection lines. The bit line connection lines have every adjacent N lines (where N is an integer of 2 or more) as one group. The sense amplifiers are arranged in a number smaller than N in a first direction that the bit line connection lines extend. An M number of the sense amplifiers are arranged in a width of a P number of groups in a second direction intersecting the first direction. The M number being larger than the P number | 12-20-2012 |
20130003433 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction. | 01-03-2013 |
20130003434 | METHOD FOR OPERATING A SEMICONDUCTOR STRUCTURE - A method for operating a semiconductor structure is provided. The semiconductor structure comprises a substrate, a first stacked structure, a dielectric element, a conductive line, a first conductive island and a second conductive island. The first stacked structure is formed on the substrate. The first stacked structure comprises first conductive strips and first insulating strips stacked alternately. The first conductive strips are separated from each other by the first insulating strips. The dielectric element is formed on the first stacked structure. The conductive line is formed on the dielectric element. The first conductive island and the second conductive island on opposite sidewalls of the first stacked structure are separated from each other. The method for operating the semiconductor structure comprises respectively applying a first voltage to the first conductive island and applying a second voltage to the second conductive island. | 01-03-2013 |
20130010514 | SEMICONDUCTOR MODULE HAVING MODULE SUBSTRATE AND PLURAL SEMICONDUCTOR DEVICES MOUNTED THEREON - Disclosed herein is a semiconductor module that includes a module substrate and a plurality of semiconductor devices mounted on the module substrate. Among the semiconductor devices, two of the semiconductor devices adjacent in a first direction differ in a mounting direction by 180°. Among the semiconductor devices, two of the semiconductor devices adjacent in a second direction perpendicular to the first direction differing in a mounting direction by 180°. | 01-10-2013 |
20130010515 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A method includes preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip, data electrodes of the first and second memory chips being electrically connected and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip, accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time, accessing the second memory chip so that a data signal is outputted and appears on the side of the second main surface of the second memory chip in second access time, and setting output timing adjustment information into at least one of the first and second memory chips. | 01-10-2013 |
20130021832 | SEMICONDUCTOR DEVICE - In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have. | 01-24-2013 |
20130039110 | 3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE - Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer. | 02-14-2013 |
20130058146 | Three-Dimensional Offset-Printed Memory - The present invention discloses a three-dimensional offset-printed memory (3D-oP). Compared with a conventional three-dimensional mask-programmed read-only memory (3D-MPROM), it has a lower data-mask count and thereby a lower data-mask cost. The mask-patterns for different memory levels/bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to said data-mask. Accordingly, data-patterns are printed into different memory levels/bits-in-a-cell from a same data-mask. | 03-07-2013 |
20130058147 | Three-Dimensional Writable Printed Memory - The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data. | 03-07-2013 |
20130070506 | SEMICONDUCTOR DEVICE HAVING STACKED LAYERS - A semiconductor device is disclosed in which there are provided a first substrate including memory cells and at least one bit line electrically coupled to the memory cells, and a second substrate including a sense amplifier. Each of the memory cells includes a first transistor, and the sense amplifier includes a second transistor. The second substrate is stacked with the first substrate such that the sense amplifier amplifies data transferred through the bit line from a selected one of the memory cells. The first transistor is lower in carrier mobility than the second transistor. | 03-21-2013 |
20130070507 | SEMICONDUCTOR MEMORY DEVICE - A memory device is provided. The memory device includes a first semiconductor chip including a memory element and a peripheral circuit configured to write or read data in or from the memory element; and a second semiconductor chip configured to perform an input/output function of data or signals exchanged between an external device and the first semiconductor chip. | 03-21-2013 |
20130100722 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A 3D non-volatile memory device including a substrate that includes a first region and a second region; a pipe channel film that is formed on the substrate in the first region; a pipe gate that substantially encloses the pipe channel film; and a driving gate that is formed on the substrate in the second region and has at least one dummy pattern. | 04-25-2013 |
20130107602 | 3-D NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME | 05-02-2013 |
20130128647 | DATA PROCESSING DEVICE - A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board. | 05-23-2013 |
20130135915 | SEMICONDUCTOR APPARATUS - Provided is a semiconductor apparatus having memory chips stacked along a direction, each memory chip having bit lines and word lines arranged therein and memory blocks each having memory cells. The semiconductor apparatus includes: bit line sense amplifiers coupled to the bit lines arranged in each of the memory chips and configured to enable the bit lines of an enabled memory chip among the plurality of bit lines; and sub word line drivers coupled to the word lines arranged in each of the memory chips and configured to enable word lines of the enabled memory chip among the plurality of word lines. The bit line sense amplifiers and sub word line drivers are provided in any one of the memory chips. | 05-30-2013 |
20130135916 | MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND DATA REGISTER BUFFER - Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors. | 05-30-2013 |
20130148398 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) non-volatile memory device according to an embodiment of the present invention includes a plurality of vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of memory cells stacked alternately along the plurality of vertical channel layers, and an air gap formed in the plurality of interlayer insulating layers disposed between the plurality of memory cells, so that capacitance between word lines is reduced to thus improve a program speed. | 06-13-2013 |
20130148399 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell. | 06-13-2013 |
20130155750 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively driving the first and second wirings. The plurality of first wirings that are specified and selectively driven at the same time by one of a plurality of address signals are separately arranged with other first wirings interposed therebetween within the memory cell array when a certain potential difference is applied to a selected memory cell positioned at an intersection between the first and second wirings by the control circuit. | 06-20-2013 |
20130155751 | MEMORY DEVICES HAVING BREAK CELLS - A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage. | 06-20-2013 |
20130170274 | SEMICONDUCTOR MEMORY DEVICE STORING MEMORY CHARACTERISTIC INFORMATION, MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF - A semiconductor memory device includes a cell array including a plurality of regions accessed by first addresses, where the plurality of regions including at least two groups of regions having respectively different memory characteristics. The device further includes a nonvolatile array for nonvolatile storage of group information indicative of which of the least two groups each of the plurality of regions belongs. | 07-04-2013 |
20130176763 | STACKED MEMORY WITH REDUNDANCY - A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path. | 07-11-2013 |
20130182483 | Discrete Three-Dimensional Memory Comprising Off-Die Address/Data Translator - The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address-data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical space for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies. | 07-18-2013 |
20130201743 | Three-Dimensional Memory Comprising an Integrated Intermediate-Circuit Die - The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least an integrated intermediate-circuit die comprising both a read/write-voltage generator (V | 08-08-2013 |
20130215659 | LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME - A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer. | 08-22-2013 |
20130229846 | Memories with Cylindrical Read/Write Stacks - A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material. | 09-05-2013 |
20130229847 | MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS - Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node. | 09-05-2013 |
20130235639 | MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN - A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. | 09-12-2013 |
20130258740 | Small-Grain Three-Dimensional Memory - The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor. | 10-03-2013 |
20130258741 | SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY - A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA | 10-03-2013 |
20130258742 | SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS - A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated. | 10-03-2013 |
20130279232 | APPARATUS, SYSTEM, AND METHOD FOR TRANSFERRING HEAT FROM MEMORY COMPONENTS - The apparatus to transfer heat from memory components includes a first non-volatile memory component and a second non-volatile memory component. The apparatus includes a heat spreading material in thermal communication with the first non-volatile memory component and the second non-volatile memory component. The heat spreading material is configured to transfer heat from the first non-volatile memory component and the second non-volatile memory component. | 10-24-2013 |
20130286706 | Memory Modules and Devices Supporting Configurable Data Widths - Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations. | 10-31-2013 |
20130294132 | Memory Arrays - Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F | 11-07-2013 |
20130314967 | MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME - A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F | 11-28-2013 |
20130314968 | OFFSETTING CLOCK PACKAGE PINS IN A CLAMSHELL TOPOLOGY TO IMPROVE SIGNAL INTEGRITY - The disclosed embodiments relate to the design of a memory system which includes a set of one or more memory modules, wherein each memory module in the set has a clamshell configuration, wherein pairs of opposing memory packages containing memory chips are located on opposite sides of the memory module. The memory system also includes a multi-drop path containing signal lines which pass through the set of memory modules, and are coupled to memory packages in the set of memory modules. For a given signal line in the multi-drop path, a first memory package and a second memory package that comprise a given pair of opposing memory packages are coupled to the given signal line at a first location and a second location, respectively, wherein the first location and the second location are separated from each other by a distance d | 11-28-2013 |
20130329478 | Semiconductor Devices Having a Three Dimensional Stacked Structure and Methods of De-Skewing Data Therein - A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard. | 12-12-2013 |
20130329479 | Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells - An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed. | 12-12-2013 |
20130336036 | NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH BIT LINE VOLTAGE CONTROL AND METHODS THEREOF - In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage. | 12-19-2013 |
20130336037 | 3D MEMORY HAVING VERTICAL SWITCHES WITH SURROUND GATES AND METHOD THEREOF - A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs. | 12-19-2013 |
20130336038 | NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH STAIRCASE WORD LINES AND VERTICAL BIT LINES AND METHODS THEREOF - In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. | 12-19-2013 |
20130336039 | MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE - A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin. | 12-19-2013 |
20130343112 | METHOD FOR PRECONDITIONING THIN FILM STORAGE ARRAY FOR DATA RETENTION - A method includes over-programming thin film storage (TFS) memory cells on a semiconductor wafer with a first voltage that is higher than a highest voltage used to program the memory cells during normal operation of the memory cells. With the memory cells in an over-programmed state, the wafer is exposed to a first temperature above a product specification temperature for a period of time sufficient to induce redistribution of charge among storage elements in the memory cells. | 12-26-2013 |
20140003113 | SEMICONDUCTOR DEVICE HAVING OPEN BITLINE STRUCTURE | 01-02-2014 |
20140016388 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A system includes a first device, a second device, and a bus interconnecting the first and second devices to each other, wherein the first device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode. | 01-16-2014 |
20140029325 | APPARATUS AND METHODS FOR A PHYSICAL LAYOUT OF SIMULTANEOUSLY SUB-ACCESSIBLE MEMORY MODULES - A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector. | 01-30-2014 |
20140036564 | NON-VOLATILE MEMORY DEVICE WITH CLUSTERED MEMORY CELLS - An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row. | 02-06-2014 |
20140043883 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 02-13-2014 |
20140050003 | VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND DRIVING METHOD OF VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE - A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state. Both the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in the inactive state. | 02-20-2014 |
20140056048 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats. | 02-27-2014 |
20140063887 | STACKED DRAM DEVICE AND METHOD OF MANUFACTURE - A memory stack includes a number of memory dies including a master die and one or more slave dies. The slave die can be converted to a master die by further processing. The slave die includes a memory core having memory cell arrays. The slave die also includes first and second metal layers that form first and second distribution lines in the memory core, respectively. An interface circuit in the slave die is decoupled from the first and second metal layers. | 03-06-2014 |
20140071729 | STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE - A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). | 03-13-2014 |
20140104915 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell, a pair of local bit lines connected to the memory cell, first and second transistors, one end of the current channel of each connected to a power supply and the other end of the current channel of each connected to one of the local bit lines, third and fourth transistors, one end of the current channel of each connected to one of the local bit lines, the other end of the current channel of each connected to one of the global bit lines, fifth and sixth transistors, one end of the current channel of each connected to one of the global bit lines and the other end of the current channel of which connected to the power supply. The device further includes a control unit configured to control the transistors. | 04-17-2014 |
20140104916 | SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS - A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated. | 04-17-2014 |
20140104917 | SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS - A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips | 04-17-2014 |
20140112046 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 04-24-2014 |
20140119090 | STACKED DYNAMIC RANDOM ACCESS MEMORY - A memory includes at least one first substrate on which unit memory arrays are disposed as a matrix type, each unit memory array including unit memory cells disposed in an array, a second substrate stacked with the at least one first substrate, the second substrate including a sense amplifier region in which sense amplifiers configured to sense information stored in the unit memory cells are disposed, and a plurality of vertical conduction traces configured to electrically connect the at least one first substrate with the second substrate. The sense amplifier region is disposed in a memory region of the second substrate, wherein the memory region of the second substrate corresponds to the memory region of the first substrate. | 05-01-2014 |
20140133208 | MEMORY ARCHITECTURES HAVING WIRING STRUCTURES THAT ENABLE DIFFERENT ACCESS PATTERNS IN MULTIPLE DIMENSIONS - Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions. | 05-15-2014 |
20140133209 | MEMORY ARCHITECTURES HAVING WIRING STRUCTURES THAT ENABLE DIFFERENT ACCESS PATTERNS IN MULTIPLE DIMENSIONS - Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions. | 05-15-2014 |
20140146589 | SEMICONDUCTOR MEMORY DEVICE WITH CACHE FUNCTION IN DRAM - A semiconductor memory device is provided which includes a dynamic random access memory including a memory cell array formed of dynamic random access memory cells; a cache memory formed at the same chip as the dynamic random access memory and configured to communicate with a processor or an external device; and a controller connected with the dynamic random access memory and the cache memory in the same chip and configured to control a dynamic random access function and a cache function. | 05-29-2014 |
20140146590 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device | 05-29-2014 |
20140160826 | DATA PROCESSING DEVICE - A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board. | 06-12-2014 |
20140177311 | MEMORY DEVICE STRUCTURE WITH DECODERS IN A DEVICE LEVEL SEPARATE FROM THE ARRAY LEVEL - A memory device structure and method of fabricating the memory device structure is described. The memory device structure has a memory array disposed in a array level and peripheral circuitry, including decoders and other peripheral circuitry, disposed in a device level. The array of memory cells has a perimeter that defines a cylinder that extends above and beneath the array of memory cells. The decoders and the other peripheral circuitry or at least part of the decoders and the other peripheral circuitry are disposed within the cylinder in the device level. The memory device structure also includes a plurality of pads in a pad level. A first plurality of inter-level conductive lines electrically couples the decoders to the bit lines and word lines in the array of memory cells. | 06-26-2014 |
20140185350 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal. | 07-03-2014 |
20140185351 | NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING - A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits. | 07-03-2014 |
20140198552 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array. | 07-17-2014 |
20140218995 | SEMICONDUCTOR CHIPS - A semiconductor chip includes a core region having a plurality of first memory cells and a first edge adjacent to a first side of the core region. The first edge includes a first region and a second region. The first region includes a plurality of second memory cells, and the second region includes a first pad portion through which at least one of an address signal, a command signal, a clock signal, a data signal and a control signal is inputted or outputted. | 08-07-2014 |
20140218996 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface. | 08-07-2014 |
20140218997 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface. | 08-07-2014 |
20140241022 | MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS - Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node. | 08-28-2014 |
20140247637 | MULTI-DIE MEMORY DEVICE - A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays. | 09-04-2014 |
20140321185 | FOUR PORT MEMORY WITH MULTIPLE CORES - A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks. | 10-30-2014 |
20140321186 | STACKED MEMORY WITH REDUNDANCY - A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information. | 10-30-2014 |
20140321187 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. | 10-30-2014 |
20140340952 | APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD - An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to faun a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates. | 11-20-2014 |
20140362629 | SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT - A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements. | 12-11-2014 |
20140376295 | MEMORY DEVICE AND SYSTEM INCLUDING THE SAME - A memory device includes a plurality of first dies stacked on a substrate, and a second die configured to perform an error correction operation on data written in the first dies and data read out from the first dies. | 12-25-2014 |
20150009737 | SELF-REFRESH ADJUSTMENT IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS - Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. | 01-08-2015 |
20150009738 | PAD SELECTION IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS - Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. | 01-08-2015 |
20150009739 | MEMORY DEVICES WITH SERIALLY CONNECTED SIGNALS FOR STACKED ARRANGEMENTS - Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. | 01-08-2015 |
20150016172 | QUERY OPERATIONS FOR STACKED-DIE MEMORY DEVICE - An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device. | 01-15-2015 |
20150029773 | CONTEXT PROTECTION FOR A COLUMN INTERLEAVED MEMORY - A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits. | 01-29-2015 |
20150029774 | STACKED DEVICE IDENTIFICATION ASSIGNMENT - Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die. | 01-29-2015 |
20150036405 | Memory Devices - Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage. | 02-05-2015 |
20150036406 | DATA PROCESSING DEVICE - A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board. | 02-05-2015 |
20150049534 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of first stacked structures including a plurality of first material layers at ends of which first contact regions are defined, a plurality of second stacked structures including a plurality of second material layers, wherein second contact regions are defined at ends of the second material layers and arranged between the first stacked structures so that the first contact regions and the second contact regions overlap each other, and a plurality of lines coupled in common to the first contact regions and the second contact regions. | 02-19-2015 |
20150049535 | SEMICONDUCTOR STORAGE DEVICE - Provided is a semiconductor storage device with which it is possible to write information to individual memory cells in which a storage node is configured with an oxide semiconductor insulated-gate FET source and a terminal of a capacitor element being connected. A storage node is configured by connecting a source of a first transistor to one terminal of a capacitor element. A drain of the first transistor and a source of a second transistor are connected to each other. A drain of the second transistor is a data input terminal. A first control terminal, which is formed by a gate of the first transistor being connected to another terminal of the capacitor element, is connected to a wordline, which extends in the row direction. A second control terminal, which is formed of a gate of the second transistor terminal, is connected to a write control line, which extends in the column direction. The storage node is connected to a gate of a third transistor, and a current flowing between a drain and a source of the third transistor is controlled according to a voltage level of the storage node. | 02-19-2015 |
20150078055 | MEMORY MODULE AND MANUFACTURING METHOD THEREOF - A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins. | 03-19-2015 |
20150078056 | Arrays Of Nonvolatile Memory Cells - Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F | 03-19-2015 |
20150085555 | PACKAGED MEMORY DIES THAT SHARE A CHIP SELECT LINE - An apparatus includes a memory module, and the memory module includes a package. The package contains memory dies, and the memory dies share a chip select line. | 03-26-2015 |
20150092468 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats. | 04-02-2015 |
20150098260 | SEMICONDUCTOR MEMORY DEVICE HAVING MAIN WORD LINES AND SUB-WORD LINES - A plurality of memory mats classified into groups selected by bits of a row address, a main word driver for selecting a main word line based on bits of the row address, an FX driver for selecting a word driver selecting line based on bits regardless of the bits of the row address, and a plurality of sub-word drivers selected by the main word line and the word driver selecting line to drive the corresponding sub-word line are arranged. | 04-09-2015 |
20150103576 | MEMORY ARRANGEMENT - Among other things, techniques and systems are provided for activating a memory cell of a memory arrangement in preparation for at least one of a read operation or write operation. The memory arrangement comprises a word-line driver comprising at least a first input terminal and a second input terminal. The first input terminal is operably coupled to a first decoder and the second input terminal is operably coupled to a second decoder. When the word-line driver senses a first voltage at the first input terminal and a second voltage at the second input terminal, the word-line driver outputs a gate voltage signal which activates the memory cell. | 04-16-2015 |
20150103577 | SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER - In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. | 04-16-2015 |
20150109843 | MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) WITH VERTICAL MEMORY COMPONENTS, RELATED SYSTEMS AND METHODS - Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use. | 04-23-2015 |
20150117078 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of main amplifiers provided between memory cell arrays. One of the main amplifiers is disposed closer to one of the memory cell arrays than to the other of memory cell arrays, and the other of the main amplifiers is disposed closer to the other of the memory cell arrays than to the one of the memory cell arrays. Additional apparatus are disclosed. | 04-30-2015 |
20150117079 | SUB WORD LINE DRIVER AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other. | 04-30-2015 |
20150131356 | DATA PROCESSING DEVICE AND MANUFACTURING METHOD THEREOF - A method by which a defective memory cell can be efficiently excluded from a memory cell array is provided. In one embodiment, the memory cell array includes M word lines and (N+K) bit lines. K of the bit lines are spares (i.e., redundant bit lines). Programmable switches in a switch array are programmed so that the switch array connects a driver that drives the bit lines to N bit lines that are not connected to defective memory cells. The memory cell array is tested by a test circuit connected to the bit lines in such a manner that the test circuit transmits and receives a signal to and from the bit lines via the switch array. The test circuit may be formed using a reconfigurable circuit. Other embodiments may be claimed. | 05-14-2015 |
20150138862 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND FABRICATING METHODS THEREOF - A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure. | 05-21-2015 |
20150294692 | Mixed Three-Dimensional Printed Memory - The present invention discloses a mixed three-dimensional printed memory (3D-P). The slow contents (e.g., e.g., digital books, digital maps, music, movies, and/or videos) are stored in large memory blocks and/or large memory arrays, whereas the fast contents (e.g., operating systems, software, and/or games) are stored in small memory blocks and/or small memory arrays. | 10-15-2015 |
20150294693 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device | 10-15-2015 |
20150302898 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region. | 10-22-2015 |
20150302899 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first memory region including a plurality of first memory cells, two or more of which are simultaneously selected by a single address, and stores a first single datum; and a second memory region including a plurality of second memory cells, each of which is selected by the single address, and stores a second single datum. | 10-22-2015 |
20150302900 | SEMICONDUCTOR STACKED PACKAGE - A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. The semiconductor stacked package may include second circuit units disposed on each of the semiconductor chips and electrically disconnected with the coupling pads, connection pads disposed on each of the semiconductor chips and corresponding to the second circuit units, and blocking circuits coupled between the second circuit units and the connection pads. The semiconductor stacked package may also include bonding wires electrically connecting the bonding pads and the coupling pads. | 10-22-2015 |
20150302901 | SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT - A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements. | 10-22-2015 |
20150302917 | SRAM Cell and Cell Layout Method - Embodiments of the present disclosure include an array of SRAM cells, an SRAM cell, and methods of forming the same. An embodiment is an array of static random access memory (SRAM) cells including a plurality of overlapping rectangular regions. Each of overlapping rectangular regions including an entire first SRAM cell, a portion of a second adjacent SRAM cell in a first corner region of the rectangular region, and a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region. Embodiments also include multi-finger cell layouts. | 10-22-2015 |
20150305143 | MULTI-LAYER PRINTED CIRCUIT BOARD STRUCTURE, CONNECTOR MODULE AND MEMORY STORAGE DEVICE - A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer. | 10-22-2015 |
20150318034 | SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER - In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. | 11-05-2015 |
20150325273 | Discrete Three-Dimensional Vertical Memory - The present invention discloses a discrete three-dimensional vertical memory (3D-M | 11-12-2015 |
20150325282 | MEMORY DEVICE AND ELECTRONIC DEVICE - To provide a memory device with low power consumption. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer where the sense amplifier is provided. The memory cells are provided over a layer where the bit lines are provided. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor. | 11-12-2015 |
20150325283 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: a memory cell array including a plurality of memory cells disposed in a matrix; and a peripheral circuit adjacent to the memory cell array. Each of the memory cells includes: a capacitive element including a lower electrode having a cylinder shape extending in a direction perpendicular to a principal surface of a substrate; and a switch transistor provided between the capacitive element and a bit line, turning on/off of the switch transistor being controlled based on a potential of a word line. The peripheral circuit includes a signal line that is adjacent to the lower electrode in a horizontal direction parallel to the principal surface and is supplied with a fixed potential, or a pair of signal lines respectively supplied with complementary potentials. | 11-12-2015 |
20150325292 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH CONNECTED WORD LINES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 11-12-2015 |
20150332734 | Discrete Three-Dimensional Memory Comprising Off-Die Address/Data Translator - The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address/data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical spaces for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies. | 11-19-2015 |
20150332746 | MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES - A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. | 11-19-2015 |
20150332752 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device | 11-19-2015 |
20150340082 | SEMICONDUCTOR DEVICE - An intermediate mode is set between the active mode in which a threshold voltage is low and a standby mode in which a threshold voltage is high. When a mode is shifted from the active mode to the standby mode, the threshold voltage for the active mode is raised temporarily to a threshold voltage for the intermediate mode and then the threshold voltage for the intermediate mode is raised to the threshold voltage for the standby mode. When a mode is shifted from the standby mode to the active mode, the threshold voltage for the standby mode is lowered temporarily to the threshold voltage for the intermediate mode and then the threshold voltage for the intermediate mode is lowered to the threshold voltage for the active mode. | 11-26-2015 |
20150340083 | DUAL-PORT SRAM CONNECTION STRUCTURE - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (PD- | 11-26-2015 |
20150348613 | Multi-Die DRAM Banks Arrangement and Wiring - The various embodiments described herein include memory dies and methods for memory die communications. In one aspect, a method is performed at a first memory die with a plurality of memory banks and a plurality of contacts. The method includes: (1) coupling a first memory bank of the plurality of memory banks to a second memory die via the plurality of contacts; (2) transmitting data between the first memory bank and the second memory die via the plurality of contacts; and (3) receiving a control signal to couple a second memory bank of the plurality of memory banks to the second memory die. The method further includes, in response to receiving the control signal, coupling the second memory bank to the second memory die via the plurality of contacts; and transmitting data between the second memory bank and the second memory die via the plurality of contacts. | 12-03-2015 |
20150348626 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device. | 12-03-2015 |
20150357002 | STACKED MEMORY WITH REDUNDANCY - A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information. | 12-10-2015 |
20150357003 | STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN - A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks. | 12-10-2015 |
20150357004 | STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN - A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks. | 12-10-2015 |
20150364214 | RECLAIMABLE SEMICONDUCTOR DEVICE PACKAGE AND ASSOCIATED SYSTEMS AND METHODS - Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly ( | 12-17-2015 |
20150371683 | STACKED-DIE MULTI-PROCESSOR - A plurality of stacked dies has outer dies that permits high heat dissipation. A plurality of possessors is located on a first outer die. A plurality of memory elements located on a second outer die. An interconnect structure is located an inner die. | 12-24-2015 |
20150371687 | SYSTEMS AND METHODS FOR ACOUSTIC WAVE ENABLED DATA STORAGE - The present disclosure provides systems and methods for storing, reading, and writing data using particle-based acoustic wave driven shift registers. The shift registers may physically shift particles along rows and/or columns of wells through the interactions of two parallel surfaces. A transducer may generate an acoustic wave to displace one or more of the two parallel surfaces. The particles may be transferred to and/or otherwise constrained by a buffer surface during at least a portion of the acoustic wave, such that the particles may be shifted during one or more cycles of the acoustic wave. In various embodiments, the amplitude of the acoustic wave may correspond to the spacing distance between each of the wells. The wells may be physical and/or potential wells. | 12-24-2015 |
20150371698 | PRINTED CIRCUIT BOARD, AND PRINTED WIRING BOARD - A motherboard includes a main wiring as a transmission line for a signal transmitted by a memory controller, and a branching wiring branched from a branching point of the main wiring and connected to the memory device. Furthermore, the motherboard includes a branching wiring including a land to which a memory device may be joined and branched from a branching point, and an open stub formed extending from the land. According to such a structure, ringing in the waveform of a signal received by the receiving circuit may be suppressed at the time of both single-side mounting and double-side mounting, and also, ringing of a signal may be sufficiently suppressed in the case where the number of DIMMs used by the same substrate is changed. | 12-24-2015 |
20150371701 | MEMORY CHIP AND LAYOUT DESIGN FOR MANUFACTURING SAME - An embedded synchronous random access memory (SRAM) chip, includes a first single-port (SP) SRAM macro and a second SP macro. The first macro includes a first periphery circuit, and a plurality of first SRAM cells. The second macro includes a second periphery circuit, and a plurality of second SRAM cells. Further, each cell of the plurality of first SRAM cells is electrically connected to a write-assist circuitry, wherein the write assist circuitry is configured to assist the write cycle capability of each cell of the plurality of first SRAM cells. Further, each cell of the plurality of second SRAM cells do not include write assist circuitry. | 12-24-2015 |
20150380060 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; and second group segment input/output lines disposed to correspond to the second cell to array region when viewed in terms of the dummy bit lines. | 12-31-2015 |
20150380061 | SEMICONDUCTOR DEVICE - A semiconductor device includes a printed circuit board having a first surface and a second surface on a side opposite to the first surface. First pads are on the first surface of the printed circuit board. An interface part is mounted on the printed circuit board via the first pads and is configured to transfer a signal between the interface part and a host device. Second pads are also on the first surface and insulated from the interface part. A semiconductor memory and a controller are mounted on the first surface. First solder balls electrically connect the first pads and the controller. Second solder balls electrical connect the second pads and the controller. A plurality of third pads are disposed on the second surface and electrically connected to the second pads allowing direct connections to the controller and memory via the second pads. | 12-31-2015 |
20150380062 | MEMORY MODULE AND VIDEO CAMERA - According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside. | 12-31-2015 |
20150380102 | MEMORY DEVICE - A memory device includes first through fourth active regions arranged sequentially along a first direction, and which extend along a second direction different from the first direction; a first gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, and extending along the first direction; a second gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, extending along the second direction, and arranged so that no other gate electrodes are between the first gate electrode and the second gate electrode in the second direction; the first gate electrode extending between a first end and a second end; | 12-31-2015 |
20160012864 | STACKED SEMICONDUCTOR PACKAGE | 01-14-2016 |
20160012865 | SEMICONDUCTOR DEVICE HAVING INTERCONNECTION IN PACKAGE AND METHOD FOR MANUFACTURING THE SAME | 01-14-2016 |
20160012879 | MULTI CHANNEL SEMICONDUCTOR DEVICE HAVING MULTI DIES AND OPERATION METHOD THEREOF | 01-14-2016 |
20160012910 | STACKED SEMICONDUCTOR DEVICE | 01-14-2016 |
20160027477 | INTERLEAVED GROUPED WORD LINES FOR THREE DIMESIONAL NON-VOLATILE STORAGE - A three dimensional non-volatile storage system includes a substrate and a plurality of memory cells arranged in a monolithic three dimensional memory array (or other 3D structure) positioned above and not in the substrate. The system includes a plurality of vertical bit lines and a plurality of word lines. Each group of three neighboring word lines on a common level of the three dimensional memory array are electrically isolated from each other and at least a subset of the three neighboring word lines of each group are connected to other word lines. | 01-28-2016 |
20160027478 | STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN - A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks. | 01-28-2016 |
20160027501 | THREE DIMENSIONAL DUAL-PORT BIT CELL AND METHOD OF USING SAME - A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch. | 01-28-2016 |
20160035418 | MEMORY DEVICE ARCHITECTURE - Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array. | 02-04-2016 |
20160035420 | NONVOLATILE MEMORY DEVICE AND METHOD FOR CONTROLLING SAME - According to one embodiment, a device includes: word lines extending in a first direction, widths of the word lines in a second direction intersecting the first direction having a first width and a second width greater than the first width; bit lines provided above or under the word lines, the bit lines extending in the second direction, widths of the bit lines in the first direction having a third width and a forth width greater than the third width; storage elements; and a control circuit applying a potential for at least one of a plurality of non-selected word lines and a plurality of non-selected bit lines other than a selected word line and a selected bit line connected to a selected storage element, among the word lines and the bit lines, the potential applied thereto according to a width thereof. | 02-04-2016 |
20160049176 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a plurality of memory packages which are arranged on a substrate; and a logic chip, which has a rhombus shape including first through fourth corners and first through fourth sides connecting the first through fourth corners, is arranged adjacent to the plurality of memory packages, and includes a plurality of terminals that are electrically connected to the plurality of memory packages, as seen on a plan view of the semiconductor package, wherein the plurality of terminals include system address terminals which are adjacent to the first corner of the logic chip and first and second system data terminals which are respectively arranged on the first and second sides contacting the first corner. Another semiconductor package and a method of fabrication are disclosed. | 02-18-2016 |
20160049178 | METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part; the different parts can be in different, neighboring memory cells. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 02-18-2016 |
20160049188 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW | 02-18-2016 |
20160049190 | MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions. | 02-18-2016 |
20160055908 | NON-VOLATILE MEMORY CELL - The invention concerns a memory cell comprising: first and second resistive elements ( | 02-25-2016 |
20160064041 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate; a memory cell array including a plurality of memory cells stacked on the substrate; an inter-layer insulating layer provided on the memory cell array; and a first control circuit. The first control circuit includes a first transistor and first semiconductor layer, a number of a grain boundary of the first semiconductor layer is not less than a number of a grain boundary of the substrate, and the first control circuit is provided on the inter-layer insulating layer and electrically connected to the memory cells. | 03-03-2016 |
20160064050 | SEMICONDUCTOR DEVICE - A semiconductor device includes a spin array in which a plurality of memory cells are disposed in a matrix configuration, a group of a predetermined number of memory cells is collected in units of spin units, and a plurality of the spin units are disposed with an adjacency; a word line provided in correspondence with rows of the memory cells; a bit line pair provided in correspondence with columns of the memory cells; a multiword decoder configured to multiplex a word address according to an input of a multiplicity specify signal to a word line and simultaneously activate a plurality of word lines; and a bit line driver configured to subject a plurality of memory cells, of the memory cells connected to bit line pairs and arrayed in a column direction, activated by the plurality of the word lines to a write operation or a read operation. | 03-03-2016 |
20160064063 | SEMICONDUCTOR DEVICE - A semiconductor device capable of controlling a memory while preventing the functional deterioration of the memory and reducing the power consumption of the semiconductor device is provided. The semiconductor device includes a first semiconductor chip (logic chip) and a second semiconductor chip (memory chip). The first semiconductor chip includes a plurality of temperature sensors disposed in mutually different places, and a memory controller that controls each of a plurality of memory areas provided in the second semiconductor chip based on output results of a respective one of the plurality of temperature sensors. | 03-03-2016 |
20160064073 | RESISTANCE CHANGE TYPE MEMORY DEVICE - A resistance change type memory device according to an embodiment includes a plurality of memory elements; a first to a fourth bit lines connected to the plurality of memory elements, respectively; a first to a fourth transistors connected at their one ends to the first to the fourth bit lines, respectively; a fifth transistor connected at its one end to the other ends of the first and second transistors; a sixth transistor connected at its one end to the other ends of the third and fourth transistors; and a fifth bit line connected to the other ends of the fifth and sixth transistors. | 03-03-2016 |
20160064075 | MEMORY DEVICE - A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array. | 03-03-2016 |
20160071566 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first pad in a first region between a memory region of a semiconductor chip and a first end portion of the semiconductor chip; a second pad in a second region between the memory region and a second end portion of the semiconductor chip, the second end portion being opposite to the first end portion; an output circuit coupled to the second pad; and a calibration circuit which is coupled to the first pad and regulates an impedance of the output circuit, the calibration circuit including a first circuit in the first region and a second circuit in the second region. | 03-10-2016 |
20160071575 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes data path circuits and control circuits alternately disposed along a first direction. A first metal layer is disposed on the data path circuits and control circuits. Each of data path circuits includes a memory cells disposed in rows along the first direction and columns along a second direction crossing the first direction and a read/write circuit disposed at an end of the columns of memory cells. At least one pair of adjacent columns of memory cells has an electrical separation between the gate polysilicon layer the pair of adjacent memory cell columns—that is, gate conductor layer of the adjacent memory columns are electrically distinct. A word line in the first metal layer is segmented along the first direction into separately addressable portions. | 03-10-2016 |
20160071583 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A plurality of word lines extend in a first direction and are disposed in a second direction and a third direction. A plurality of bit lines extend in the third direction and are disposed in the first direction and the second direction. A global bit line is coupled in common to the plurality of bit lines. A selection elements is disposed between the bit line and the global bit line. A control circuit is able to perform respective operations of reading, writing, and deletion on the storage element. A resistive element is disposed on the global bit line side with respect to the selection element. The resistive element adjusts a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element. | 03-10-2016 |
20160078906 | SEMICONDUCTOR DEVICE - According to one embodiment, electrodes are provided in stacked M (M is an integer of 2 or more) semiconductor chips, a transmission units are provided for the semiconductor chips and, based on a chip identification information on a semiconductor chip in the present stage, transmits the chip identification information on a semiconductor chip in the next stage via the electrodes, or transmit a data for setting the chip identification information, and the direction in which an external signal is sent via the electrodes is opposite to the direction in which the chip identification information is transmitted via the electrodes. | 03-17-2016 |
20160078910 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - According to one embodiment, a driving method of a semiconductor memory device, the semiconductor memory device has a stacked body, in which a first electrode film, a second electrode film, a third electrode film are stacked in this order via insulating films, a first semiconductor pillar extending in a stacking direction of the first electrode film, the second electrode film, and the third electrode film and provided in the stacked body, and a memory film. The driving method comprises applying a first voltage to the third electrode film, the first voltage being lower than a second voltage applied to the first electrode film, in case applying a program voltage to the second electrode film, the program voltage to inject charges from the first semiconductor pillar to a portion of the memory film located between the first semiconductor pillar and the second electrode film. | 03-17-2016 |
20160078922 | SRAM CELLS WITH VERTICAL GATE-ALL-ROUND MOSFETS - A Static Random Access Memory (SRAM) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary. | 03-17-2016 |
20160078924 | MEMORY DEVICE WITH MEMORY CELLS SRAM (STATIC RANDOM ACCESS MEMORIES) AND CONTROLLING THE POLARIZATION OF BOXES OF TRANSISTORS OF THE MEMORY CELLS - A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns. | 03-17-2016 |
20160078932 | SEMICONDUCTOR STORAGE DEVICE - An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. | 03-17-2016 |
20160086923 | Stacked Semiconductor Device Assembly - The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices. In some embodiments, the first pad is associated with a first capacitance, while the second pad is associated with a second capacitance that is smaller than the first capacitance. | 03-24-2016 |
20160093339 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 03-31-2016 |
20160093340 | COMPACT MICROELECTRONIC ASSEMBLY HAVING REDUCED SPACING BETWEEN CONTROLLER AND MEMORY PACKAGES - A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations. | 03-31-2016 |
20160093378 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include a plurality of memory chips stacked upon one another, and electrically coupled to one another through a plurality of first TSVs. The semiconductor memory device may include a plurality of second memory chips stacked separately from the first memory chips, and the plurality of second memory chips electrically coupled to one another through a plurality of second TSVs. The semiconductor memory device may include a plurality of external connection electrodes coupled to both to the first memory chips and the second memory chips. Wherein one of the first and second memory chips may be accessed in response to chip select signals inputted through the external connection electrodes. | 03-31-2016 |
20160099078 | DATA STORAGE DEVICE HAVING REFLOW AWARENESS - A method includes, responsive to a power-up event at a data storage device that includes a memory, reading a flag stored at the data storage device and determining that the flag has a first value indicating that a reflow operation has not previously been detected at the memory. The method also includes, in response to determining that the flag has the first value, performing reflow detection at the memory. The method further includes, in response to the reflow detection indicating that the reflow operation has occurred, setting the flag to a second value. | 04-07-2016 |
20160104516 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device | 04-14-2016 |
20160104524 | INTEGRATED CIRCUIT - An integrated circuit includes a plurality of first memory cells and a plurality of second memory cells. Each cell of the plurality of first memory cells includes a first inverter, a second inverter, a first pass-gate (PG) transistor and a second PG transistor. Each inverter of the first and second inverters includes a P-type single FinFET transistor and an N-type single FinFET transistor. The first PG transistor and the second PG transistor each are an N-type single FinFET transistor. Each cell of the plurality of second memory cells includes a third inverter, a fourth inverter, a third PG transistor and a fourth PG transistor. Each inverter of the third and fourth inverters includes a P-type single FinFET transistor and an N-type transistor. Each transistor of the third and fourth PG transistors include at least two FinFET transistors electrically coupled in a parallel configuration. | 04-14-2016 |
20160104709 | PASSING ACCESS LINE STRUCTURE IN A MEMORY DEVICE - A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins. | 04-14-2016 |
20160118095 | DIE STACK ADDRESS BUS HAVING A PROGRAMMABLE WIDTH - The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information. | 04-28-2016 |
20160118113 | MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINES AND DUAL-GATE BIT LINE SELECT TRANSISTORS - A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis, vertically-oriented bit lines disposed above the global bit lines, word lines disposed above the global bit lines, memory cells coupled between the vertically-oriented bit lines and the word lines, and vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines. Each vertically-oriented bit line select transistor has a width, a first control terminal and a second control terminal. The word lines and the vertically-oriented bit lines have a half-pitch, and the width of the vertically-oriented bit line select transistors is between about two times the half-pitch and about three times the half-pitch. Vertical bit lines disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. | 04-28-2016 |
20160132238 | EXTENDED-HEIGHT DIMM - An extended-height DIMM for use in a memory system having slots designed to receive DIMMs that comply with a JEDEC standard that specifies a maximum height for the DIMM and a maximum number of devices allowed to reside on the DIMM. The DIMM comprises a PCB having an edge connector designed to mate with a memory system slot and a height which is greater than the maximum height specified in the applicable standard, a plurality of memory devices which exceeds the maximum number of devices specified in the applicable standard, and a memory buffer, or a register control device and data buffers, which operates as an interface between a host controller's data and command/address busses and the memory devices. This arrangement enables the extended-height DIMM to provide greater memory capacity than would a DIMM which complies with the maximum height and maximum number of devices limits. | 05-12-2016 |
20160133301 | MULTILAYERED SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit. | 05-12-2016 |
20160133312 | STACK SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SAME - A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where ‘N’ is a natural number greater than 1, and ‘K’ is a natural number ranging from 1 to (N−1). | 05-12-2016 |
20160133836 | HIGH ENDURANCE NON-VOLATILE STORAGE - The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage. | 05-12-2016 |
20160141049 | ANTI-FUSE TYPE ONE-TIME PROGRAMMABLE MEMORY CELL ARRAY AND METHOD OF OPERATING THE SAME - An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor. | 05-19-2016 |
20160141337 | MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES - A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair. | 05-19-2016 |
20160148656 | ADDRESS-REMAPPED MEMORY CHIP, MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME - A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit. | 05-26-2016 |
20160148910 | Semiconductor Device Having Plural Memory Chip - A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions. | 05-26-2016 |
20160155487 | MEMORY DEVICE, MEMORY MODULE INCLUDING THE MEMORY DEVICE, METHOD OF FABRICATING THE MEMORY MODULE, AND METHOD OF REPAIRING THE MEMORY MODULE | 06-02-2016 |
20160163365 | SEMICONDUCTOR DEVICE - A semiconductor device may include a mat array, and a plurality of memory cell mats each including bit lines. The memory cell mats may be included in the mat array. The semiconductor device may include edge sense amplifier blocks comprising edge sense amplifiers coupled to half of the bit lines of the outermost memory cell mats among the memory cell mats. The half of the bit lines of the outermost memory cell mats may be coupled to the edge sense amplifiers, respectively, and may be configured for a first input. The semiconductor device may include half dummy mats each having an area corresponding to half of the area of a memory cell mat of the plurality of memory cell mats and configured to provide reference bit lines for a second input to the edge sense amplifiers, respectively. | 06-09-2016 |
20160163374 | MEMORY DEVICE - In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured. | 06-09-2016 |
20160180891 | SEMICONDUCTOR WAFER AND METHOD OF FABRICATING AN IC DIE | 06-23-2016 |
20160189754 | Three-Dimensional One-Time-Programmable Memory Comprising Off-Die Read/Write-Voltage Generator - The present invention discloses a three-dimensional one-time-programmable memory (3D-OTP) comprising an off-die read/write-voltage generator (V | 06-30-2016 |
20160196861 | MAGNETIC MEMORY AND SEMICONDUCTOR-INTEGRATED-CIRCUIT | 07-07-2016 |
20160379701 | MAGNETORESISTIVE MEMORY DEVICE - According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction. | 12-29-2016 |
20160379709 | STORAGE DEVICE - A storage device has a recording media capable of recording information, a probe array which is arranged opposed to one main surface of the recording media and includes a plurality of probes capable of reading and writing the information from/to the recording media by contacting the probes with or providing the probes adjacent to the one main surface, and an actuator to relatively move the recording media and the probe array along a direction parallel to the one main surface. The probe includes a cantilever which comprises a groove on a surface side opposed to the one main surface and an electrode arranged on at least one side surface connected to the surface opposed to the one main surface of the cantilever. | 12-29-2016 |
20160381800 | METHODS OF FORMING TRENCHES IN PACKAGES STRUCTURES AND STRUCTURES FORMED THEREBY - Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die. | 12-29-2016 |
20170236574 | SEMICONDUCTOR DEVICE | 08-17-2017 |
20170236576 | SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY | 08-17-2017 |
20190147918 | MEMORY DEVICE | 05-16-2019 |
20190147940 | SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY | 05-16-2019 |
20190148637 | WRAPAROUND TOP ELECTRODE LINE FOR CROSSBAR ARRAY RESISTIVE SWITCHING DEVICE | 05-16-2019 |
20220139445 | STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies. | 05-05-2022 |
20220139446 | MULTI-DIE MEMORY DEVICE - A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays. | 05-05-2022 |