Class / Patent application number | Description | Number of patent applications / Date published |
365490170 |
Compare/Search/Match circuit
| 134 |
365490110 |
Flip-Flop
| 10 |
365050000 |
Magnetic cell
| 8 |
365490180 |
Priority encoders | 5 |
20080239779 | System and Method for Detecting Multiple Matches - A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted. | 10-02-2008 |
20090067209 | Low-Power Content-Addressable-Memory Device - A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence. | 03-12-2009 |
20090251939 | PRIORITY ENCODER - A priority encoder encodes an (N+1)-bit thermometer code, where N indicates a natural number. A plurality of selectors are arranged in a matrix of M rows and (N+1) columns, where M indicates a natural number, and select one of signals at first and second input terminals (1,0) in accordance with the value of a signal input to the control terminal. An output signal from the selector in the i-th row and (j−1)th column is input to the first input terminal of the selector in the i-th row and j-th column (1≦i≦M, 2≦j≦N+1), a predetermined value of 1 or 0 is input to the second input terminal of the selector in the i-th row and j-th column, and the j-th significant bit of the thermometer code is input to the control terminal of the selector in the i-th row and j-th column. | 10-08-2009 |
20100321972 | SYSTEMS FOR IMPLEMENTING SDRAM CONTROLLERS, AND BUSES ADAPTED TO INCLUDE ADVANCED HIGH PERFORMANCE BUS FEATURES - An arbitration logic including one or more modular priority encoders. Each modular priority encoder includes a first logic circuit, a comparator circuit, a second logic circuit, and an encoder circuit. The first logic circuit may be configured to generate a first output signal in response to a plurality of request signals. The comparator circuit may be configured to compare all possible pairs of a plurality of priority signals. The second logic circuit may be configured to generate a control signal in response to (i) the plurality of request signals and (ii) a result of comparing all possible pairs of the plurality of priority signals. The encoder circuit may be configured to generate a second output signal in response to the control signal. | 12-23-2010 |
20130265813 | MULTI-PRIORITY ENCODER - A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input. | 10-10-2013 |
365490150 |
Auxiliary lines | 4 |
20130223121 | SENSE SCHEME FOR PHASE CHANGE MATERIAL CONTENT ADDRESSABLE MEMORY - A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold. | 08-29-2013 |
20140153310 | CONTENT ADDRESSABLE MEMORY - A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F | 06-05-2014 |
20140313807 | CONTENT ADDRESSABLE MEMORY DEVICE - A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A. | 10-23-2014 |
20160148655 | Sense Amplifier - A sense amplifier for sensing a line of a semiconductor device comprises a p-channel pull-up transistor for charging the line, an inverter, and a pull-up controller. The p-channel pull-up transistor and the inverter are coupled to the line. The inverter inverts a line voltage of the line. The pull-up controller is coupled to the gate of the p-channel pull-up transistor and operates the p-channel pull-up transistor as a function of the inverted line voltage. | 05-26-2016 |
365490120 |
Capacitor cell | 2 |
20080285322 | Junction field effect dynamic random access memory cell and content addressable memory cell - A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion comprising p-channel junction field effect transistors. The TCAM cell including an x-cell, y-cell, and comparator circuit. The x-cell, y-cell, and comparator circuits comprising p-channel JFETs. | 11-20-2008 |
20110051484 | LOW ACTIVE POWER CONTENT ADDRESSABLE MEMORY - A dynamic, content addressable memory (CAM) cell includes a match line, a write line, a first pair of complementary bit lines for read and search operations, and a second pair of complementary bit lines for write operations; a first storage transistor connected between one of the first pair of complementary bit lines and the match line; a second storage transistor connected between the other of the first pair of complementary bit lines and the match line; a first write transistor connected between a gate of the first storage transistor and one of the second pair of complementary bit lines; and a second write transistor connected between a gate of the second storage transistor and the other of the second pair of complementary bit lines, with both the first and second write transistors having a gate connected to the write line. | 03-03-2011 |
Entries |
Document | Title | Date |
20080232148 | SEMICONDUCTOR MEMORY DEVICE AND REDUNDANCY METHOD THEREOF - A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a content-addressable memory to which the first address is input as a search address, and which performs a search to determine whether or not the first address and a defective address coincide with each other and, when the first address and the defective address coincide with each other, outputs a second address and a control signal, a second memory which, when the second address is input thereto, outputs redundant data corresponding to the second address, and a multiplexer which, when the control signal is input thereto, switches the output data from the first output data to the redundant data, and outputs the redundant data to an input/output terminal. | 09-25-2008 |
20080259667 | Content addressable memory - Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes writing entries, including a type field, to a ternary content addressable memory (TCAM). The method includes marking certain entries as valid. The method includes precharging match lines associated with the entries when an entry is valid and based on a type selection. | 10-23-2008 |
20080273361 | Memory Cell for Content-Addressable Memory - A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation. | 11-06-2008 |
20080316787 | METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE - A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming. | 12-25-2008 |
20090161399 | Super leakage current cut-off device for ternary content addressable memory - A super leakage current cut-off device for a ternary content addressable memory (TCAM) is provided. For various operations of the TCAM, the device uses the high-end and low-end power gating control transistors to turn on/off the don't-care cells to reduce the leakage current passing through the don't-care cells. | 06-25-2009 |
20090161400 | Leakage current cut-off device for ternary content addressable memory - A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode. | 06-25-2009 |
20090168478 | Semiconductor memory device that can relieve defective address - A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder ( | 07-02-2009 |
20090279340 | N-way mode content addressable memory array - A disclosed embodiment is an N-way mode CAM (content addressable memory) array comprising M rows that each contain N subwords. Each of the N subwords has a respective mode cell. Additionally, a mode input bus is coupled to each mode cell of each of the N subwords, and a data input bus is coupled to each of the M rows. The mode input bus and the data input bus can uniquely identify as a match a single subword or a plurality of subwords in one of the M rows during a search operation. The disclosed embodiment further comprises a row address encoder/generator coupled to each of the M rows, and an address output bus coupled to each of the row address encoder/generators. The mode input bus is also coupled to each of the row address encoder/generators. A uniquely identified single subword address may be outputted on the address output bus. | 11-12-2009 |
20090316460 | METHOD AND APPARATUS FOR MEMORY REDUNDANCY IN A MICROPROCESSOR - An apparatus for redundancy of a memory array includes a primary memory array including a plurality of memory cells, one or more of which are defective. A redundant array includes a CAM array that includes a plurality of memory cells. The CAM array is addressed by the address of a defective memory location within the primary memory array and provides a match identification and a resource identification. The redundant array also includes a translation array wherein an offset to configure an input/output multiplexer is stored. The redundant array also includes a redundant data array including a plurality of memory cells wherein one or more memory cells of the redundant data array are used instead of one or more defective memory cells of the primary array. | 12-24-2009 |
20090316461 | Method and Apparatus for Performing Variable Word Width Searches in a Content Addressable Memory - A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR. | 12-24-2009 |
20100085790 | AMPLIFIER CIRCUIT AND ASSOCIATIVE MEMORY - An amplifier circuit according to the present invention includes a plurality of input nodes receiving a plurality of input voltages (VI | 04-08-2010 |
20100097831 | ITERATIVE SERIAL CONTENT ADDRESSABLE MEMORY - A technique is presented for implementing a content addressable memory (CAM) function using traditional memory, where the input data is serially loaded into a serial CAM. Various additions, which allow for predicting the result of a serial CAM access coincident with the completion of serially inputting the data are also presented. | 04-22-2010 |
20100124089 | SINGLE-ENDED SENSE AMPLIFIER CIRCUIT - Single-ended sense amplifier circuit. An example of the sense amplifier circuit includes an inverter coupled to a bit line to read a bit cell. The sense amplifier circuit also includes a first circuit responsive to a control signal to charge the bit line for a predefined time. Further, the sense amplifier circuit includes a second circuit coupled to the bit line and responsive to a read 1 operation to retain voltage of the bit line above a first threshold to render the inverter to read 1 from the bit cell. | 05-20-2010 |
20100142241 | CAM CELL MEMORY DEVICE - A code address memory (CAM) cell memory device comprises a first storage unit comprising a first nonvolatile memory cell configured to output a power source voltage in response to a read voltage, and a second storage unit comprising a second nonvolatile memory cell configured to output a ground voltage in response to the read voltage. | 06-10-2010 |
20100302826 | CAM CELL CIRCUIT OF NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A Code Address Memory (CAM) cell circuit of a nonvolatile memory device includes a CAM cell unit configured to store data, a control circuit unit configured to read data stored in the CAM cell unit and to output data read as read data, and register units each configured to comprise a number of registers for storing the read data. Each of the registers is reset such that first data are latched when a reset operation is performed, and is configured to maintain the first data or newly latch second data in response to the read data. | 12-02-2010 |
20100302827 | CODE ADDRESS MEMORY (CAM) CELL READ CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA OF CAM CELL - A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals, and a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals. The internal ready/busy signal is generated after the externally input reset signal has reset the CAM cell read circuit. | 12-02-2010 |
20100302828 | ADDRESSING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND ADDRESSING METHOD THEREFOR - The addressing circuit of a semiconductor memory device includes a plurality of register units coupled to an input unit and a plurality of memory cell arrays, wherein the plurality of register units are configured to store inputted data in response to register control signals, and a control unit configured to generate the register control signals, using defect information of respective memory cell arrays, to control whether or not the register units store the inputted. | 12-02-2010 |
20100328979 | NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF - In a method of operating a nonvolatile memory device, at least one among memory cell blocks of the nonvolatile memory device is designated as a content addressable memory (CAM) block which includes a plurality of CAM cells coupled to respective word lines of the nonvolatile memory device. Chip information for operations of the nonvolatile memory device is stored in the CAM cells which are coupled to a selected word line, whereas the remaining CAM cells of the CAM block are in an erased state. | 12-30-2010 |
20100328980 | MULTI-CHIP MEMORY DEVICE - A multi-chip memory device includes a number of chips and a control circuit included in each of the chips and configured to generate an internal chip enable signal in response to set data stored therein and an external chip enable signal | 12-30-2010 |
20110013442 | USING STORAGE CELLS TO PERFORM COMPUTATION - An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry. | 01-20-2011 |
20110026287 | METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE - A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming. | 02-03-2011 |
20110051482 | CONTENT ADDRESSABLE MEMORY ARRAY PROGRAMMED TO PERFORM LOGIC OPERATIONS - A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed. | 03-03-2011 |
20110051483 | CONTENT ADDRESSABLE MEMORY ARRAY - A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs. | 03-03-2011 |
20110134676 | RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE - Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element. | 06-09-2011 |
20110149627 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device comprises a voltage detector for generating a detection signal when the external power supply voltage is higher than a set voltage and memory chips, each comprising a memory cell unit and a content-addressable memory (CAM) cell unit and performing internal operations in response to the detection signal. | 06-23-2011 |
20110249480 | NONVOLATILE MEMORY DEVICE - Disclosed is a nonvolatile memory device including a memory cell array including main and redundant memory cells, content addressable memory cells configured to store a defective column address corresponding to a defective memory cell among the main cells, and a repair controller configured to compare the defective column address with an input address to generate a matching control signal and generate a redundancy check-enable signal when the defective column address is inputted as the input address and configured to generate a repair control signal in response to the matching control signal and the redundancy check-enable signal. | 10-13-2011 |
20120008360 | MULTI-CHIP PACKAGE AND METHOD OF OPERATING THE SAME - A multi-chip package includes a plurality of memory chips for performing a content addressable memory (CAM) read operation in response to a command signal for the CAM read operation and an address signal for selecting the memory chips and a controller for outputting the command signal and the address signal to the memory chips and controlling the sequence of the CAM read operations for the memory chips. | 01-12-2012 |
20120057389 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a memory device configured to read control data for operating conditions from a content addressed memory (CAM) block by performing a CAM read operation and to perform a data input/output operation based on the control data and a memory controller configured to store the control data of the memory device and to determine whether the memory device is to perform the CAM read operation by comparing the stored control data with the control data of the memory device when an operating mode of the memory device or the memory controller changes. | 03-08-2012 |
20120106224 | NONVOLATILE MEMORY APPARATUS, REPAIR CIRCUIT FOR THE SAME, AND METHOD FOR READING CODE ADDRESSABLE MEMORY DATA - A nonvolatile memory apparatus includes: a memory cell array including a plurality of planes and configured to store a plurality of code addressable memory (CAM) data in independent planes. A redundancy cell array is configured to replace the memory cell array and a CAM data read unit is configured to read the plurality of CAM data from the respective planes in parallel, in response to a CAM data read command, and store the read data. | 05-03-2012 |
20120120701 | TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES - A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care. | 05-17-2012 |
20120127771 | MULTI-WAFER 3D CAM CELL - A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. | 05-24-2012 |
20120140540 | CHARGE SHARING IN A TCAM ARRAY - A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor. | 06-07-2012 |
20120147642 | System and method for reducing power consumption in a content-addressable memory - According to one disclosed embodiment, a content-addressable memory (CAM) system configured for reduced power consumption includes a sensing circuit utilized to apply a sense voltage to a matchline of the CAM system, a valid bit cell coupled to the matchline, and a power cut-off circuit configured to isolate the sense voltage from the matchline when an invalid validity state is stored in the valid bit cell, thereby reducing power consumption by the CAM system. In one embodiment, the power cut-off circuit isolates the sense voltage from the matchline by decoupling the sensing circuit from a control signal when an invalid validity state is stored in the valid bit cell. | 06-14-2012 |
20120163059 | CONDITIONALLY PRECHARGED DYNAMIC CONTENT ADDRESSABLE MEMORY - A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid. | 06-28-2012 |
20120243283 | USING STORAGE CELLS TO PERFORM COMPUTATION - A method includes activating at least two rows of pure memory cells and reading at least one column of activated the memory cells, the reading generating a binary function of data stored in the activated memory cells. | 09-27-2012 |
20120268977 | SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A semiconductor memory device includes a memory cell block configured to include a plurality of main cells and a plurality of CAM cells, a plurality of page buffers configured to store data to be programmed into the memory cell block, and a Y decoder configured to transfer CAM data to respective page buffers, selected from among the plurality of page buffers, in response to a data determination signal and CAM column addresses whenever the CAM data is inputted in a CAM data input mode. | 10-25-2012 |
20130033915 | CONTENT ADDRESSABLE MEMORIES WITH WIRELINE COMPENSATION - What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of the group of wires is divided into at least one subgroup (N). Next, a capacitance (C | 02-07-2013 |
20130077373 | NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF - In a method of operating a nonvolatile memory device, at least one among memory cell blocks of the nonvolatile memory device is designated as a content addressable memory (CAM) block which includes a plurality of CAM cells coupled to respective word lines of the nonvolatile memory device. Chip information for operations of the nonvolatile memory device is stored in the CAM cells which are coupled to a selected word line, whereas the remaining CAM cells of the CAM block are in an erased state. | 03-28-2013 |
20130155749 | CONTENT ADDRESSABLE MEMORY - A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. | 06-20-2013 |
20130188409 | PROBABILISTICALLY-BANKED CONTENT ADDRESSABLE MEMORY AND STORAGE - An energy-efficient CAM architecture provides increased speed of searching, reduced power consumption, or a tuned combination of increased speed of searching and reduced power consumption. The CAM comprises a plurality of CAM banks, a plurality of Bloom filters, each Bloom filter associated with a content addressable memory bank, each Bloom filter recording elements inserted into an associated content addressable memory bank, wherein the size of each Bloom filter is configured to reduce energy or power consumption of the content addressable memory apparatus. The size of each Bloom filter may be configured to reduce energy or power consumption of the content addressable memory apparatus. | 07-25-2013 |
20140050002 | TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) STORAGE SYSTEM - A system for ternary content addressable memory (TCAM) storage may include a TCAM having multiple entries and a processor that is communicatively coupled to the TCAM. The processor may be operative to receive a first numerical range and determine a first ternary representation of a second numerical range that encompasses the first numerical range. The processor may be further operative to determine a second ternary representation corresponding to at least one of a lower bound or an upper bound of the first numerical range. The processor may be further operative to store a combination of the first and second ternary representations in one of the entries of the TCAM. In one or more implementations, the numerical range may be a port range and the combination of the ternary representations may be stored in one of the entries of the TCAM as a portion of a packet classification rule. | 02-20-2014 |
20140198551 | Content Addressable Memory Device Having Electrically Floating Body Transistor - A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data. | 07-17-2014 |
20150109840 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device employs a technology for improving data retention characteristics of a cell array storing data regarding conditions for controlling internal operations of the semiconductor device. The semiconductor device includes a content addressable memory (CAM) cell array configured to store CAM data regarding conditions for controlling the internal operations, a control logic configured to store the CAM data read out of the CAM cell array, and a microprocessor configured to perform a reprogramming operation on the CAM cell array using the CAM data stored in the control logic. | 04-23-2015 |
20150109841 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device comprises a memory block having a content addressable memory (CAM) cell array storing data for internal operation conditions, and a memory cell array. The semiconductor device also comprises a page buffer to program data in the memory block or read the data programmed in the memory block; a control logic to activate a reset enable signal for initializing the page buffer during a reset operation and output the activated reset enable signal; and a power-supply controller to output a reset control signal for initializing the page buffer when the reset enable signal is activated, and provide a page buffer power-supply signal to the page buffer. The power-supply controller provides the page buffer power-supply signal after initialization of the page buffer. | 04-23-2015 |
20150348594 | MEMORY BANKS WITH SHARED INPUT/OUTPUT CIRCUITRY - A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks. | 12-03-2015 |
20160064081 | SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE DEVICE INCLUDING THE SAME - A semiconductor memory device includes a setting information area suitable for storing setting information necessary for driving of memory cells, a control logic suitable for loading the setting information stored in the setting information area on a content-addressable memory (CAM) block, a CAM state information storage block suitable for storing information on whether the setting information loaded on the CAM block is changed, wherein when a reloading operation of the setting information stored in the setting information area on the CAM block is requested, the control logic selectively performs the reloading operation based on the information stored in the CAM state information storage block. | 03-03-2016 |
20160169944 | ELECTRONIC APPARATUS | 06-16-2016 |