| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365045000 | ANALOG STORAGE SYSTEMS | 23 |
| 20080298109 | Fast Analog Sampler For Continuous Recording and Read-Out and Digital Conversion System - An analog sampler ( | 12-04-2008 |
| 20100073981 | SWITCHED CURRENT MEMORY CELL - A switched current memory cell includes: a current source | 03-25-2010 |
| 20100091535 | ADAPTIVE ESTIMATION OF MEMORY CELL READ THRESHOLDS - A method for operating a memory ( | 04-15-2010 |
| 20100124088 | STORAGE AT M BITS/CELL DENSITY IN N BITS/CELL ANALOG MEMORY CELL DEVICES, M>N - A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set. | 05-20-2010 |
| 20100157641 | MEMORY DEVICE WITH ADAPTIVE CAPACITY - A method for data storage in a memory ( | 06-24-2010 |
| 20100165689 | REJUVENATION OF ANALOG MEMORY CELLS - A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the memory cells in the group to meet the given storage quality level, is applied to the identified group. Data is stored in the rejuvenated group of the memory cells. | 07-01-2010 |
| 20100220509 | Selective Activation of Programming Schemes in Analog Memory Cell Arrays - A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme. | 09-02-2010 |
| 20100309703 | COMPACT AND ACCURATE ANALOG MEMORY FOR CMOS IMAGING PIXEL DETECTORS - The present invention relates to an analog memory circuit, i.e. a sample and hold circuit, wherein the source and the gate of the switching transistor is maintained at a same potential prior and after the sampling process using a transistor circuitry. The analog memory circuit comprises a memory capacitor ( | 12-09-2010 |
| 20120224404 | ENHANCED PROGRAMMING AND ERASURE SCHEMES FOR ANALOG MEMORY CELLS - A method for data storage includes setting a group of analog memory cells to respective analog values by performing an iterative process that applies a sequence of pulses to the memory cells in the group. During the iterative process, a progress of the iterative process is assessed, and a parameter of the iterative process is modified responsively to the assessed progress. The iterative process is continued in accordance with the modified parameter. | 09-06-2012 |
| 20120262970 | SELECTIVE ACTIVATION OF PROGRAMMING SCHEMES IN ANALOG MEMORY CELL ARRAYS - A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme. | 10-18-2012 |
| 20120262971 | Selective Activation of Programming Schemes in Analog Memory Cell Arrays - A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme. | 10-18-2012 |
| 20120287692 | READ THRESHOLD SETTING BASED ON TEMPERATURE INTEGRAL - A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the memory cells in the group to meet the given storage quality level, is applied to the identified group. Data is stored in the rejuvenated group of the memory cells. | 11-15-2012 |
| 20130063997 | High-Resolution Readout of Analog Memory Cells - A method includes storing data in an analog memory cell by writing an analog value into the memory cell. After storing the data, the data stored in the memory cell is read by discharging electrical current to flow through the memory cell, during a predefined time interval, while applying a variable voltage to a gate of the memory cell. A fraction of the predefined time interval, during which the variable voltage allows the electrical current to flow through the memory cell, is estimated. The stored data is estimated based on the estimated fraction. | 03-14-2013 |
| 20130170272 | OPTIMIZED THRESHOLD SEARCH IN ANALOG MEMORY CELLS - A method includes storing data in a group of analog memory cells. The memory cells in the group are read using first read thresholds to produce first readout results, and re-read using second read thresholds to produce second readout results. Third read thresholds, which include at least one of the first read thresholds and at least one of the second read thresholds, are defined. Readout performance of the first, second and third read thresholds is evaluated based on the first and second readout results. The first, second or third read thresholds are selected based on the evaluated readout performance, and data recovery is performed using the selected read thresholds. | 07-04-2013 |
| 20130235638 | HIGH SPEED INTERFACE FOR MULTI-LEVEL MEMORY - A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller. | 09-12-2013 |
| 20130258738 | OPTIMIZED THRESHOLD SEARCH IN ANALOG MEMORY CELLS USING SEPARATOR PAGES OF THE SAME TYPE AS READ PAGES - A method includes reading a group of analog memory cells using first explicit read thresholds, to produce first readout results. The group is re-read using second explicit read thresholds, to produce second readout results. The group is read using one or more sets of auxiliary thresholds so as to produce auxiliary readout results, such that the number of the auxiliary thresholds in each set is the same as the number of the first explicit read thresholds and the same as the number of the second explicit read thresholds. A readout performance of third read thresholds, which include at least one of the first explicit read thresholds and at least one of the second explicit read thresholds, is evaluated using the first, second and auxiliary readout results. | 10-03-2013 |
| 20140092664 | Associative Memory Oscillator Array - An embodiment of the invention includes an analog associative memory, which includes an array of coupled voltage or current controlled oscillators, that matches patterns based on shifting frequencies away from a center frequency of the oscillators. The test and memorized patterns are programmed into the oscillators by varying the voltage or current that controls the oscillators. Matching patterns result in smaller shifts of frequencies and enable synchronization of oscillators. Non-matching patterns result in larger shifts and preclude synchronization of oscillators. In one embodiment the patterns each include binary data and the pattern matching is based on discrete shifts. In one embodiment the patterns each include grayscale data and the pattern matching is based on continuously-varied shifts. Other embodiments are described herein. | 04-03-2014 |
| 20140119089 | DATA STORAGE IN ANALOG MEMORY CELLS USING A NON-INTEGER NUMBER OF BITS PER CELL - A method for data storage includes, in a first programming phase, storing first data in a group of analog memory cells by programming the memory cells in the group to a set of initial programming levels. In a second programming phase that is subsequent to the first programming phase, second data is stored in the group by: identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels; and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels. | 05-01-2014 |
| 20140340951 | APPLICATIONS FOR INTER-WORD-LINE PROGRAMMING - A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration. | 11-20-2014 |
| 20150055388 | SELECTIVE ACTIVATION OF PROGRAMMING SCHEMES IN ANALOG MEMORY CELL ARRAYS - A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme. | 02-26-2015 |
| 20150302906 | DATA STORAGE USING ANALOG CODING - In an embodiment, a memory system is provided. The memory system can include one or more memory elements, a quantity associated with each of the one or more memory elements can take a value in a continuous range of values; an encoder configured to determine a value for a quantity of a first memory element of the one or more memory elements based on data to be stored; and a memory controller configured to control the first memory element such that the quantity of the first memory element is set to the determined value. | 10-22-2015 |
| 365046000 | Resistive | 2 |
| 20110069521 | ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES - An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location to store a desired content. The selected memory location is subject to data dependent noise and is capable of storing a range of values grouped into “n” bins configured such that the average cost to write to at least “n-1” of the bins is within a threshold of a target cost for the selected analog memory location. The system also includes a read apparatus. The system further includes write control circuitry that includes a write signal selector selecting the one or more write control signals responsive to the desired content, current content of the selected memory location, and a bin associated with the desired content. | 03-24-2011 |
| 20150009736 | APPROXIMATE MULTI-LEVEL CELL MEMORY OPERATIONS - The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency. | 01-08-2015 |
