Entries |
Document | Title | Date |
20080198664 | NON-VOLATILE STORAGE APPARATUS WITH MULTIPLE PASS WRITE SEQUENCE - A set of non-volatile storage elements are erased to an erased threshold voltage distribution. A multi-pass programming process is performed that programs the set of non-volatile storage elements from the erased threshold voltage distribution to a set valid data threshold voltage distributions. Each programming pass has one or more starting threshold voltage distributions and programs non-volatile storage elements to at least two ending threshold voltage distributions. | 08-21-2008 |
20080198665 | VARIABLE INITIAL PROGRAM VOLTAGE MAGNITUDE FOR NON-VOLATILE STORAGE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional programming passes include the programming of data. In another embodiment, all of the programming process include programming data. For at least a subset of said programming processes, a program pulse associated with achieving a particular result for a respective programming process is identified. The identified program pulse is used to adjust programming for a subsequent programming process. | 08-21-2008 |
20080198666 | Semiconductor device including adjustable driver output impedances - A semiconductor device is disclosed. In one embodiment, the device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to drive output signals and includes an adjustable output impedance. The second circuit is configured to adjust the adjustable output impedance. The third circuit is configured to sense a first parameter and to activate the second circuit to adjust the adjustable output impedance based on changes in the first parameter exceeding a first threshold value. | 08-21-2008 |
20080219058 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 09-11-2008 |
20080225599 | FLASH MEMORY DEVICE WITH REDUCED COUPLING EFFECT AMONG CELLS AND METHOD OF DRIVING THE SAME - Embodiments of the invention provide a flash memory device that can improve the reliability of a reading operation by minimizing a variation in the threshold voltage distribution that occurs due to coupling between cells, and a method of driving the flash memory device. In an embodiment of the invention, the method of driving the flash memory includes: performing an erasing operation on memory cells; after the performing the erasing operation, performing a post-programming operation to control a threshold voltage of the memory cells; and after performing the post-programming operation, performing a main programming operation on the memory cells, wherein the performing of the post-programming operation comprises increasing the threshold voltage of the memory cells in an erased state, thereby reducing a difference in the threshold voltage between the memory cells in the erased state and the memory cells in the programmed state. | 09-18-2008 |
20080253197 | Predictive Programming in Non-Volatile Memory - In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. The checkpoint is an actual programming voltage that programs the memory cell in question to a verified designated threshold voltage level. | 10-16-2008 |
20080266977 | METHOD FOR HIGH SPEED PROGRAMMING OF A CHARGE TRAPPING MEMORY WITH AN ENHANCED CHARGE TRAPPING SITE - A method of high speed programming and erasing of a charge trapping memory using turn-on-mode assist-charge (TOM-AC) operations. The charge trapping memory includes a charge trapping structure overlying a substrate body with source and drain regions. The charge trapping structure includes a charge trapping layer overlying a dielectric layer. The charge trapping layer has an assist charge site (also referred to as AC-site, AC-side, or a first charge trapping site) and a data site (also referred to as data-side or a second charge trapping site). Initially, to place the charge trapping memory cell in a TOM operation, both the AC-site and the data site of the charge trapping memory cell are erased to a negative threshold voltage level, −Vt, by FN injection, thereby inducing a hole charge induced channel between the source and drain regions. | 10-30-2008 |
20090086546 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING DATA INTO THE SAME - In a nonvolatile semiconductor memory device, a memory cell array has a plurality of nonvolatile memory cells arranged in a matrix. A selecting section selects as selection memory cells, at least two of the plurality of nonvolatile memory cells from the memory cell array. A write section applies to the selection memory cells, a gate voltage which increases step by step, until a threshold voltage of each of the selection memory cells reaches a target threshold voltage, such that the threshold voltage increases step-by-step. | 04-02-2009 |
20090103370 | EFFICIENT ERASE ALGORITHM FOR SONOS-TYPE NAND FLASH - A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of voltages from the gate to the substrate of the memory cell to further reduce the threshold voltage of the memory cell, wherein a subsequent voltage in the sequence of voltages has a lower magnitude from the gate to the substrate than that of a preceding voltage in the sequence of voltages. | 04-23-2009 |
20090109761 | Method of operating nonvolatile memory device - Provided is a method of operating a three-dimensional nonvolatile memory device which may increase the reliability and efficiency of the three-dimensional nonvolatile memory device. The method of operating a nonvolatile memory device may include: resetting the nonvolatile memory device by injecting charges into charge storage layers of a plurality of memory cells of a block; and setting the nonvolatile memory device by removing at least some of the charges injected into the charge storage layers of one or more memory cells selected from among the plurality of memory cells. | 04-30-2009 |
20090122617 | SOFT PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a first cell group including memory cells other than memory cells adjacent to a drain select transistor in a block, and a second cell group including the memory cells adjacent to the drain select transistor in the block. An erase operation is performed on the memory cells in the block. The first cell group is programmed by applying a first soft programming voltage to the first cell group. The second cell group is programmed by applying a second soft programming voltage to the second cell group. | 05-14-2009 |
20090180330 | NON-VOLATILE MEMORY DEVICE AND METHODS OF USING - The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed. | 07-16-2009 |
20090190408 | Method of Operating an Integrated Circuit, Integrated Circuit and Method to Determine an Operating Point - Embodiments of the present invention relate to a method to operate an integrated circuit that includes a memory. The memory encompasses a first and a second threshold level. The invention further relates to integrated circuits including a memory with a first and a second threshold level and a method to determine an operating point of an integrated circuit. | 07-30-2009 |
20090201742 | Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device - A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (approximately 90% between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated. | 08-13-2009 |
20090219763 | NON-VOLATILE MEMORY - A non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each cell including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in the portion of the substrate. A circuit provides a first voltage to the substrate and a second voltage to both S/D regions of each cell, wherein the difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes. The circuit also provides a voltage to the control gate and the period of applying the voltages are controlled such that the threshold voltages of all the cells converge in a tolerable range. | 09-03-2009 |
20100020619 | MEMORY CONTROLLER, MEMORY SYSTEM, RECORDING AND REPRODUCING METHOD FOR MEMORY SYSTEM, AND RECORDING APPARATUS - A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation. | 01-28-2010 |
20100020620 | Memory device and method of programming thereof - Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells. | 01-28-2010 |
20100027351 | Memory device and memory programming method - A memory device and a memory programming method are provided. The memory device may program data in a multi-level cell (MLC) or a multi-bit cell (MBC) memory device. The memory device may include a memory cell array, a programming unit and a program level stabilization unit. The memory cell array may include a plurality of multi-level cells. The programming unit may be configured to program a first data page in the plurality of multi-level cells and to program a second data page in the plurality of multi-level cells having the programmed first data page. The program level stabilization unit may be configured to stabilize a program level of at least one of the first data page and the second data page. | 02-04-2010 |
20100067309 | EFFICIENT ERASE ALGORITHM FOR SONOS-TYPE NAND FLASH - A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of voltages from the gate to the substrate of the memory cell to further reduce the threshold voltage of the memory cell, wherein a subsequent voltage in the sequence of voltages has a lower magnitude from the gate to the substrate than that of a preceding voltage in the sequence of voltages. | 03-18-2010 |
20100091574 | ONE-TRANSISTOR COMPOSITE-GATE MEMORY - One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies. | 04-15-2010 |
20100110798 | PROGRAM WINDOW ADJUST FOR MEMORY CELL SIGNAL LINE DELAY - A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed. | 05-06-2010 |
20100142285 | REDUCING READ FAILURE IN A MEMORY DEVICE - Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines. | 06-10-2010 |
20100182845 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR COPY-BACK THEREOF - A method for performing a copy-back operation in a non-volatile memory device includes: measuring and recording a maximum program voltage used to program a part of target data to copy-back when a copy-back command is inputted; and performing a copy-back operation using the recorded maximum program voltage. | 07-22-2010 |
20100214852 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 08-26-2010 |
20100220531 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 09-02-2010 |
20100238737 | BIT LINE SELECT VOLTAGE GENERATOR AND NONVOLATILE MEMORY DEVICE USING THE SAME - A bit line select voltage generator includes a first and second voltage generators and a voltage transmission unit. The first voltage generator operates to divide a reference voltage of a reference voltage generator to generate a first voltage and a second voltage, wherein the second voltage is lower than the first voltage. The second voltage generator operates to change the first voltage according to change of temperatures thereby generating a third voltage. The voltage transmission unit operates to transmit the second voltage or the third voltage to an output terminal according to a voltage level of a first voltage transmit control signal or a second voltage transmit control signal. | 09-23-2010 |
20100254195 | Memory device and method for estimating characteristics of multi-bit programming - Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell. | 10-07-2010 |
20100290293 | METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME - A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme. | 11-18-2010 |
20100309728 | MEMORY READ METHODS, APPARATUS, AND SYSTEMS - Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number of states. The states represent values of information stored in the memory cells. During a read operation to read the first memory cells, a first voltage may be applied to the first line and a second voltage may be applied to the second line. At least one of the first and second voltages may include a value based on a change of at least one of the threshold voltage values changing from a first value to a second value. The first and second values may correspond to a unique state selected from all of the states. Other embodiments including additional apparatus, systems, and methods are disclosed. | 12-09-2010 |
20100322012 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD FOR THE SAME - According to one embodiment, a semiconductor device includes memory cells, bit lines, a write circuit, and sense amplifiers. The bit lines are connected to the memory cells. The sense amplifiers are configured to bias the bit line to which the selected memory cell is connected, to a first voltage until the threshold of the selected memory cell reaches the value of a first write state. Then, when the threshold of the selected memory cell reaches the value of the first write state, the bit line is biased to a second voltage higher than the first voltage. When the threshold of the selected memory cell reaches the value of a second write state, the bit line is continuously biased to a third voltage higher than the second voltage. Bit lines connected to unselected memory cells corresponding to the memory cells other than the selected one are biased to the third voltage. | 12-23-2010 |
20100329033 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In general, according to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array including memory cells; and a control unit to control a signal applied to the memory cells. Each of the memory cells are settable to: first, second and third states having first, second and third threshold voltage distributions (VD | 12-30-2010 |
20110007573 | GAIN CONTROL FOR READ OPERATIONS IN FLASH MEMORY - A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read threshold voltage levels. In one approach, M-quantized threshold voltage values are multiplied by a gain to obtain gain-adjusted threshold voltage values, which are quantized by an L-level quantizer, where L01-13-2011 | |
20110013462 | Method for Operating Memory - A memory operating method includes the following steps. First, a memory with a charge storage structure is provided. Next, the memory is biased to a first threshold voltage. Then, the memory is biased to a second threshold voltage. Next, the memory is biased to a third threshold voltage. The first threshold voltage is higher than a first level. The second threshold voltage is lower than a second level. The third threshold voltage is approximating or equal to the second level. | 01-20-2011 |
20110085386 | METHODS OF PROGRAMMING AND READING SINGLE-LEVEL TRAPPED-CHARGE MEMORY CELLS USING SECOND-BIT THRESHOLD DETECTION - Methods are disclosed to compensate for a second-bit effect during programming and reading of charge-trapping memory cells having left and right data regions. When only one of the left and right data regions is to be programmed, a two-step programming procedure is performed on the data region to be programmed. When the memory cell is to be read, threshold voltages for the left and right data regions are sensed with a joint decision regarding left and right data bit values being reached depending upon both sensed threshold voltage values. | 04-14-2011 |
20110299341 | METHOD OF PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE - A method of programming a semiconductor memory device includes the steps of grouping memory cells in accordance with levels of threshold voltages to be programmed, programming the memory cell groups by sequentially applying program voltages to the memory cell groups, and program-verifying the memory cell groups. | 12-08-2011 |
20110317491 | MEMORY READ METHODS, APPARATUS, AND SYSTEMS - Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number of states. The states represent values of information stored in the memory cells. During a read operation to read the first memory cells, a first voltage may be applied to the first line and a second voltage may be applied to the second line. At least one of the first and second voltages may include a value based on a change of at least one of the threshold voltage values changing from a first value to a second value. The first and second values may correspond to a unique state selected from all of the states. Other embodiments including additional apparatus, systems, and methods are disclosed. | 12-29-2011 |
20120008413 | METHOD FOR OPERATING SEMICONDUCTOR MEMORY DEVICE - A method for operating a semiconductor memory device includes the steps of: erasing memory cells of a memory block to set the memory cells in a first erased state, programming a part of the memory cells of the memory block to convert them into a programmed state, raising threshold voltages of selected memory cells of the memory block and converting the selected memory cells from the programmed state to a second erased state, and reading data from the memory cells in the first erased state, the programmed state, and the second erased state, and outputting the data read from the memory cells in the first and second erased states with the same value. | 01-12-2012 |
20120008414 | SYSTEMS AND METHODS FOR STORING, RETRIEVING, AND ADJUSTING READ THRESHOLDS IN FLASH MEMORY STORAGE SYSTEM - A method, system and computer-readable medium are provided for reading information from a memory unit. A read instruction may be received to read information from a set of memory cells in the memory unit. A data structure storing sets of read thresholds may be searched for a set of read thresholds based on one or more characteristic value(s) of the set of memory cells. If the set of read thresholds is found, the set of memory cells may be read to execute the read instruction using the found set of read thresholds. The set of read thresholds may be thresholds which were previously used to successfully read a set of cells having the same or similar characteristic value(s). | 01-12-2012 |
20120063236 | Method and Apparatus for Reducing Read Disturb in Memory - Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution. | 03-15-2012 |
20120063237 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a memory block including a plurality of memory cells grouped by word lines, an operation circuit group configured to perform a program operation or a read operation for the memory cells, and a control circuit configured to control the operation circuit group to set each of threshold voltages of a group of the memory cells, coupled to a word line selected from the word lines, to one of an erase level and five program levels in response to input data. | 03-15-2012 |
20120069681 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a cell array, a controller, and a voltage generator. The cell array includes cells. Each of the cells holds data “0” or “1”. The controller counts the number of times N of sequentially writing the data into the cells. The controller transfers a write voltage and a read voltage. The write voltage and the read voltage are variable according to the number of times N. The voltage generator generates the write voltage and the read voltage. When the N-th (≧2) write request is issued to the cell, the controller causes the voltage generator to generate the read voltage corresponding to an (N−1)th time. The controller causes the voltage generator to generate the write voltage which changes a threshold voltage of the cell. When the cell has reached a prescribed value, the controller erases the data held in the cell. | 03-22-2012 |
20120170378 | READ METHODS OF SEMICONDUCTOR MEMORY DEVICE - A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation on first cells next to the target cells along a first direction if, as a result of the read operation on the target cells, error correction is unfeasible, performing the read operation again on the target cells by selecting one of a plurality of read voltages in response to a result of the read operation on the first cells and by using the selected read voltage for reading data of the target cells, and terminating the read operation on the target cells if error correction is feasible. | 07-05-2012 |
20120195128 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure, a semiconductor pillar, a storage layer, an inner insulating film, an outer insulating film, a memory cell transistor. The control unit performs control of setting the thresholds of the memory transistor to either positive or negative, and performs control so that, with one of the thresholds most distant from 0 volts being defined as n-th threshold, width of distribution of m-th threshold (m being an integer of 1 or more smaller than n) having a sign being same as the n-th threshold is set narrower than width of distribution of the n-th threshold. | 08-02-2012 |
20120275235 | METHOD AND APPARATUS FOR TEMPERATURE COMPENSATION FOR PROGRAMMING AND ERASE DISTRIBUTIONS IN A FLASH MEMORY - A method and apparatus for a memory device is provided. The memory device includes a memory cell, a memory controller, and a temperature-sensing device that detects a temperature. The memory controller enables adjusting, based on the detected temperature, a parameter associated with a bit-altering operation to the memory cell that changes a threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is compensated for variations in temperature. | 11-01-2012 |
20120281483 | SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE - Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog. | 11-08-2012 |
20130010542 | PROGRAMMING METHODS AND MEMORIES - Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell. | 01-10-2013 |
20130033939 | FUNCTIONAL DATA PROGRAMMING AND READING IN A MEMORY - Methods for functional programming memory cells and apparatuses are disclosed. One such method for functional programming includes encoding a group of data with a function to generate representative data and programming the representative data to the memory. In one embodiment, the representative data is a pattern of threshold voltages to be programmed to a group of memory cells. | 02-07-2013 |
20130083608 | 1T SMART WRITE - The threshold voltages of particular nonvolatile memory cells on a word line are selectively increased on a column by column (cell by cell) basis. A selective program is performed on some of the cells, and simultaneously a program inhibit on other of the cells, resulting in all of the cells having a threshold voltage that falls between a minimum acceptable value and a maximum acceptable value. | 04-04-2013 |
20130121084 | METHOD AND APPARATUS TO PROVIDE DATA INCLUDING HARD BIT DATA AND SOFT BIT DATA TO A RANK MODULATION DECODER - A method includes providing data including hard bit data and soft bit data to a rank modulation decoder. | 05-16-2013 |
20130128674 | METHOD OF OPERATING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING RELATED APPLICATION DATA - A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 05-23-2013 |
20130148436 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTIVALUED DATA - According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory includes a plurality of memory cells each of which stores data when one of an n number of threshold voltages (n being a natural number not less than two) is set. The controller reads data from the memory. The controller reads data from the memory cells at each of the threshold voltages in a read operation that checks a distribution of threshold voltages of the memory cells, calculates difference data on data read at each of the threshold voltages, calculates a minimum value of the distribution of the threshold voltages from the difference data, calculates a range of threshold voltages lower than the minimum value based on the minimum value, and sets a central voltage in the calculated range of threshold voltages as a read voltage. | 06-13-2013 |
20130155776 | INTER-CELL INTERFERENCE CANCELLATION - A method includes selecting a first memory cell located along a first bit line and a first word line of a memory array. The method further includes selecting a second memory cell located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. A location of the second memory cell is selected based on a predetermined sequence of programming the memory cells. The method further includes writing data in the first memory cell, subsequently writing data in the second memory cell, and reading the first memory cell and the second memory cell. The method further includes detecting one or more states of the second memory causing interference to the first memory cell. | 06-20-2013 |
20130163346 | METHODS AND APPARATUSES FOR DETERMINING THRESHOLD VOLTAGE SHIFT - Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells include determining changes in threshold voltage for memory cells at each data state of a first number of data states by searching threshold voltage data of memory cells programmed to the first number of data states and determining changes in threshold voltage for memory cells at each data state of a second number of data states by searching threshold voltage data of memory cells programmed to the second number of data states within a range of threshold voltages, wherein the range is shifted from a previous range based on the changes in threshold voltage for memory cells programmed to the first number of data states. | 06-27-2013 |
20130176792 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device and a method of programming the same. The nonvolatile memory device includes a memory cell array including a plurality of memory cells and a program control logic circuit controlling the memory cell array. The program control logic circuit programs a first memory cell so that the threshold voltage of the first memory cell corresponding to data of erasure state is higher than the threshold voltage of a second memory cell corresponding to data of program state, in the memory cell array. The nonvolatile memory device controlled in this manner can provide higher reliability. | 07-11-2013 |
20130182510 | MEMORY DEVICES AND PROGRAMMING METHODS - Memory devices and programming methods are disclosed. In an embodiment of one such method, a memory cell is programmed to at least a first threshold voltage. After programming the memory cell to at least the first threshold voltage, the memory cell is read, using a read voltage that is less than the first threshold voltage. After reading the memory cell, the memory cell is programmed to at least a second threshold voltage that is greater than the first threshold voltage. | 07-18-2013 |
20130272071 | DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS - The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells. | 10-17-2013 |
20130279265 | Method and Apparatus for Reducing Erase Time of Memory By Using Partial Pre-Programming - Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells. | 10-24-2013 |
20130279266 | COMPLEMENTARY ELECTRICAL ERASABLE PROGRAMMABLE READ ONLY MEMORY - Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is disclosed. CEEPROM cell comprises a pair of non-volatile memory elements and one access transistor. The two elements of the non-volatile memory pair are configured to be one with high electrical conductance and the other with low electrical conductance. The positive voltage V | 10-24-2013 |
20130308391 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE AND NON-VOLATILE MEMORY DEVICE USING THE SAME - A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected level of the program voltage. | 11-21-2013 |
20130336072 | ADAPTIVE VOLTAGE RANGE MANAGEMENT IN NON-VOLATILE MEMORY - A method for adaptive voltage range management in non-volatile memory is described. The method includes establishing an adaptive voltage range for a memory element of an electronic memory device. The memory element includes at least two states. The adaptive voltage range comprises a lower state and an upper state. The method also includes establishing an adjustment process to implement a first adjustment of an abode characteristic of a first state and to implement a second adjustment of an abode characteristic of a second state in the adaptive voltage range in response to a trigger event, wherein the first adjustment of an abode characteristic of the first state is different from the second adjustment of an abode characteristic of the second state. | 12-19-2013 |
20130343131 | FAST TRACKING FOR FLASH CHANNELS - An SSD controller dynamically adjusts read thresholds in an NVM to reduce errors due to device threshold voltage distribution shifts, thus improving performance, reliability, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller periodically performs offline tracking on a portion of the NVM. The controller reads a representative sub-portion with current read thresholds. If the read meets a condition, then the controller reads the sub-portion with sample read thresholds, estimates the device threshold voltage distributions, and adjusts the current read thresholds of the portion to calculated new operating read thresholds of the sub-portion. In a second aspect, the portion includes data with a known statistical average number of zero and/or one bits. | 12-26-2013 |
20140063975 | INFERRING THRESHOLD VOLTAGE DISTRIBUTIONS ASSOCIATED WITH MEMORY CELLS VIA INTERPOLATION - The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values. | 03-06-2014 |
20140063976 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 03-06-2014 |
20140098616 | METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY - Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution. | 04-10-2014 |
20140104958 | PROGRAMMING METHODS AND MEMORIES - Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell. | 04-17-2014 |
20140126298 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device may include increasing threshold voltage of memory cells by performing an LSB program operation on the memory cells having first state, decreasing threshold voltage of memory cells to be programmed to second state of the memory cells to a level lower than a first level in unit of a memory cell for an MSB program operation, and increasing threshold voltage of memory cells to be programmed to third state of the memory cells to a level higher than a second level, which is higher than the first level, in unit of a memory cell for an MSB program operation. | 05-08-2014 |
20140146617 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines. Those current path switching circuits which are connected to the selected bit lines supply a current from the power supply line to the memory cells or a predetermined terminal depending on a measured value of the amount of charge measured by the charge amount measurement section. | 05-29-2014 |
20140169102 | LOG-LIKELIHOOD RATIO AND LUMPED LOG-LIKELIHOOD RATIO GENERATION FOR DATA STORAGE SYSTEMS - An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) for upper and lower pages of memory cells in MLC solid-state media. Disclosed are systems and methods for generating lumped-LLR for upper pages, wherein at least some voltage threshold reads are linked together in order to reduce the number of reads. Efficiency and reliability are thereby improved. | 06-19-2014 |
20140211569 | ADJUSTING OPERATIONAL PARAMETERS FOR MEMORY CELLS - Techniques and devices relating to adjusting one or more operational parameters for memory cells are provided. One such device may include a detection unit configured to perform one or more reading operations on a set of memory cells to determine an upper bound of the threshold voltages of the set of memory cells. The device may further include a parameter adjustment unit configured to adjust one or more operational parameters for the set of memory cells based, at least in part, on the determined upper bound of the threshold voltages. Other techniques and devices are also provided. | 07-31-2014 |
20140233322 | ADAPTIVE ARCHITECTURE IN A CHANNEL DETECTOR FOR NAND FLASH CHANNELS - An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether the read is successful, (iii) if the read is not successful, perform a plurality of reads with a varying value of the threshold voltage, (iv) read a calibration value from a look-up table based on the plurality of reads and (v) set the threshold value in response to the calibration value. | 08-21-2014 |
20140269100 | SHARED BIT LINE STRING ARCHITECTURE - Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings. | 09-18-2014 |
20140269101 | PROGRAMMING A MEMORY CELL TO A VOLTAGE TO INDICATE A DATA VALUE AND AFTER A RELAXATION TIME PROGRAMMING THE MEMORY CELL TO A SECOND VOLTAGE TO INDICATE THE DATA VALUE - A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is programmed to at least a second threshold voltage to indicate the particular data value. The second threshold voltage is greater than the first threshold voltage. | 09-18-2014 |
20140286105 | NAND FLASH MEMORY UNIT, OPERATING METHOD AND READING METHOD - A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased. | 09-25-2014 |
20140286106 | MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS - Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing. | 09-25-2014 |
20140301147 | SEMICONDUCTOR STORAGE WITH A FLOATING DETECTION CIRCUITRY AND FLOATING DETECTION METHOD THEREOF - A storage medium including a plurality of memory cells, a plurality of transmission lines, a driving module and a floating detection module is disclosed. The memory cells store data. The transmission lines are coupled to the memory cells. The driving module accesses the memory cells via the transmission lines. The floating detection module includes a reset unit, a plurality of connectors and a detector. The reset unit is coupled to a detection line. Each of the connectors is coupled between one of the transmission lines and the detection line. The detector determines whether a state of at least one of the transmission lines is a floating state according to a level of the detection line. | 10-09-2014 |
20140321215 | INHIBITING PILLARS IN 3D MEMORY DEVICES - Methods and controllers for programming a memory are provided. In one such method, a potential for pillars of the memory that are to be inhibited is lowered, and programming cells of the memory is accomplished while the pillars of the memory that are to be inhibited have the lower potential. | 10-30-2014 |
20140321216 | RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES - Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal. | 10-30-2014 |
20150023110 | INFERRING THRESHOLD VOLTAGE DISTRIBUTIONS ASSOCIATED WITH MEMORY CELLS VIA INTERPOLATION - The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values. | 01-22-2015 |
20150063037 | Non-Volatile Memory Devices and Related Operating Methods - Non-volatile memory devices and related methods are provided. The non-volatile memory devices include a memory cell array having a plurality of cell strings, each cell string including: a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and a bit line; an address decoder coupled to the plurality of memory cells in the plurality of cell strings through word lines, to the string selection transistors in the plurality of cell strings through string selection lines, and to the ground selection transistors in the plurality of cell strings through a ground selection line; a read/write circuit coupled to the string selection transistors in the plurality of cell strings through the bit lines; and control logic configured to adjust a substrate voltage applied to the substrate such that threshold voltages of the ground selection transistors are higher than a predetermined level during read operations for at least one of the plurality of memory cells in the plurality of cell strings. | 03-05-2015 |
20150138894 | FINDING OPTIMAL READ THRESHOLDS AND RELATED VOLTAGES FOR SOLID STATE MEMORY - A read is performed using a first iteration of a read threshold voltage that is set to a default voltage to obtain a first characteristic. A second iteration of the read threshold voltage is generated using the default voltage and an offset. A read is performed using the second iteration of the read threshold voltage to obtain a second characteristic. A third iteration of the read threshold voltage is generated using the first and second characteristics. A read is performed using the third iteration of the read threshold voltage to obtain a third characteristic. It is determined if the third characteristic is one of the two characteristics closest to a stored characteristic. If so, a fourth iteration of the read threshold voltage is generated using the two closest characteristics. | 05-21-2015 |
20150294728 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations. | 10-15-2015 |
20150310920 | STORAGE DEVICE, MEMORY CONTROLLER AND MEMORY CONTROL METHOD - According to one embodiment, a storage device comprises a nonvolatile memory and a memory controller that performs reading and writing data from and into the nonvolatile memory. A number, not being 2 | 10-29-2015 |
20160019973 | 3D STACKED MEMORY ARRAY AND METHOD FOR DETERMINING THRESHOLD VOLTAGES OF STRING SELECTION TRANSISTORS - This invention provides 3D stacked memory arrays and methods for determining threshold voltages of string selection transistors by LSMP (layer selection by multi-level permutation) for enabling to select layers regardless of the number or as many as possible by the limited numbers of threshold voltage states and SSLs. Thus, this invention enables to maximize the degree of integrity of memory by minimizing the number of SSLs and to select layers with no limitation of the number by considering a recent aspect ratio of the semiconductor etching process. | 01-21-2016 |
20160055913 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device is provided. The operating method of the semiconductor memory device includes programming a second source select transistor electrically coupled to a common source line through a first source select transistor; reprogramming the second source select transistor when a threshold voltage of the second source select transistor is less than a target voltage, and ending a program for the second source select transistor when the threshold voltage of the second source select transistor is greater than or equal to the target voltage. The programming includes electrically decoupling the second source select transistor from the common source line by turning off the first source select transistor. | 02-25-2016 |
20160078949 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first set of memory cells commonly connected to a first word line, a second set of memory cells commonly connected to a second word line, and a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines. The writing operation includes a coarse program operation and a fine program operation and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes starting the following operations in order: (1) the coarse program operation on the first set of memory cells; (2) the coarse program operation on the second set of memory cells; (3) the fine program operation on the first set of memory cells; and (4) the fine program operation on the second set of memory cells. | 03-17-2016 |
20160086670 | Ephemeral Storage Elements, Circuits, and Systems - An array of programmable non-volatile devices are is adapted such that their logic state is controllably altered over time by quiescent changes, slow controlled changes, scheduled changes, or some combination thereof imposed at a physical level. This allows for improved security and privacy for data to be permanently deleted. In some applications a data refresh and/or automatic backup can be implemented as well. | 03-24-2016 |
20160118128 | METHODS FOR REDUCING BODY EFFECT AND INCREASING JUNCTION BREAKDOWN VOLTAGE - Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of the transistor are described. The transistor may comprise an NMOS transistor that transfers a programming voltage (e.g., 24V) to a word line of a memory array during a programming operation. In some cases, a first poly shield may be positioned within a first distance of a gate of the transistor and may comprise a first polysilicon structure that is directly adjacent to the gate of the transistor. The first poly shield may be arranged in a first direction (e.g., in the channel length direction of the transistor). The first poly shield may be biased to a first voltage greater than ground (e.g., 10V) during the programming operation to reduce an increase in the threshold voltage of the transistor due to the body effect. | 04-28-2016 |
20160125951 | DETECTING VOLTAGE THRESHOLD DRIFT - Apparatuses, systems, methods, and computer program products are disclosed for detecting voltage threshold drift. A method includes programming a predetermined pattern to one page of at least three pages of a set of memory cells. A pattern may have a configuration to reduce a number of bit transitions between abodes of a set of memory cells based on a coding scheme for the set of memory cells. A method includes reading data from a different page of at least three pages. A method includes determining a direction for adjusting a read voltage threshold for a set of memory cells based on read data. | 05-05-2016 |
20160180958 | DYNAMICALLY COMPENSATING FOR DEGRADATION OF A NON-VOLATILE MEMORY DEVICE | 06-23-2016 |
20160203873 | MEMORY SYSTEM | 07-14-2016 |