| Entries |
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| 20080198656 | TIME-DEPENDENT COMPENSATION CURRENTS IN NON-VOLATILE MEMORY READ OPERATIONS - Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and consequently, lowering the sensed conduction current of a memory cell. The read process for a selected memory cell takes into account the state of one or more adjacent memory cells. If an adjacent memory cell is in one or more of a predetermined set of programmed states, a compensation current can be provided to increase the apparent conduction current of the selected memory cell. An initialization voltage is provided to the bit line of the programmed adjacent memory cell to induce a compensation current between the bit line of the programmed adjacent memory cell and the bit line of the selected memory cell. | 08-21-2008 |
| 20080205147 | Local self-boost inhibit scheme with shielded word line - A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by utilizing sets of two or more adjacent word lines and applying the same voltage to each in array access operations. This allows each word line of the set or pair to shield the other from word line to word line capacitive voltage coupling. In NAND memory string embodiments the various cells of strings of non-volatile memory cells are programmed utilizing modified or unmodified drain-side self boost, source-side self boost, local self boost, and virtual ground programming processes that utilize two or more “blocking” memory cells on either the source line side and drain line side of a selected memory cell. The paired blocking cells shield each other during programming to reduce coupled noise, to prevent charge leakage from the boosted channel of the selected memory cell. | 08-28-2008 |
| 20080205148 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers, each amplifier being connected to one of the plurality of bit lines respectively and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of the memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of the plurality of word lines respectively, the plurality of memory strings being connected to a corresponding bit line of the plurality of bit lines respectively, and at the time of programming all of the plurality of bit lines are selected, the number of the storage states being different in two of the memory cells which are adjacent on the same bit line. | 08-28-2008 |
| 20080212373 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A STACKED GATE INCLUDING A FLOATING GATE AND A CONTROL GATE - A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness. | 09-04-2008 |
| 20080219055 | MULTIPLE LEVEL PROGRAMMING IN A NON-VOLATILE MEMORY DEVICE - The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels. | 09-11-2008 |
| 20080225594 | Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array - A nonvolatile memory structure with pairs of serially connected select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the serially connected select transistors has an implant to make a threshold voltage of the implanted first serially connected select transistor different from a non-implanted second serially connected select transistor. The pair of serially connected top select transistors is connected to a first of two associated bit lines. Optionally, the NAND nonvolatile memory strings further is connected a pair of serially connected bottom select transistors that is connected to the second associated bit line. | 09-18-2008 |
| 20080232168 | LEVEL SHIFT CIRCUIT WHICH IMPROVED THE BLAKE DOWN VOLTAGE - A gate and the other end of the current path of first and second transistors are cross-connected. A third transistor is inserted to the other end of the current path of the first transistor, and a gate is supplied with a constant voltage, and further, one end of the current path and well are connected. A fourth transistor is inserted to the other end of the current path of the second transistor, and a gate is supplied with a constant voltage, and further, one end of the current path and well are connected. Fifth and sixth transistors are connected to the other end of the current path of the third and fourth transistors, and a gate is complementarily supplied with an input signal. Seventh and eighth transistors are connected to a back gate (well) of the third and fourth transistors, and a gate is complementarily supplied with an output signal. | 09-25-2008 |
| 20080232169 | NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES - A flash memory integrated circuit includes a plurality of flash memory arrays. A global word line driver is associated with each array, each global word line driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bit lines. A plurality of sub arrays in each array each include a plurality of NAND flash memory cells coupled to local word lines and local bit lines. A local word line driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local word lines in its sub array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bit line driver is coupled between selected ones of the local bit lines in each sub array and selected ones of the plurality of bit lines. | 09-25-2008 |
| 20080232170 | MEMORY DEVICE, A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING A MEMORY DEVICE - A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier. | 09-25-2008 |
| 20080239818 | THREE DIMENSIONAL NAND MEMORY - A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate line of the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line. | 10-02-2008 |
| 20080239819 | NAND FLASH MEMORY WITH FIXED CHARGE - A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also. | 10-02-2008 |
| 20080239820 | SELF-ADAPTIVE AND SELF-CALIBRATED MULTIPLE-LEVEL NON-VOLATILE MEMORIES - Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell. As the stepped voltage applied to the gate of an NVM cell transitions from a voltage just below the threshold voltage of the NVM cell to a voltage corresponding to the threshold voltage of the NVM cell, the output current (voltage) from the NVM cell will pass the current (voltage) transition in comparison with the reference current (voltage). The current (voltage) transition can be detected and converted into the bit-word information representing the voltage level stored in the NVM cell. When the response of an NVM cell falls outside the response tolerance window into the guard-band regions, the NVM cell can be re-calibrated and the bit-word information can be saved from fading away. | 10-02-2008 |
| 20080239821 | NAND MEMORY WITH SIDE-TUNNELING - A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer. | 10-02-2008 |
| 20080239822 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell. | 10-02-2008 |
| 20080253186 | Bit line structure for a multilevel, dual-sided nonvolatile memory cell array - A nonvolatile memory array includes a plurality of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. Pairs of braided bit lines are connected in a braided columnar bit line structure such that each column of the dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of braided bit lines. | 10-16-2008 |
| 20080253187 | MULTIPLE SELECT GATE ARCHITECTURE - Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing multiple series-coupled select gates, each gate can be made using smaller features sizes while achieving the same level of protection against GIDL and other forms of current leakage. By reducing the feature size of the select gates, the footprint of the strings of memory cells can be reduced, thereby facilitating smaller memory device sizing. Further reductions in device sizing may be achieved utilizing a staggered self-aligned bit line contact configuration. | 10-16-2008 |
| 20080253188 | PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY - A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level. | 10-16-2008 |
| 20080259687 | Integrated Circuits and Methods of Manufacturing Thereof - Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure. | 10-23-2008 |
| 20080259688 | Non-volatile memory devices and methods of operating the same - A non-volatile memory device includes memory transistors disposed on a semiconductor substrate in a NAND string. A string select transistor is disposed at a first end of the NAND string, and a ground select transistor is disposed at a second end of the NAN string. Bit lines are electrically connected to the semiconductor substrate outside of the string select transistor and a gate electrode of the ground select transistor. | 10-23-2008 |
| 20080259689 | MIMICKING PROGRAM VERIFY DRAIN RESISTANCE IN A MEMORY DEVICE - A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the bit line are biased with a modified V | 10-23-2008 |
| 20080266963 | COMPENSATING SOURCE VOLTAGE DROP IN NON-VOLATILE STORAGE - A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated. | 10-30-2008 |
| 20080266964 | NON-VOLATILE STORAGE WITH COMPENSATION FOR SOURCE VOLTAGE DROP - A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated. | 10-30-2008 |
| 20080266965 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING PLURAL DATA STORAGE PORTIONS FOR A BIT LINE CONNECTED TO MEMORY CELLS - Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used. | 10-30-2008 |
| 20080273388 | ADJUSTING RESISTANCE OF NON-VOLATILE MEMORY USING DUMMY MEMORY CELLS - In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming memory cells on the dummy word line(s), the resistances associated with the data memory cells can be changed to account for different programmed data patterns. | 11-06-2008 |
| 20080273389 | Flash memory cells, NAND cell units, methods of forming NAND cell units, and methods of programming NAND cell unit strings - Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate types, and capacitively coupled with control gates of the first gate types. The second gate types may be multilevel cell (MLC) devices, and pass voltage applied to the control gates of the first gate types may be utilized to reduce programming voltages utilized to reach memory states of the MLC devices. Some embodiments include NAND cell units, and some embodiments include methods of forming NAND cell units. Also, some embodiments include methods of programming NAND cell unit string gates in which programming voltage applied to a first string gate is held below a threshold, and pass voltage applied to an adjacent string gate is increased and utilized to program the first string gate. | 11-06-2008 |
| 20080273390 | NAND flash memory cell array and method of fabricating the same - A novel NAND flash memory cell array and the method of fabricating the same are disclosed in this invention. The NAND flash memory cell array comprises a substrate with an active area; a plurality of cells arranged in a row on the active area; a first barrier layer covering the cells and the active area around each end of the row; a first oxide deposited to fill a gap between the cells; an oxide spacer formed along the sidewall of a cell located at each end of the row; and a poly spacer formed on the oxide spacer acting as a selection gate for driving the row of cells. The aspect ratio of the gap between the cells is about 1.8 to 3.2. Many advantages are provided with such NAND flash memory fabricating by the self-aligned process of the present invention. | 11-06-2008 |
| 20080279007 | BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING - Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed. | 11-13-2008 |
| 20080279008 | NON-VOLATILE STORAGE WITH BOOSTING USING CHANNEL ISOLATION SWITCHING - Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed. | 11-13-2008 |
| 20080285349 | NONVOLATILE MEMORY WITH BACKPLATE - The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common. In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors. | 11-20-2008 |
| 20080285350 | Circuit and method for a three dimensional non-volatile memory - An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. Preferred SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment and a planar FD-SOI embodiment cell are disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems from subsequent thermal processing steps. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non volatile arrays formed of the SONOS cells rely on conventional semiconductor processing and so are easily integrated with other circuitry to form an ASIC or SoC device. P-channel and n-channel devices may be used to form the SONOS non-volatile cells. | 11-20-2008 |
| 20080298127 | Method of Reading Flash Memory Device for Depressing Read Disturb - Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected transistor among the plurality of memory cells. Then, a pass voltage is applied to gates of unselected transistors among the plurality of memory cells. Furthermore, when the pass voltage is applied, a first pass voltage is applied and then a second pass voltage is applied after an elapse of a predetermined time following the applying of the first pass voltage. The second pass voltage has a level different from that of the first pass voltage. | 12-04-2008 |
| 20080310232 | ERASE VERIFY FOR MEMORY DEVICES - Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to apply a first voltage to gates of the first memory cells during a verify operation of the first memory cells, and second word lines configured to apply a second voltage to gates of the second memory cells during the verify operation. | 12-18-2008 |
| 20080310233 | MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS - Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer. | 12-18-2008 |
| 20080316827 | NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS - A non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates. | 12-25-2008 |
| 20080316828 | Memory in logic cell - Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type. | 12-25-2008 |
| 20080316829 | SYSTEM FOR VERIFYING NON-VOLATILE STORAGE USING DIFFERENT VOLTAGES - When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. In some embodiments, the second voltage is lower than the first voltage. | 12-25-2008 |
| 20090003068 | METHOD FOR SOURCE BIAS ALL BIT LINE SENSING IN NON-VOLATILE STORAGE - Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground. | 01-01-2009 |
| 20090003069 | NON-VOLATILE STORAGE WITH SOURCE BIAS ALL BIT LINE SENSING - A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground. | 01-01-2009 |
| 20090003070 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string. | 01-01-2009 |
| 20090010064 | NAND FLASH CELL STRUCTURE - NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel r | 01-08-2009 |
| 20090010065 | NON-VOLATILE MEMORY USING MULTIPLE BOOSTING MODES FOR REDUCED PROGRAM DISTURB - A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device. | 01-08-2009 |
| 20090016110 | METHODS OF READING DATA FROM NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically connected to a selected cell located in a selected string. A first read voltage is applied to word lines electrically connected to first non-selected cells separated from the selected cell in the selected string, and a second read voltage is applied to word lines electrically connected to second non-selected cells adjacent to the selected cell in the selected string. The second read voltage is lower than the first read voltage. A pass voltage is applied to turn on a string select transistor and a ground select transistor, respectively, in the selected string. An electrical signal output from the selected string is compared with a standard signal to read data stored in the selected cell. | 01-15-2009 |
| 20090016111 | Flash memory device and program recovery method thereof - A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages. | 01-15-2009 |
| 20090016112 | Method of Programming a Flash Memory Device - A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell(s). This voltage level of the blocking voltage is set so that Vdcp| 01-15-2009 | |
| 20090021982 | SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF - A semiconductor memory device includes a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first and second select transistors, a source line, and a bit line, wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage. | 01-22-2009 |
| 20090021983 | Word Line Compensation In Non-Volatile Memory Erase Operations - Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used. | 01-22-2009 |
| 20090027968 | NAND FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A NAND flash memory device having memory cells for storing data includes a fuse circuit configured to store option information for operation of the NAND flash memory device as logic codes. A register circuit includes registers for temporarily storing the logic codes stored in the fuse circuit. A test circuit is configured to change the logic code stored in the register circuit and store the changed logic code irrespective of the logic code of the fuse circuit for test operation of the NAND flash memory device. A processor is configured to control operation of the NAND flash memory device. | 01-29-2009 |
| 20090034336 | Flash memory device having improved bit-line layout and layout method for the flash memory device - Provided are a flash memory device having an improved bit-line layout and a layout method for the flash memory device. The flash memory device in which bit lines are disposed based on double patterning technology (DPT), may include at least one main bit line connected to a cell string including a memory cell storing data, at least one dummy bit line disposed parallel to the at least one main bit line, and a common source line transferring a common source voltage, and disposed on a different layer from a layer on which the at least one main bit line and the at least one dummy bit line are disposed, wherein the at least one dummy bit line may include a first dummy bit line transferring a first voltage and a second dummy bit line transferring a second voltage. | 02-05-2009 |
| 20090046515 | NOR Flash Memory Device and Method for Fabricating the Same - Embodiments of a NOR flash memory and method for fabricating the same are provided. Bit lines can be formed as self-aligned source and drain regions between adjacent first polysilicon patterns. Contacts for the source and drain regions can be provided according to bit line instead of per cell. Word lines can be formed as second polysilicon patterns, which are used as control gates, and are provided perpendicular to the longitudinal axis of the bit lines. During formation of the second polysilicon patterns, a dielectric film and exposed regions of the first polysilicon patterns can be etched to form floating gates below the second polysilicon patterns. | 02-19-2009 |
| 20090052251 | INTEGRATED CIRCUIT MEMORY DEVICES INCLUDING MEMORY CELLS ON ADJACENT PEDESTALS HAVING DIFFERENT HEIGHTS, AND METHODS OF FABRICATING SAME - Coupling among adjacent rows of memory cells on an integrated circuit substrate may reduced by forming the adjacent rows of memory cells on adjacent semiconductor pedestals that extend different distances away from the integrated circuit substrate. NAND flash memory devices that include different pedestal heights and fabrication methods for integrated circuit memory devices are also disclosed. | 02-26-2009 |
| 20090052252 | METHODS OF APPLYING READ VOLTAGES IN NAND FLASH MEMORY ARRAYS - Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage. | 02-26-2009 |
| 20090059669 | NAND TYPE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING SIDEFACE ELECTRODE SHARED BY MEMORY CELLS - An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel region to thereby improve operation margins is disclosed. The NAND EEPROM, also known as NAND flash memory, has on a semiconductive substrate an array of memory cells including a serial combination of memory cell transistors. Each of memory cell transistors has a pair of source and drain regions, a channel region, a tunnel insulator film, a charge storage layer, a control dielectric film, a control electrode, a sideface dielectric film on the sidefaces of the channel region, and sideface electrodes which are formed on the side surfaces of channel region with the channel region being laterally interposed therebetween. The sideface electrodes are commonized or “shared” by adjacent ones of the serially coupled memory cell transistors. | 03-05-2009 |
| 20090067246 | Methods to Prevent Program Disturb in Nonvolatile Memory - Methods are provided to be used individually or in any combination that reduce program disturb in a non-volatile memory consisting of dual-gate memory cells. These methods counteract the effect of a leakage current in reducing a boosted voltage in a non-selected dual-gate memory string. According to one approach, a voltage applied to the gate electrode of an access device of a dual-gate memory cell is increased during a programming event. According to a second approach, the gate electrodes of an access device of a dual-gate memory cell is applied a series of electrical pulses synchronously with programming the memory device of the dual-gate memory cell by a second series of electrical pulses. According to a third approach, multiple dual-gate select devices are provided between a string of dual-gate memory devices and either a source line or a bit line, or both. | 03-12-2009 |
| 20090067247 | Method of programming nonvolatile memory device - A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage. | 03-12-2009 |
| 20090080258 | ERASE METHOD IN THIN FILM NONVOLATILE MEMORY - An erase method applicable to dual-gate memory strings has key advantages over erase methods for other thin-film non-volatile memory strings. The advantages include (a) fast erase without any source-to-body short; (b) flexible erase which erases any number of memory cells in a block (i.e., from none to all cells); (c) source voltage may be set to optimize non-selected string channel boosting; and (d) the thickness of the thin-film device's body can be optimized for scalability. The method uses the access devices of the dual-gate memory cells in a memory string to form inversion channels, so as to provide conductive paths between the memory cells to be erased and a node at a more positive voltage than the erase voltage applied to the gate electrodes of the memory devices to be erased. | 03-26-2009 |
| 20090086542 | High Voltage Generation and Control in Source-Side Injection Programming of Non-Volatile Memory - Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used. | 04-02-2009 |
| 20090097317 | Integrated Circuit Having NAND Memory Cell Strings - Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench. | 04-16-2009 |
| 20090097318 | Programming sequence in NAND memory - An analog voltage NAND architecture non-volatile memory device and programming process is described that reduce the effects of NAND string resistance in source follower sensing by programming the cells in NAND memory cell strings to maintain the resistance presented by the unselected cells on the source-side of a given selected memory cell of the NAND string during both the verify and read. In particular, in one embodiment of the present invention, the cells in the NAND string are programmed sequentially in order from the cells closest the bit line to the final cell that is closest the source line in the string. This allows the source follower sensing of the verify and later read operations to read the programmed threshold voltage across the same stable source-side resistance | 04-16-2009 |
| 20090097319 | APPLYING ADAPTIVE BODY BIAS TO NON-VOLATILE STORAGE BASED ON NUMBER OF PROGRAMMING CYCLES - Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage. | 04-16-2009 |
| 20090103364 | SERIAL INTERFACE NAND - Embodiments are provided that include operating a NAND memory device via an SPI interface. One such method includes cache loading a NAND memory device including loading data into a cache of the NAND memory device, writing data from the cache of the NAND memory device to an address of a memory array of the NAND memory device, and polling to determine the status of the data being written. Further one such method includes caching of data in a NAND memory device via an SPI interface comprising loading first data to a cache of the NAND memory device, writing the first data to a first address of a NAND memory array of the NAND memory device, polling the status of the cache, if polling indicates that the cache is ready, then loading a portion of the cache with second data, polling the status of the cache and the NAND memory device, and if polling indicates that the cache is ready and the device is ready, writing the second data to a second address of the NAND memory array of the NAND memory device. | 04-23-2009 |
| 20090103365 | Sensing of memory cells in NAND flash - An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (Vpass) is placed on the gates of the unselected cells of the string to place them in a pass through mode of operation, and a read gate voltage (Vg) is applied to the gate of the selected cell. The selected memory cell operates as a source follower to set a voltage on the coupled bit line at the read gate voltage minus the threshold voltage of the cell (Vg−Vt), allowing the voltage of the cell to be directly sensed or sampled. | 04-23-2009 |
| 20090116290 | METHODS AND APPARATUSES RELATING TO AUTOMATIC CELL THRESHOLD VOLTAGE MEASUREMENT - Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells and a pre-charge bit line reference circuit. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a pre-charged bit line reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 10 nA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed. | 05-07-2009 |
| 20090122613 | Non-volatile memory device and method of operating the same - A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings. | 05-14-2009 |
| 20090129165 | Nonvolatile Memory Devices and Methods of Operating Same to Inhibit Parasitic Charge Accumulation Therein - Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells. | 05-21-2009 |
| 20090141555 | METHOD OF PROGRAMMING AND ERASING A P-CHANNEL BE-SONOS NAND FLASH MEMORY - A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state. | 06-04-2009 |
| 20090147584 | NAND ARCHITECTURE MEMORY DEVICES AND OPERATION - Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device. | 06-11-2009 |
| 20090154247 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 06-18-2009 |
| 20090161436 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device related to an embodiment of the present invention including a memory string in which a plurality of memory cells are connected, a bit line connected to an end of the memory string, a power supply circuit which generates a voltage or a current related to an operation state of each memory cell, a sense amplifier which supplies a control voltage or a control current which controls an operation state of each memory cell via the bit line according to the voltage or the current generated in the power circuit, and a transient response adjustment circuit which adjusts the transient response characteristics of the voltage or the current generated in the power supply circuit when the sense amplifier supplies to the bit line the control voltage or the control current which shifts the memory string from a first operation state to a second operation state. | 06-25-2009 |
| 20090161437 | HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY - Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground. | 06-25-2009 |
| 20090168532 | NONVOLATILE MEMORY DEVICES THAT UTILIZE DUMMY MEMORY CELLS TO IMPROVE DATA RELIABILITY IN CHARGE TRAP MEMORY ARRAYS - A charge trap flash memory device includes a flash memory array having at least a first page of charge trap memory cells therein electrically coupled to a first word line. The first page of charge trap memory cells includes a plurality of addressable memory cells configured to store data to be retrieved during read operations and a plurality of immediately adjacent non-addressable “dummy” memory cells configured to store dummy data that is not retrievable during the read operations. The plurality of dummy memory cells include at least one auxiliary dummy memory cell that operates as a buffer against lateral hole transfer within a charge trap layer of the array. | 07-02-2009 |
| 20090168533 | THREE-DIMENSIONAL MEMORY DEVICE AND PROGRAMMING METHOD - A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each memory array having a string of memory cells. The programming method includes, for each unselected string associated with an unselected layer in the plurality of layers, charging the channel of memory cells associated with unselected string with a shut-off voltage, and thereafter programming a selected string associated with a selected layer in the plurality of layers. | 07-02-2009 |
| 20090168534 | THREE-DIMENSIONAL MEMORY DEVICE WITH MULTI-PLANE ARCHITECTURE - Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane. | 07-02-2009 |
| 20090180324 | Semiconductor Constructions, NAND Unit Cells, Methods Of Forming Semiconductor Constructions, And Methods Of Forming NAND Unit Cells - Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells. | 07-16-2009 |
| 20090180325 | Partitioned Erase And Erase Verification In Non-Volatile Memory - A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset. In one embodiment, the bias conditions for the string during each individual erase are selected so that every memory cell of the set will experience similar capacitive coupling effects from neighboring transistors. | 07-16-2009 |
| 20090190404 | NAND FLASH CONTENT ADDRESSABLE MEMORY - NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics for low power and portable applications. In one NAND architecture non-volatile CAM memory embodiment a wired NOR match line array is utilized. In another embodiment a NAND match line array is shown. In yet other embodiments, hierarchal addressing, hash addressing, tree search and algorithmic/hardware engine based search is detailed utilizing both conventional NAND architecture non-volatile Flash memory arrays and dedicated NAND architecture CAM arrays utilizing wired NOR and wired NAND match lines. | 07-30-2009 |
| 20090190405 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses. | 07-30-2009 |
| 20090201738 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier which detects a voltage or a current of the bit line, and which decides the read data from each of the memory cells; a clamping transistor which is connected between the sense amplifier and the bit lines, and which determines a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer. | 08-13-2009 |
| 20090213658 | READING NON-VOLATILE STORAGE WITH EFFICIENT SETUP - A process for reading data (including verifying during programming) from a selected non-volatile storage elements of a group (e.g., NAND string) of non-volatile storage elements includes maintaining an intermediate voltage as a control gate voltage for an unselected non-volatile storage element and subsequently changing the control gate voltage for the unselected non-volatile storage element from the intermediate voltage to a read enable voltage. The control gate voltage for the selected non-volatile storage element is raised from a standby voltage (which is different than the intermediate voltage) to a read compare voltage. While the control gate for the selected non-volatile storage element is at the read compare voltage and the control gate for the unselected non-volatile storage element is at the read enable voltage, the state of the selected non-volatile storage element is sensed to determine information about the data stored in the selected non-volatile storage element. | 08-27-2009 |
| 20090238001 | Interface for NAND-Type Flash Memory - A NAND-type flash memory device is described. In some embodiments, the memory device includes NAND-type flash memory cells, and a synchronous NAND interface. The synchronous NAND interface includes a standard NAND flash interface pin arrangement and a clock (CLK) pin. The synchronous NAND interface is configured to interface with a NOR-compatible memory interface. | 09-24-2009 |
| 20090238002 | NAND TYPE NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF - A NAND type non-volatile memory having a plurality of bit lines and a dummy bit line is provided. The intersections of each of the bit lines with a first select gate line, a plurality of word lines, and a second select gate line are corresponding to a memory cell row. The intersections of the dummy bit line with the first select gate line, the word lines, and the second select gate line are corresponding to a dummy memory cell row. A source line is disposed on the substrate at one side of the memory cell rows, wherein the dummy memory cell row and the dummy bit line are served as a current path for connecting the source line. | 09-24-2009 |
| 20090238003 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage. | 09-24-2009 |
| 20090251967 | NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL - A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well. | 10-08-2009 |
| 20090251968 | Integrated circuit having a base structure and a nanostructure - In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure. | 10-08-2009 |
| 20090257279 | MEMORY DEVICE OPERATION - Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device or by using one bit line as a ground node for sensing current flow through the strings. The use of bit lines for virtual grounding is further suitable to other array architectures. | 10-15-2009 |
| 20090262579 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING DATA IN NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES - The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both electrically separated from each other. In this mode, a write non-selection voltage applied to a non-selected memory cell next to the second selection gate transistor is switched, at least in two stages, between a lower voltage V | 10-22-2009 |
| 20090262580 | FLASH MEMORY DEVICE ADAPTED TO PREVENT READ FAILURES DUE TO DUMMY STRINGS - In a NAND flash memory device, a dummy NAND string is arranged between a plurality of normal NAND strings. A dummy bit line connected to the dummy NAND string is formed and/or controlled such that when program voltages are applied to the normal NAND strings, memory cells within the dummy NAND string are not programmed. | 10-22-2009 |
| 20090273978 | NAND FLASH MEMORY - A NAND flash memory has a control circuit. The control circuit applies a writing voltage between a control gate and a well by applying a first voltage to the well and a positive second voltage higher than the first voltage to the control gate during the writing operation, and then the control circuit applies a detrapping voltage between the control gate and the well by applying a third voltage to the control gate and a positive fourth voltage higher than the third voltage to the well before the verification reading operation. | 11-05-2009 |
| 20090273979 | PROGRAMMING METHOD TO REDUCE WORD LINE TO WORD LINE BREAKDOWN FOR NAND FLASH - A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage differences between the word lines of the memory cell string or array during a programming cycle. This allows the word line to word line voltage differential to be reduced and thus decreases the likelihood of breakdown or punch through of the insulator materials placed between the adjacent word lines. | 11-05-2009 |
| 20090273980 | NAND ARCHITECTURE MEMORY WITH VOLTAGE SENSING - A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell that is coupled to a reference bit line. A voltage is precharged onto a bit line to be read and an associated reference bit line. The bit line is then coupled to a NAND string and selected memory cell while the reference bit line is coupled to a reference NAND string and selected reference memory cell. The relative voltage level of the bit line and reference bit line are then set by the relative currents flowing through the coupled NAND string and reference NAND string, and the voltage differential read by a coupled voltage sense amplifier. | 11-05-2009 |
| 20090279359 | NAND WITH BACK BIASED OPERATION - Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts | 11-12-2009 |
| 20090279360 | NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash memory array, and a method of forming a NAND based NMOS NOR flash memory array - A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process. | 11-12-2009 |
| 20090285027 | Non-volatile memory devices and methods of operating non-volatile memory devices - A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line. | 11-19-2009 |
| 20090296475 | VERIFICATION PROCESS FOR NON-VOLATILE STORAGE - When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements. | 12-03-2009 |
| 20090296476 | Flash Memory Device and Method for Manufacturing the Same - A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge. | 12-03-2009 |
| 20090296477 | Nonvolatile Memory Devices Having Electromagnetically Shielding Source Plates - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder. | 12-03-2009 |
| 20090303794 | Structure and Method of A Field-Enhanced Charge Trapping-DRAM - A field-enhanced (FE) charge trapping-DRAM (TDRAM) device is described which is suitable for DRAM applications, and for additional applications with lower power requirements. In some embodiments, the FE-TDRAM device comprises a charge trapping FinFET structure including an upside-down U-shaped volatile programmable structure and an upside-down U-shaped dielectric structure overlying the volatile programmable structure. | 12-10-2009 |
| 20090303795 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 12-10-2009 |
| 20090303796 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including: a memory cell coupled to a bit line via a select gate transistor; a sense amplifier configured to have a current source for supplying current to the bit line, and detect cell current of the memory cell flowing on the bit line; and a select gate line driver configured to drive the select gate transistor so as to keep the memory cell applied with substantially constant drain-source voltage independently of the bit line resistance at a read time. | 12-10-2009 |
| 20090310414 | NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same - A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/driver circuits are connected to blocks of the charge retaining transistors for controlling the application of the necessary read, program, and erase signals. Erase count registers, each of the erase count registers associated with one block of the array of the charge retaining transistors for storing an erase count for the associated block for determining whether a refresh operation is to be executed. Groupings on each column of the array of charge retaining transistors are connected as NAND series strings where each NAND string has a select gating charge retaining transistor connected to the top charge retaining transistor for connecting the NAND series string to the bit lines. | 12-17-2009 |
| 20090310415 | NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND STRINGS AND METHODS OF FORMING THE SAME - A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device. | 12-17-2009 |
| 20090310416 | SELECTIVE THRESHOLD VOLTAGE VERIFICATION AND COMPACTION - Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string. | 12-17-2009 |
| 20090323420 | MINIMIZING POWER NOISE DURING SENSING IN MEMORY DEVICE - In a sensing method, accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different sense amps are strobed at different times. First and second sets of sense amps perform a sensing operation on respective storage elements, such as in an all bit line configuration. The first set of sense amps is strobed at a first time point. In response, a sensed analog level is converted to digital data. The A/D conversion relies on the sense amp supply voltage being accurate. To avoid a fluctuation in the sense amp supply voltage, a bypass path allows the storage elements associated with the first set of sense amps to continue to draw power from the sense amp supply voltage. The second set of sense amps is strobed at a later, second time point. | 12-31-2009 |
| 20090323421 | MEMORY DEVICE WITH POWER NOISE MINIMIZATION DURING SENSING - Accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different sense amps are strobed at different times. First and second sets of sense amps perform a sensing operation on respective storage elements, such as in an all bit line configuration. The first set of sense amps is strobed at a first time point. In response, a sensed analog level is converted to digital data. The A/D conversion relies on the sense amp supply voltage being accurate. To avoid a fluctuation in the sense amp supply voltage, a bypass path allows the storage elements associated with the first set of sense amps to continue to draw power from the sense amp supply voltage. The second set of sense amps is strobed at a later, second time point. | 12-31-2009 |
| 20100002513 | Selective Erase Operation For Non-Volatile Storage - A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line) without intentionally erasing other non-volatile storage elements that are connected to the common word line (or other type of control line) but not in the subset. | 01-07-2010 |
| 20100002514 | Correcting For Over Programming Non-Volatile Storage - A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line). | 01-07-2010 |
| 20100002515 | Programming And Selectively Erasing Non-Volatile Storage - A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data. | 01-07-2010 |
| 20100002516 | Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same - Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors. | 01-07-2010 |
| 20100027340 | PATTERN DEPENDENT STRING RESISTANCE COMPENSATION - Pattern dependent string resistance compensation of a memory device is generally described. In one example, an electronic device includes a first string of memory cells and a first bit line coupled with the first string of memory cells wherein a memory cell of the first string of memory cells is read, in part, by pre-charging the first bit line through the first string of memory cells to compensate for resistance of unselected cells in the first string of memory cells. | 02-04-2010 |
| 20100027341 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time. | 02-04-2010 |
| 20100039862 | READ OPERATION FOR NAND MEMORY - Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively coupled to a bit line through a string of series-coupled non-volatile memory cells containing a memory cell targeted for reading, and where a second, different, potential is supplied to other source lines selectively coupled to the bit line through other strings of series-coupled non-volatile memory cells not containing the target memory cell. Supplying a different potential to the other source lines facilitates mitigation of current leakage between the other source lines and the bit line while sensing a data value of the target memory cell. | 02-18-2010 |
| 20100046294 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes dummy cell transistors connected to the first and second strings, and first and second dummy word lines configured to receive different bias voltages. | 02-25-2010 |
| 20100046295 | FAST DATA ACCESS MODE IN A MEMORY DEVICE - A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode. | 02-25-2010 |
| 20100061151 | MULTI-PASS PROGRAMMING FOR MEMORY WITH REDUCED DATA STORAGE REQUIREMENT - Coupling effects between adjacent floating gates in a non-volatile storage device are reduced in a multi-pass programming operation, while reducing program data storage requirements. In one approach, storage elements are programmed in an out of sequence or zigzag word line order. A particular word line is programmed with a coarse program pass, after which another word line is programmed with a fine program pass, after which the particular word line is read. The particular word line is read before another word line is programmed with a coarse program pass which causes coupling interference to storage elements of the particular word line. The read data is subsequently used to perform a fine program pass for the particular word line. This avoids the need to store program data of multiple word lines concurrently, so that storage hardware can be reduced in size along with power consumption. | 03-11-2010 |
| 20100067299 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory device including a NAND string with multiple memory cells connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the device has a data read mode performed under the bias condition of: a selected cell is applied with a read voltage; and unselected cells are applied with read pass voltages, and wherein in the data read mode, one of the unselected cells adjacent to one of the first and second select gate transistor is applied with a first read pass voltage while the other unselected cells are applied with a second read pass voltage lower than the first read pass voltage. | 03-18-2010 |
| 20100067300 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being configured by an assembly of NAND cell units, each of the NAND cell units including a plurality of nonvolatile memory cells connected in series and word lines configured to commonly connect control gates of the memory cells. A data erase operation is executed by first applying a pre-charge voltage to the word lines, then setting to a floating state the word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to the word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where the memory cell array is formed, thereby altering a threshold voltage of the memory cells in the selected block. | 03-18-2010 |
| 20100074014 | DATA STATE-BASED TEMPERATURE COMPENSATION DURING SENSING IN NON-VOLATILE MEMORY - Temperature effects in a non-volatile storage device are addressed by providing a data state-dependent, and optionally temperature dependent, sense current during verify and read operations. A different sense current is provided for each data state, so that a common temperature coefficient is realized for storage elements with different data states. The temperature coefficient for higher states can be reduced to that of lower states. During sensing, a sense time can be adjusted to achieve a desired sense current when a selected storage element is in a conductive state. A fixed voltage trip point may be maintained. During the sense time, a pre-charged capacitor discharges into a selected storage element such as via a bit line and NAND string, when the selected storage element is in a conductive state. The discharge level is translated to a current which is compared to a state-dependent, and optionally temperature dependent, reference current. | 03-25-2010 |
| 20100074015 | SENSING FOR MEMORY READ AND PROGRAM VERIFY OPERATIONS IN A NON-VOLATILE MEMORY DEVICE - Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line. | 03-25-2010 |
| 20100074016 | DATA RETENTION OF LAST WORD LINE OF NON-VOLATILE MEMORY ARRAYS - Techniques are disclosed herein for operating non-volatile storage. The techniques compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on different word lines. An erase of a group of non-volatile storage elements is performed. A set of the non-volatile storage elements are for storing data and at least one of the non-volatile storage elements is a dummy that is not for storing data. The dummy is a neighbor to one of the data non-volatile storage elements. The data non-volatile storage elements are programmed at some point after the erase. Then, a programming voltage is applied to the dummy non-volatile storage element to increase the threshold voltage of the dummy to cause floating gate coupling effect to the neighbor non-volatile storage element to compensate for lesser floating gate coupling effect that the neighbor experienced during programming. | 03-25-2010 |
| 20100074017 | Method for Programming Nand Type Flash Memory - Disclosed is a method for programming a flash memory device capable of preventing a threshold voltage distribution of a memory cell from being moved due to a pass disturbance of the memory cell programmed initially at a program operation performed on a page-unit basis. The method for programming a NAND flash memory device including a plurality of cell strings having N memory cells connected, in which gates of the memory cells are connected to a word line, the method is performed by applying a program voltage to at least two word lines simultaneously including a selected word line. | 03-25-2010 |
| 20100074018 | READ OPERATION FOR NON-VOLATILE STORAGE WITH COMPENSATION FOR COUPLING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. | 03-25-2010 |
| 20100074019 | MEMORY CARD, SEMICONDUCTOR DEVICE, AND METHOD OF CONTROLLING MEMORY CARD - A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile semiconductor memory, and a load section which activates the second program on the basis of the information written to the nonvolatile semiconductor memory to modify the function of the first program. | 03-25-2010 |
| 20100074020 | CHARGE PUMP OPERATION IN A NON-VOLATILE MEMORY DEVICE - A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage. | 03-25-2010 |
| 20100074021 | NAND FLASH MEMORY PROGRAMMING - A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages. | 03-25-2010 |
| 20100080061 | NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors. | 04-01-2010 |
| 20100085811 | SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME - A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that are coupled to the first select gate. Gates associated with the plurality of wordlines are formed of p+ polysilicon. A second select gate that has a width of 140 nm or less is coupled to the plurality of wordlines. | 04-08-2010 |
| 20100085812 | Nonvolatile Memory Devices Having Common Bit Line Structure - Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings. A first string selection line is connected to one of the first and second selection transistors of a first memory string of one pair of memory strings that are connected to one of the common bit lines. A second string selection line is connected to one of the first and second selection transistors of a second memory string of one pair of memory strings that are connected to one of the common bit lines. Multiple word lines are connected to control gates of the unit elements having the NAND cell array structure which are arranged in the same rows. | 04-08-2010 |
| 20100091571 | NONVOLATILE MEMORY DEVICE WITH NAND CELL STRINGS - A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage. | 04-15-2010 |
| 20100097861 | Multi-Pass Programming For Memory Using Word Line Coupling - A multiple pass programming scheme is optimized using capacitive coupling in the word line to word line direction during program-verify operations. A different pass voltage is used in different programming passes on an adjacent word line of a selected word line which is being verified. In particular, a lower pass voltage can be used in a first pass than in a second pass. The programming process may involve a word line look ahead or zigzag sequence in which WLn is programmed in a first pass, followed by WLn+1 in a first pass, followed by WLn in a second pass, followed by WLn+1 in a second pass. An initial programming pass may be performed before the first pass in which storage elements are programmed to an intermediate state and/or to a highest state. | 04-22-2010 |
| 20100097862 | FLASH MEMORY DEVICES WITH MEMORY CELLS STRINGS INCLUDING DUMMY TRANSISTORS WITH SELECTIVE THRESHOLD VOLTAGES - Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to a bit line and a second memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to the bit line. The first dummy memory cells of the first and second memory cell strings have gates connected in common to a first dummy word line and have different threshold voltages and the second dummy memory cells of the first and second memory cell strings have gates connected in common to a second dummy bit line and have different threshold voltages. In some embodiments, the first dummy memory cell of the first memory cell string and the second dummy memory cell of the second memory cell string may have threshold voltages greater than a predetermined voltage and the second dummy memory cell of the first memory cell string and the first dummy memory cell of the second memory cell string may have threshold voltages less than the predetermined voltage. | 04-22-2010 |
| 20100110792 | PAIR BIT LINE PROGRAMMING TO IMPROVE BOOST VOLTAGE CLAMPING - A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry. | 05-06-2010 |
| 20100124118 | Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array - A nonvolatile memory structure with pairs of serially connected threshold voltage adjustable select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the threshold voltage adjustable select transistors has its threshold voltage level adjusted to a first threshold voltage level and a second of the threshold voltage adjustable select transistors adjusted to a second threshold voltage level. The pair of serially connected threshold voltage adjustable select transistors is connected to a first of two associated bit lines. The NAND nonvolatile memory strings further is connected to a pair of serially connected threshold voltage adjustable bottom select transistors that is connected to the second associated bit line. | 05-20-2010 |
| 20100128533 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of strings each of which is configured with a first select transistor, a second select transistor, and a plurality of memory cells connected in series between the first and second select transistors. A common source line is connected to a source of the second select transistor. A metal interconnection is electrically insulated from the common source line, and connected to the source of the second select transistor. | 05-27-2010 |
| 20100142280 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 06-10-2010 |
| 20100157677 | NON-VOLATILE SEMICONDUCTOR MEMORY - A non-volatile semiconductor memory device is provided so that chip size may not increase and occurrence of misreading induced by capacitance of adjacent global bit lines GBL may be prevented, and includes: a non-volatile memory cell array for recording data by setting a threshold voltage for each memory cell transistor serially connected between selection transistors on terminals of a selected bit line; and a control circuit | 06-24-2010 |
| 20100157678 | NON-VOLATILE MEMORY WITH BOOST STRUCTURES - A non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string. | 06-24-2010 |
| 20100165733 | NAND NONVOLATILE SEMICONDUCTOR MEMORY - A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines respectively connected to control gate electrodes of the memory cells, a first selection transistor connected between one end of the memory cells and a source line, a second selection transistor connected between the other end of the memory cells and a bit line, and a driver configured to control voltages applied to the word lines. The driver applies a first voltage to a first word line connected to a selected memory cell, and applies a cutoff voltage that cuts off a channel of a memory cell to second word lines of a number not less than three arranged side by side on the source line side with respect to the first word line during a write operation. | 07-01-2010 |
| 20100172182 | Nonvolatile memory device and method for operating the same - Disclosed is a nonvolatile memory device which includes a plurality of cell array layers stacked on a semiconductor substrate. Each of the plurality of cell array layers includes a plurality of strings. Each of the plurality of strings has string and ground select transistors and a plurality of memory cells connected in series between the string and ground select transistors. A common source line is on each of the plurality of cell array layers. Each common source line is connected with first sides of the plurality of strings on a corresponding cell array layer. A plurality of bit lines is connected with second sides of the plurality of strings disposed on the cell array layers and arranged in the vertical direction to the semiconductor substrate. A plurality of word lines is connected with the plurality of memory cells. | 07-08-2010 |
| 20100177566 | Non-volatile memory device having stacked structure, and memory card and electronic system including the same - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set. | 07-15-2010 |
| 20100195395 | Non-volatile memory device having vertical structure and method of operating the same - A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string. | 08-05-2010 |
| 20100195396 | SEMICONDUCTOR MEMORY DEVICE AND SELF-TEST METHOD OF THE SAME - A semiconductor memory device includes a main memory includes a nonvolatile memory, and a buffer which stores input/output data of the nonvolatile memory, a buffer unit of the main memory, the buffer unit includes a volatile memory, a self-test interface includes a data input/output pin, and a controller which controls the main memory and the buffer unit. The controller at least stores data in the buffer from the self-test interface via the data input/output pin. | 08-05-2010 |
| 20100195397 | Controlled Boosting In Non-Volatile Memory Soft Programming - A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The level of boosting in the channel region of the inhibited NAND string is governed by the pre-charge voltage and the soft programming voltage. By controlling the pre-charge voltage, more reliable and consistent channel boosting can be achieved. In one embodiment, the pre-charge voltage is increased between applications of the soft programming voltage to reduce or eliminate a rise in the channel's boosted potential. In one embodiment, the soft programming pre-charge voltage level(s) is determined during testing that is performed as part of a manufacturing process. | 08-05-2010 |
| 20100195398 | APPLYING DIFFERENT BODY BIAS TO DIFFERENT SUBSTRATE PORTIONS FOR NON-VOLATILE STORAGE - Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage. | 08-05-2010 |
| 20100202206 | NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND CHANNELS AND METHODS OF FORMING THE SAME - A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device. | 08-12-2010 |
| 20100202207 | ALL-BIT-LINE ERASE VERIFY AND SOFT PROGRAM VERIFY - Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with bit lines and word lines. One or more non-negative compare voltages (e.g., zero volts) are applied to at least a portion of the word lines after applying the erase pulses. Conditions on the bit lines are sensed while holding differences between voltages on the bit lines substantially constant and while applying the one or more compare voltages. A determination is made whether the group is sufficiently erased based on the conditions. At least one additional erase pulse is applied to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased. | 08-12-2010 |
| 20100214839 | NAND FLASH MEMORY STRING APPARATUS AND METHODS OF OPERATION THEREOF - A NAND string, its operation, and manufacture is described herein. The NAND string includes one or more memory cells, a first selection transistor coupled to the memory cells, and a second selection transistor coupled between the memory cell and the first selection transistor, wherein the second selection transistor has a process defined threshold voltage. | 08-26-2010 |
| 20100214840 | MULTI-DOT FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME - A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical. | 08-26-2010 |
| 20100238730 | CONTROLLING SELECT GATE VOLTAGE DURING ERASE TO IMPROVE ENDURANCE IN NON-VOLATILE MEMORY - A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates float after being driven at a specific initial level, to reach a specific, optimal final level. In another approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage. In another approach, onset of select gate floating is delayed while the p-well voltage ramps up. In another approach, p-well voltage is ramped up in two steps, and the select gates are not floated until the second ramp begins. Floating can be achieved by raising the drive voltage to cut off pass gates of the select gates. | 09-23-2010 |
| 20100238731 | PARTIAL LOCAL SELF-BOOSTING OF A MEMORY CELL CHANNEL - A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage. | 09-23-2010 |
| 20100238732 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state. | 09-23-2010 |
| 20100238733 | NAND FLASH MEMORY - A NAND flash memory includes a NAND string and a control circuit, wherein in a write operation, the control circuit applies a writing voltage between a control gate of a selected memory cell to be written and a semiconductor well, and after the write operation and before performing a verification read operation of verifying whether data has been written into the selected memory cell, the control circuit performs a de-trapping operation, in which a first voltage of a same potential as that of the semiconductor well or a same polarity as that of the writing voltage is applied to the control gate of the selected memory cell and in which a second voltage of a same polarity as that of the writing voltage and larger than the first voltage as an absolute value is applied to a control gate of unselected memory cells not to be written. | 09-23-2010 |
| 20100254192 | MEMORY WITH CORRELATED RESISTANCE - Methods, systems, and devices are disclosed, such as a system for sequentially writing to a data locations coupled to one another in series. In certain embodiments, the system includes a plurality of data locations and a controller. The controller is configured to sequentially write data values to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location. | 10-07-2010 |
| 20100259987 | Two Pass Erase For Non-Volatile Storage - Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells' threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing. | 10-14-2010 |
| 20100259988 | OFFSET NON-VOLATILE STORAGE - A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements. | 10-14-2010 |
| 20100259989 | OFFSET NON-VOLATILE STORAGE - A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements. | 10-14-2010 |
| 20100259990 | MEMORY ARRAYS, MEMORY DEVICES AND METHODS OF READING MEMORY CELLS - Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional memory array architectures. Reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device. | 10-14-2010 |
| 20100265770 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory comprising: a first semiconductor layer having a first stripe-shaped region and a second stripe-shaped region which is adjacent to the first stripe-shaped region; a first NAND string formed on the first stripe-shaped region, the first NAND string having a plurality of first memory cell transistors connected in series; a first insulating film formed above the second stripe-shaped region; a second semiconductor layer formed on the first insulating film; and a second NAND string formed on the second semiconductor layer, the second NAND string having a plurality of second memory cell transistors connected in series. | 10-21-2010 |
| 20100271879 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a common voltage generating circuit which maintains a fixed voltage supply capability, and a plurality of voltage generating circuits which are disposed in accordance with a number of the plurality of planes, and a control circuit configured to control the power supply voltage generating circuit. | 10-28-2010 |
| 20100277983 | Two Pass Erase For Non-Volatile Storage - Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing. | 11-04-2010 |
| 20100315875 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME - Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings. | 12-16-2010 |
| 20100322005 | REDUCED PROGRAMMING PULSE WIDTH FOR ENHANCED CHANNEL BOOSTING IN NON-VOLATILE STORAGE - Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter duration, partway through the programming operation. A switchover point can be based on temperature, selected word line position and/or tracking of storage elements to a trigger state. The switchover point occurs sooner for higher temperatures, and for drain side word lines. The trigger state can be selected based on temperature. A portion of storage elements which are required to reach the trigger state to trigger a switchover can also be set a function of temperature. Programming pulses of a shorter duration improve channel boosting for inhibited storage elements, thereby reducing program disturb for these storage elements. | 12-23-2010 |
| 20100322006 | NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME - A memory cell string is disclosed. The memory cell string includes a first select gate that includes a first plurality of elements. A plurality of wordlines are coupled to the first select gate and a second select gate, that includes a second plurality of elements, is coupled to the plurality of wordlines. The distances between one element of the first and the second plurality of elements and the plurality of wordlines are the same as the distances that exist between each wordline of the plurality of wordlines. | 12-23-2010 |
| 20100329010 | READ OPERATION FOR MEMORY WITH COMPENSATION FOR COUPLING BASED ON WRITE-ERASE CYCLES - A read operation for non-storage elements compensates for floating gate-to-floating gate coupling and effects of program-erase cycles. During programming of a word line WLn+1, the threshold voltages of previously-programmed storage elements on WLn are increased due to coupling. To compensate for the increase, during a subsequent read operation of WLn, different sets of pass voltages are applied to WLn+1 for each control gate read voltage which is applied to WLn. The pass voltages vary in each different set so that they are a function of the control gate read voltage which is applied to WLn. The pass voltages may also be a function of a number of program-erase cycles. A higher amount of compensation is provided by increasing the pass voltages as the number of program-erase cycles increases. | 12-30-2010 |
| 20100329011 | MEMORY SYSTEM HAVING NAND-BASED NOR AND NAND FLASHES AND SRAM INTEGRATED IN ONE CHIP FOR HYBRID DATA, CODE AND CACHE STORAGE - A memory system includes a NAND flash memory, a NOR flash memory and a SRAM manufactured on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers. | 12-30-2010 |
| 20100329012 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second element regions having a rectangular bent portion and a pair of straight line portions connected to both ends of the bent portions, respectively. The pair of straight line portions extends in an opposite direction each other along a first direction. A first element region is arranged in parallel with the second element region so that the first and second element regions are isolated by an element isolation region, and the first and second bent portions are arranged along a second direction in which the first direction intersects with the second direction at an acute angle. A select gate line connected to select transistors extends in the second direction. A plurality of word lines connected to the memory cells are arranged in parallel with the select gate line in an opposite side of the bent portions with respect to the select gate line. | 12-30-2010 |
| 20110007568 | NAND TYPE ROM - The invention discloses a NAND type ROM. The NAND type ROM comprises a plurality of bit lines, a plurality of word lines, a first source line, a second source line, and a plurality of NAND strings. The bit lines comprise a plurality of upper bit lines, first lower and second lower bit lines. The first lower and second lower bit lines are alternately arranged in parallel, and the plurality of word lines are vertically arranged to each bit lines. The first and second source line are respectively connected to the plurality of first and second lower bit lines. The plurality of NAND strings comprise a plurality of first and second NAND strings. The first NAND strings are connected to the upper bit lines, word lines, and first lower bit lines. The second NAND strings are connected to the upper bit lines, word lines, and second lower bit lines. | 01-13-2011 |
| 20110007569 | CORRECTING FOR OVER PROGRAMMING NON-VOLATILE STORAGE - A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line). | 01-13-2011 |
| 20110013456 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE - According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines. | 01-20-2011 |
| 20110019478 | SENSING OF MEMORY CELLS IN NAND FLASH - An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (V | 01-27-2011 |
| 20110026327 | BIT-LINE CONNECTIONS FOR NON-VOLATILE STORAGE - Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One type of bit line connection may include a metal pad between an upper via and lower via. Another type of bit line connection may include an upper via and lower via, but does not include the metal pad. Three rows of bit line connections may be used to relax the pitch. For example, two rows of bit line connections on the outside may have the metal pad, whereas bit line connections in the middle row do not have the metal pad. | 02-03-2011 |
| 20110032764 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit ( | 02-10-2011 |
| 20110038211 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other. | 02-17-2011 |
| 20110044111 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING DATA IN NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES - The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both electrically separated from each other. In this mode, a write non-selection voltage applied to a non-selected memory cell next to the second selection gate transistor is switched, at least in two stages, between a lower voltage V | 02-24-2011 |
| 20110051517 | PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES - Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher. | 03-03-2011 |
| 20110051518 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device, in which flag data read of a flag data region is performed during data write, comprises: a nonvolatile memory cell array having an ordinary data region and the flag data region allocated to a one page range in which read and write are simultaneously performed; and a one page amount of sense amplifiers, each of the sense amplifiers comprising a data latch for retaining write data. During read of the flag data by the sense amplifier circuit, in the case of one of the sense amplifiers corresponding to the flag data region, read flag data is transferred to the data latch. In the case of one of the sense amplifiers corresponding to the ordinary data region, write data retained by the data latch is rewritten regardless of read cell data. | 03-03-2011 |
| 20110058423 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - In an embodiment, a semiconductor memory device including a cell array with NAND strings arranged therein, wherein the device has such a program mode that bit lines and cell's channels of the NAND strings coupled thereto are initially charged in accordance with program data, and then program voltage is applied to memory cells selected in the cell array. In the program mode, a certain bit line and a program-inhibited cell's channel coupled thereto, which are initially charged to Vdd, are boosted to be higher than Vdd by capacitive coupling from the cell source line prior to the program voltage application. | 03-10-2011 |
| 20110063915 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells capable electrically rewriting data, bit lines and source lines. A driver circuit is coupled with the source lines of the memory cell array to output a voltage higher than a power source voltage or a programming voltage for writing data in the memory cell by switching over, and the driver circuit discharges the source lines to ground. A sense amplifier circuit is coupled with the bit line and reads out the data in the memory cell. The sense amplifier includes a sense node and a capacitor having first and second terminals, and the first terminal is coupled with the sense node. The sense node is boosted by a plurality of voltages applied to the second terminal of the capacitor. | 03-17-2011 |
| 20110063916 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - At least some of the memory transistors included in a first memory string are commonly connected to first conductive layers that are connected to at least some of the memory transistors included in a second memory string connected to the same third and fourth conductive layers as the first memory string. At least one of either the memory transistors or the back-gate transistor in the first memory string and at least one of either the memory transistors or the back-gate transistor in the second memory string are connected to the independent first or fifth conductive layers, respectively. | 03-17-2011 |
| 20110063917 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line. | 03-17-2011 |
| 20110075484 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM EMPLOYING SAME - A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode. | 03-31-2011 |
| 20110075485 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to one aspect of the present invention includes a plurality of sense amplifier circuit that are configured to carry out a plurality of read cycles on a plurality of bit lines connected to those memory cells that are selected by a selected one of the word lines. During the second and subsequent read cycles, supply of a read current is ceased to those bit lines when it is determined in the preceding read cycle that a current not less than a certain determination current level flows therethrough, and the read current is supplied only to the remaining bit lines. A setup time of the bit lines in the first read cycle is set shorter than a setup time of the bit lines in the second and subsequent read cycles. | 03-31-2011 |
| 20110090738 | NAND FLASH MEMORY DEVICE HAVING DUMMY MEMORY CELLS AND METHODS OF OPERATING SAME - A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith. | 04-21-2011 |
| 20110096604 | SEMICONDUCTOR MEMORY DEVICE INCLUDING ALTERNATELY ARRANGED CONTACT MEMBERS - According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer contact members. First metal wirings are provided on the first upper-layer contact members. Second metal wirings are provided on the plugs. A height of a top surface of the plugs is higher than a top surface of the first metal wirings. A width of a bottom surface of the first metal wirings in a shorter-side direction is shorter than a width of a top surface of the first metal wirings. A width of a bottom surface of the second metal wirings in a shorter-side direction is shorter than a width of a top surface of the second metal wirings. | 04-28-2011 |
| 20110096605 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell. | 04-28-2011 |
| 20110103147 | NAND FLASH MEMORY DEVICES HAVING WIRING WITH INTEGRALLY-FORMED CONTACT PADS AND DUMMY LINES AND METHODS OF MANUFACTURING THE SAME - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 05-05-2011 |
| 20110110158 | MASS STORAGE DEVICE WITH SOLID-STATE MEMORY COMPONENTS CAPABLE OF INCREASED ENDURANCE - A mass storage device that utilizes one or more solid-state memory components to store data for a host system, and a method for increasing the write endurance of the memory components. The memory components are periodically heated above an intrinsic operating temperature thereof to a preselected temperature that is sufficient to thermally recondition the memory component in a manner that increases the write endurance of the memory component. | 05-12-2011 |
| 20110110159 | Nonvolatile Memory Device for Preventing Program Disturbance and Method of Programming the Nonvolatile Memory Device - A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected to even word lines and odd word lines. After a program verification, the word line driver drives the even word lines with a first voltage and then the odd word lines with the first voltage to drop the even word line to a voltage lower than the first voltage. The well bias control unit floats a bias of a p-well formed by high voltage NMOS transistors that apply corresponding driving voltages to the even word lines and the odd word lines according to an operation mode of a program operation, a read operation, and an erase operation. | 05-12-2011 |
| 20110141814 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, in a nonvolatile semiconductor memory device, a data latch circuit which is connected to a sense amplifier circuit controls a data writing operation and a data reading operation to and from a nonvolatile memory cell array through a data bus, and outputs the stored data to the data bus when the sense amplifier circuit performs the data writing operation. The data latch circuit is provided with two nodes respectively storing and outputting normal data and reverse data which are connected to the data bus. | 06-16-2011 |
| 20110149654 | NAND Programming Technique - A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS | 06-23-2011 |
| 20110149655 | Non-volatile memory cell array - A non-volatile microelectronic memory that has a memory cell array, which includes memory cell string pairs that share a bitline contact, that have separate source lines, and that have at least two transistors within each memory cell string that may be programming for sharing the bitline contact. | 06-23-2011 |
| 20110157989 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A control circuit is configured to erase a selected block in the erase operation by applying a predetermined potential to the source-line and the third conductive layer to generate a current to increase a potential of the first columnar semiconductor layer and by providing a first voltage to the first conductive layer. The control circuit is configured to keep first conductive layers at a floating state during the first period, while during the second period after the first period, to switch the first conductive layers from the floating state to a state in which the conductive layer is charged to a second voltage higher than the first voltage, in an unselected block in the erase operation. | 06-30-2011 |
| 20110157990 | CONTROL DEVICE FOR NONVOLATILE MEMORY AND METHOD OF OPERATING CONTROL DEVICE - A device comprises a nonvolatile memory cell array, a buffer circuit, a program control circuit, and a read control circuit. The nonvolatile memory cell array comprises a plurality of memory cells. The program control circuit stores program data in the buffer circuit. The read control circuit reads data from a selected address of the nonvolatile memory cell array. The program control circuit compares the program data with the read data, and sets a bit of the program data as a program-inhibit bit based on the comparison. | 06-30-2011 |
| 20110164451 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE FUSE - A semiconductor integrated circuit comprises a plurality of fuses arranged to be spaced apart from one another by predetermined intervals, and a page buffer electrically connected to the plurality of fuses and configured to determine whether to disconnect the fuses. The fuses comprise a NAND flash string. The NAND flash string comprises a drain select transistor connected to a bit line, a flash memory cell electrically connected to the drain select transistor, and a source select transistor connected between the flash memory cell and a ground terminal. | 07-07-2011 |
| 20110170352 | NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES - A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost. | 07-14-2011 |
| 20110176366 | SEMICONDUCTOR STORAGE DEVICE AND READING METHOD THEREOF - An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common source line. The SEN node is configured to be able to be electrically connected to a voltage source and the bit line. In the capacitor, one end is connected to the SEN node while the other end is connected to a CLK node to which a voltage within a predetermined range is applied. A discharge rate of the SEN node is enhanced by decreasing a capacitance during discharge of the SEN node only when a selected memory cell selected from the plural memory cells is an on-cell. | 07-21-2011 |
| 20110176367 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines; bit lines; and a control circuit configured to write multi-value data in the memory cells. The control circuit sets either even-ordinal-number bit lines or odd-ordinal-number bit lines as selected bit lines while setting the other as unselected bit lines; applies a write inhibiting voltage to the unselected bit lines; applies a write voltage to the selected bit lines corresponding to unwritten memory cells to be given one of threshold voltage distributions representing different written states; and applies the write inhibiting voltage to the selected bit lines corresponding to unwritten memory cells to be given any other of the threshold voltage distributions representing the different written states, memory cells already written, and memory cells to be maintained in a threshold voltage distribution representing an erased state, thereby executing a write operation. | 07-21-2011 |
| 20110188312 | METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells. | 08-04-2011 |
| 20110188313 | DATA RETENTION OF LAST WORD LINE OF NON-VOLATILE MEMORY ARRAYS - Techniques for operating non-volatile storage compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on different word lines. An erase of a group of non-volatile storage elements is performed. A set of the non-volatile storage elements are for storing data and at least one of the non-volatile storage elements is a dummy that is not for storing data. The dummy is a neighbor to one of the data non-volatile storage elements. The data non-volatile storage elements are programmed at some point after the erase. Then, a programming voltage is applied to the dummy non-volatile storage element to increase the threshold voltage of the dummy to cause floating gate coupling effect to the neighbor non-volatile storage element to compensate for lesser floating gate coupling effect that the neighbor experienced during programming. | 08-04-2011 |
| 20110194350 | COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE - In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation. | 08-11-2011 |
| 20110194351 | SOURCE SIDE ASYMMETRICAL PRECHARGE PROGRAMMING SCHEME - A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell. | 08-11-2011 |
| 20110199828 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING SAME - A nonvolatile memory device comprises a bulk region and a plurality of memory cells connected to a source line and a plurality of wordlines. The method comprises applying a source line voltage to the source line with a first magnitude, applying a bulk voltage to the bulk region with a second magnitude lower than the first magnitude, and performing access operations on the plurality of memory cells while maintaining a substantially constant difference between the bulk voltage and the source line voltage. | 08-18-2011 |
| 20110199829 | Nonvolatile Memory Device, Programming Method Thereof And Memory System Including The Same - Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages. | 08-18-2011 |
| 20110205800 | MEMORY DEVICES HAVING STRINGS OF SERIES-COUPLED MEMORY CELLS SELECTIVELY COUPLED TO DIFFERENT BIT LINES - Memory devices where ends of series-coupled strings of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device or by using one bit line as a ground node for sensing current flow through the strings. The use of bit lines for virtual grounding is further suitable to other array architectures. | 08-25-2011 |
| 20110222346 | NAND-TYPE FLASH MEMORY - A NAND-type flash memory has a bit line; a source line; and a NAND string that is configured by connecting a plurality of memory cells, into which data can be electrically rewritable, in series. The NAND-type flash memory has a drain-side selection gate transistor that has a gate to which a drain-side selection gate line is connected and that is connected between one end of the NAND string and the bit line; and a source-side selection gate transistor that has a gate to which a source-side selection gate line is connected and that is connected between the other end of the NAND string and the source line. The NAND-type flash memory has a row decoder that selects the memory cell by controlling voltages applied to control gates of the memory cells and that controls voltages applied to the drain-side selection gate line and the source-side selection gate line; and a bit line control circuit that controls a voltage of the bit line. | 09-15-2011 |
| 20110228609 | CORRECTING FOR OVER PROGRAMMING NON-VOLATILE STORAGE - A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line). | 09-22-2011 |
| 20110235420 | SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE - Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time. | 09-29-2011 |
| 20110235421 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer. | 09-29-2011 |
| 20110235422 | APPARATUS HAVING A STRING OF MEMORY CELLS - Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target voltage compensating, at least in part, for a voltage drop across any unselected memory cells in the string on a source side of the selected memory cell during a sensing operation. Some apparatus have circuitry configured to maintain a resistance presented by source-side unselected memory cells of the string the same between a program verify operation and a later read operation. | 09-29-2011 |
| 20110235423 | VERIFICATION PROCESS FOR NON-VOLATILE STORAGE - When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements. | 09-29-2011 |
| 20110235424 | HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY - Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground. | 09-29-2011 |
| 20110242892 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage. | 10-06-2011 |
| 20110261621 | PROGRAMMING AND SELECTIVELY ERASING NON-VOLATILE STORAGE - A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data. | 10-27-2011 |
| 20110267887 | Reducing Energy Consumption When Applying Body Bias To Substrate Having Sets Of Nand Strings - Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage. | 11-03-2011 |
| 20110267888 | Controlling Select Gate Voltage During Erase To Improve Endurance In Non-Volatile Memory - A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage. | 11-03-2011 |
| 20110280075 | MEMORY DEVICE AND OPERATING METHOD THEREOF - The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory cells and at least a string selection transistor. The common word lines are configured above the semiconductor layers, wherein each common word line is coupled to the memory cells arranged in a same row of the semiconductor layers. The common bit lines are configured on the common word lines, wherein each common bit line is coupled to a first ends of the NAND strings arranged in the same column of the semiconductor layers. The common source line is configured on the common word lines and coupled to a second ends of the NAND strings of the semiconductor layers. | 11-17-2011 |
| 20110280076 | JUNCTIONLESS TFT NAND FLASH MEMORY - A non-volatile memory device includes at least one junctionless transistor and a storage region. The junctionless transistor includes a junctionless, heavily doped semiconductor channel having two dimensions less than 100 nm. | 11-17-2011 |
| 20110286274 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line. | 11-24-2011 |
| 20110286275 | Stacked Memory Devices And Method Of Manufacturing The Same - A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of string selection pads. The memory string may include a plurality of memory strings arranged in a matrix and each of the memory strings may include a plurality of memory cells and a string selection device arranged perpendicular to a substrate. The plurality of bit lines may extend in a first direction and may be connected to ends of the plurality of memory strings. The plurality of string selection pads may be arrayed in a single line along the first direction and may be connected to the string selection devices included in the plurality of memory strings. | 11-24-2011 |
| 20110292731 | Three-Dimensional Non-Volatile Memory Devices Having Highly Integrated String Selection and Sense Amplifier Circuits Therein - Nonvolatile memory devices include an electrically insulating layer on a semiconductor substrate and a NAND-type string of nonvolatile memory cells on an upper surface of the electrically insulating layer. The NAND-type string of nonvolatile memory cells includes a plurality of vertically-stacked nonvolatile memory cell sub-strings disposed at side-by-side locations on the electrically insulating layer. A string selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate. A ground selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate. | 12-01-2011 |
| 20110292732 | NAND MEMORY DEVICE AND PROGRAMMING METHODS - A NAND Flash memory device reduces circuitry noise during program operations. The memory includes bit lines that are electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines. A NAND flash cell is programmed by coupling a first memory array bit line to a program voltage to program the memory cell, biasing a second memory array bit line to a ground potential, wherein the second memory array bit line is located adjacent to the first memory array bit line, activating at least one first transistor to electrically coupling the first and second memory array bit lines together, and activating at least one second transistor to electrically couple the first and second memory array bit lines to a discharge potential. | 12-01-2011 |
| 20110305089 | THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS - According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant. | 12-15-2011 |
| 20110310670 | VERTICALLY-INTEGRATED NONVOLATILE MEMORY DEVICES HAVING LATERALLY-INTEGRATED GROUND SELECT TRANSISTORS - Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines. | 12-22-2011 |
| 20120002477 | MEMORIES AND THEIR FORMATION - Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a first data line is selectively coupled to the first memory cells at the first and second vertical levels, and a second data line over the first data line is selectively coupled to the second memory cells at the first and second vertical levels. | 01-05-2012 |
| 20120002478 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases. | 01-05-2012 |
| 20120008399 | METHODS OF OPERATING MEMORIES INCLUDING CHARACTERIZING MEMORY CELL SIGNAL LINES - Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC time constant of the memory cell signal line. | 01-12-2012 |
| 20120020161 | Multiple Plane, Non-Volatile Memory With Synchronized Control - This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the “program phase” and the “verify phase” of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution. | 01-26-2012 |
| 20120057407 | CACHING SCHEME SYNERGY FOR EXTENT MIGRATION BETWEEN TIERS OF A STORAGE SYSTEM AND METHODS THEREOF - A storage system according to one embodiment includes logic adapted for determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system, wherein a set of tracks of the extent is presently being accessed; logic adapted for determining whether any track from the set of tracks is presently being written to; logic adapted for designating to a write-stack associated with the source-tier each track that is presently being written to and designating to a read-stack associated with the source-tier remaining tracks from the set of tracks; logic adapted for removing oldest tracks from the read-stack and the write-stack until the read-stack and the write-stack have been depleted of tracks; logic adapted for populating a destination-tier cache with the tracks as they are removed from the read-stack and the write-stack using a predetermined read-to-write ratio when a parameter of the extent exceeds a migration threshold; logic adapted for removing any tracks from a source-tier cache that were removed from the read-stack and the write-stack; and logic adapted for migrating the extent from the source-tier to the destination-tier. | 03-08-2012 |
| 20120069667 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SPEEDING UP DATA WRITE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array having a plurality of memory cells is connected to a plurality of word lines stacked on a semiconductor substrate, and the memory cells having a charge accumulation layer, and the charge accumulation layers are united between adjacent memory cells. When writing data to a memory cell group connected to the nth (n is a natural number) word line of the memory cell array, the control circuit controls to simultaneously apply the same program voltage to memory cell groups connected to the (n−1)th and (n+1)th word lines. | 03-22-2012 |
| 20120075931 | Techniques for the Fast Settling of Word Lines in NAND Flash Memory - In non-volatile memory devices, a write operation typically consists of an alternating set of pulse and verify operations. After a pulse is applied, the device must be biased properly for an accurate verify, with a selected word-line settled at the desired voltage level. The techniques described here address the problem of a relatively large waiting time at the start of a verify phase of a write operation when the selected word line is moving to its first verify level, while at the same time the non-selected word lines of a NAND type array are ramping up to a read pass level. For the non-selected word lines, during the program pulse, these are set at a first voltage above ground and then, during the verify operation, then are set at the read pass level. Rather than take the non-selected word lines to ground in between, they are instead moved directly from their voltage in the pulse phase directly into their read pass level. This helps to reduce the amount of movement in the selected word line due to capacitive coupling, allowing the preparation of the verify level of a selected word line settings earlier. | 03-29-2012 |
| 20120081963 | MULTI-STEP CHANNEL BOOSTING TO REDUCE CHANNEL TO FLOATING GATE COUPLING IN MEMORY - In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are subject to full channel boosting. Or, the boosting can be stepped up over multiple program-verify iterations after lockout. The amount of channel boosting can be set by adjusting the timing of a channel pre-charge operation and by stepping up pass voltages which are applied to unselected word lines. The reduced channel boosting can be implemented for a range of program-verify iterations where the lockout condition is most likely to be first reached, for one or more target data states. | 04-05-2012 |
| 20120081964 | SENSING FOR NAND MEMORY BASED ON WORD LINE POSITION - In a NAND non-volatile memory system, a sensing process accounts for a relative position of a selected non-volatile storage element in a NAND string. In one approach, the storage elements are assigned to groups based on their position, and each group receives a common sensing adjustment during a verify or read process. A group which is closest to a source side of the NAND string may be the largest of all the groups, having at least twice as many storage elements as the other groups. The adjusting can include adjusting a sensing parameter such as body bias, source voltage, sensing time or sensing pre-charge level, based on the position of the sensed storage element or its associated word line position. The adjusting of the sensing may also be based on the control gate voltage and the associated data state involved in a specific sensing operation. | 04-05-2012 |
| 20120081965 | METHOD OF EVALUATING A SEMICONDUCTOR STORAGE DEVICE - A method of evaluating a semiconductor storage device of a floating gate type has calculating an electron density distribution of a tunnel insulating film of a memory cell by multiplying a change rate of a threshold voltage Vt of the memory cell of the semiconductor storage device with respect to the change of the logarithm of a time with ε*Cr*2k/Tox/q (where ε is the permittivity of the tunnel insulating film of the memory cell, Cr indicates a coupling ratio of the memory cell, Tox indicates the thickness of the tunnel insulating film, k indicates an attenuation rate of the existence probability when the charges are detrapped and is represented as k=(2mE/(h/2π) | 04-05-2012 |
| 20120087190 | Write BIAS condition for 2T-string NOR flash cell - This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias conditions in cell array improves over the critical concern of punch-through issue when cell is migrating to the more advanced technology node of next generation. The invention adopts a novel preferable symmetrical 2T-string NOR flash cell. Each NAND or NAND like cell of this 2T-string NOR cell is to store 2 bits and is preferable to be made of N-channel device. The cell is preferable to use Fowler-Nordheim Tunneling scheme for both erase and program operations. The invention is to provide a novel 2T-string NOR flash cell structure made of N-channel device offering most flexible erase sizes in unit of byte, page, sector, block and chip with the least program and erase disturbances. | 04-12-2012 |
| 20120092931 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, threshold voltages of memory cells being set lowest in an erase state and sequentially set higher according to data in a program state, a plurality of bit lines connected to the memory cells, a word line connected to the memory cells, and a control circuit. In a case where a first memory cell is programmed to a first threshold voltage that is lowest among threshold voltages in the program state, the control circuit is configured to charge a first bit line connected to the first memory cell to a third voltage between a first voltage applied to a bit line when a memory cell is programmed to a second threshold voltage higher than the first threshold voltage and a second voltage applied to a bit line when a memory cell is inhibited from being programmed. | 04-19-2012 |
| 20120120727 | METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE - A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage. | 05-17-2012 |
| 20120127797 | SYSTEM AND METHOD FOR TESTING FOR DEFECTS IN A SEMICONDUCTOR MEMORY ARRAY - A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect. | 05-24-2012 |
| 20120134212 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment of the present invention includes: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells having a charge storage layer and a control electrode; and a control unit configured to execute a write cycle multiple times, the write cycle including a write operation and a write verify operation, the write operation being an operation for applying a write pulse voltage multiple times to the control electrode selected for data write, and the write verify operation being an operation for determining whether data write is completed or not. During one time of the write operation, the control unit makes a voltage value of a finally applied write pulse voltage larger than a voltage value of an initially applied write pulse voltage. | 05-31-2012 |
| 20120147675 | Nonvolatile Stacked Nand Memory - A NAND string of memory cells has stacks of split word lines (gates), with resulting increased bit density. Variants add a top assist gate to the NAND string, a bottom assist gate to the NAND string, or both a top assist gate and a bottom assist gate to the NAND string. | 06-14-2012 |
| 20120147676 | NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES CONNECTED TO SINGLE SELECTION DEVICE - A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. | 06-14-2012 |
| 20120155177 | STRUCTURES AND METHODS FOR READING OUT NON-VOLATILE MEMORY USING REFERENCING CELLS - The structures and methods of reading out semiconductor Non-Volatile Memory (NVM) using referencing cells are disclosed. The new invented scheme can reduce large current consumption from the direct current biasing in the conventional scheme and achieve a high resolution on the cell threshold voltage with a good sensing speed. | 06-21-2012 |
| 20120155178 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory, and a data transfer section configured to perform data transfer from and to the memory, and having a first mode to transfer data with a first bit width and a second mode to transfer data with a second bit width. The data transfer section includes a first latch circuit configured to hold first data read from the memory, a second latch circuit configured to hold second data having the first bit width of the first data in the first mode, and to hold third data having the second bit width of the first data in the second mode, and data bus connecting the first latch circuit to the second latch circuit and shared by the first and second modes. | 06-21-2012 |
| 20120155179 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array having memory cells, word lines connected to the memory cell array, a generation circuit configured to generate voltages required for operations of the memory cell array, selection circuits connected to the word lines, respectively, each of the selection circuits being configured to select a voltage applied to a word line from the voltages, and a transfer unit configured to transfer items of control data for selecting the voltage to the selection circuits, respectively. The transfer unit includes transfer circuits which shift an enable signal in sequence. The transfer circuits include latch circuits which hold the items of control data based on the shifted enable signal, respectively. | 06-21-2012 |
| 20120155180 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING A NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a plurality of page buffers coupled to the respective bitlines of the memory cell array, each page buffer including a latch configured to store data to be written into and read from a memory cell coupled to a respective bitline of the memory cell array. The memory device further includes a control circuit configured to execute an over-program verify operation which includes detecting an over-programmed memory cell among the plurality of memory cells with reference to pass/fail data stored in the respective latches of the plurality of page buffers, and decreasing a threshold voltage of a detected over-programmed memory cell while maintaining a threshold voltage of memory cells which have not been detected as being over-programmed. | 06-21-2012 |
| 20120163083 | ALTERNATE BIT LINE BIAS DURING PROGRAMMING TO REDUCE CHANNEL TO FLOATING GATE COUPLING IN MEMORY - In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse. A slow down measure such as an elevated bit line voltage is applied to the storage elements of a word line which are associated with odd-numbered bit lines, but not to the storage elements associated with even-numbered bit lines. The elevated bit line voltage is applied over a range of program pulses, then stepped down to ground over one or more program pulses. The range of programming pulses over which the slow down measure is applied, can be fixed or determined adaptively. A program pulse increment can be dropped, then increased, when the bit line voltage is stepped down. Storage elements which are programmed to a highest target data state can be excluded from the slow down measure. | 06-28-2012 |
| 20120170370 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM EMPLOYING SAME - A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode. | 07-05-2012 |
| 20120176841 | Flexible 2T-Based Fuzzy and Certain Matching Arrays - A novel NVM-based 2T or 2nT NAND-cell for a NAND-array for PLD, PAL and matching functions is disclosed. The preferable NVM cell can be ROM or Flash. The 2T flash cell preferably uses FN for both program and erase operation, while 2T ROM cell preferably to use phosphorus for ROM code implant to get negative Vt0. | 07-12-2012 |
| 20120182805 | STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME - Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed. | 07-19-2012 |
| 20120182806 | Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures - A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines. | 07-19-2012 |
| 20120206967 | PROGRAMMING AND SELECTIVELY ERASING NON-VOLATILE STORAGE - A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data. | 08-16-2012 |
| 20120206968 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line. | 08-16-2012 |
| 20120213006 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall film covers a side surface of a gate of the end memory cell and a side surface of a gate of the selective transistor between the end memory cell and the selective transistor. An air gap is provided between the sidewall film of the end memory cell and the sidewall film of the selective transistor, | 08-23-2012 |
| 20120218822 | CONTENT ADDRESSABLE MEMORY - NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics for low power and portable applications. In one NAND architecture non-volatile CAM memory embodiment a wired NOR match line array is utilized. In another embodiment a NAND match line array is shown. In yet other embodiments, hierarchal addressing, hash addressing, tree search and algorithmic/hardware engine based search is detailed utilizing both conventional NAND architecture non-volatile Flash memory arrays and dedicated NAND architecture CAM arrays utilizing wired NOR and wired NAND match lines. | 08-30-2012 |
| 20120236647 | HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY - Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground. | 09-20-2012 |
| 20120243317 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a non-volatile semiconductor memory device includes a writing unit that performs a writing operation on memory cells while stepping up a writing voltage based on a check result of a verifying operation on the memory cells, a threshold-value determining unit that determines threshold values of the memory cells based on a write verifying operation on the memory cells, and a step-up voltage changing unit that changes a step-up voltage for stepping up the writing voltage, based on the threshold values of the memory cells. | 09-27-2012 |
| 20120250414 | REDUCING NEIGHBOR READ DISTURB - Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn−2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1. | 10-04-2012 |
| 20120250415 | SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE - Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time. | 10-04-2012 |
| 20120275225 | Variable Resistance Switch Suitable for Supplying High Voltage to Drive Load - A circuit for supplying a high voltage to load is described. An example of such a circuit could be used in the peripheral circuitry of a non-volatile memory device for supplying a program voltage from a charge pump to a selected word line. The circuit includes a charge pump that generates the high voltage and decoding circuitry that is connected to receive this high voltage and selectively apply it to a load. The decoding circuitry receives the high voltage through a switch, where the switch is of a variable resistance that progressively passes the high voltage in response to a control signal. In a particular example, the switch includes a transistor connected between the charge pump and the decoding circuitry, where the control gate of the transistor is connected to the output of a second charge pump that is connected to receive the high voltage and a settable clock signal as its inputs. | 11-01-2012 |
| 20120275226 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING POWER CONSUMPTION - According to one embodiment, a nonvolatile semiconductor memory device includes an electrically rewritable nonvolatile memory, a grounding pad, a first power supply pad, a second power supply pad, a voltage reduction circuit, and a first pump circuit. A first power supply is supplied to the first power supply pad. A second power supply, a voltage of which is higher than that of the first power supply is supplied to the second power supply pad. The voltage reduction circuit reduces the second power supply, generates a first voltage lower than that of the second power supply, and supplies the first voltage to the nonvolatile memory. The first pump circuit generates a voltage higher than that of the second power supply on the basis of the first power supply, and supplies the second voltage to the nonvolatile memory. | 11-01-2012 |
| 20120275227 | PHOTOSENSITIVE COMPOSITION AND COMPOUND FOR USE IN THE PHOTOSENESITIVE COMPOSITION - A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages. | 11-01-2012 |
| 20120281475 | NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME - An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device. | 11-08-2012 |
| 20120287716 | Using Channel-To-Channel Coupling To Compensate Floating Gate-To-Floating Gate Coupling In Programming Of Non-Volatile Memory - In a non-volatile storage system, during a verify operation, a verify voltage of a currently-sensed target data state is applied to a selected word line. A higher, nominal bit line voltage is used for the storage elements which have the currently-sensed target data state and a verify status of pass or no pass, a target data state lower than the currently-sensed target data state and a verify status of pass or no pass, or a target data state higher than the currently-sensed target data state and a verify status of pass. A lower bit line voltage is used for the storage elements which have the target data state higher than the currently-sensed target data state and a verify status of no pass, to enhance channel-to-channel coupling, as an offset to floating gate-to-floating gate coupling which is later caused by these storage elements. | 11-15-2012 |
| 20120300550 | Ramping Pass Voltage To Enhance Channel Boost In Memory Device, With Optional Temperature Compensation - In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions. | 11-29-2012 |
| 20120300551 | NON-VOLATILE MEMORY CELL HEALING - Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string. | 11-29-2012 |
| 20120307561 | NON-VOLATILE MEMORY DEVICE AND METHOD CONTROLLING DUMMY WORD LINE VOLTAGE ACCORDING TO LOCATION OF SELECTED WORD LINE - A non-volatile memory device includes access circuitry that selects a word line during an operation, applies a selected word line voltage to the selected word line, applies a non-selected word line voltage to non-selected word lines among the word lines, and applies a dummy word line voltage to the dummy word line. The dummy word line voltage is a first dummy word line voltage when the selected word line is not adjacent to the dummy word line and a second dummy word line voltage different from the first dummy word line voltage when the selected word line is adjacent to the dummy word line. | 12-06-2012 |
| 20120327713 | IN-FIELD BLOCK RETIRING - Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed. | 12-27-2012 |
| 20120327714 | Memory Architecture of 3D Array With Diode in Memory String - Various embodiments are directed to 3D memory arrays that lack a select line and devices controlled by the select line between one of the source line and the bit line, and the memory cells. Diodes between the other of source line and the bit line, and the memory cells provide needed isolation from the memory cells. | 12-27-2012 |
| 20120327715 | NONVOLATILE MEMORY DEVICES HAVING VERTICALLY INTEGRATED NONVOLATILE MEMORY CELL SUB-STRINGS THEREIN - Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series. | 12-27-2012 |
| 20130003461 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE - According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines. | 01-03-2013 |
| 20130021848 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE THEREIN - A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell. | 01-24-2013 |
| 20130028021 | Simultaneous Sensing of Multiple Wordlines and Detection of NAND Failures - Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed. | 01-31-2013 |
| 20130044544 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a circuit and a memory cell. The circuit outputs a program voltage. The memory cell is programmed data by being applied the program voltage. The circuit outputs the program voltage so as to satisfy the following formulae, in the case of repeating an output of the program voltage n times (n is an integer not less than 3), when the program voltage in the k-th output (k is an integer not less than 2 and not greater than n) is set to Vpgm(k), a constant voltage is set as Δv | 02-21-2013 |
| 20130044545 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME - A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string. | 02-21-2013 |
| 20130070531 | SUBSTRATE BIAS DURING PROGRAM OF NON-VOLATILE STORAGE - A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up during the programming operation, and discharged after programming. Therefore, for operations such as verify and read, the substrate may be grounded. In one embodiment, the substrate is charged just prior to applying a program pulse, then discharged prior to a program verify operation. In one embodiment, the substrate is charged while unselected word lines are ramped up to a pass voltage. The substrate bias may depend on program voltage, temperature, and/or hot count. | 03-21-2013 |
| 20130077404 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, and applies a second read pass voltage to a second non-selected word line connected to a non-written memory cell. Each of the read voltages is set to a voltage between two threshold voltage distributions. The first read pass voltage is set so that the data-written memory cells become conductive. The second read pass voltage is set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages. | 03-28-2013 |
| 20130083601 | VERTICAL NAND MEMORY - A vertical NAND structure includes one or more mid-string devices having at least two functional modes. In the first mode, the one or more mid-string devices couple the bodies of stacks of NAND memory cells to the substrate for erase operations. In the second mode, the one or more mid-string devices couple the body of a first stack of NAND memory cells to a body of a second stack of memory NAND memory cells, allowing the two stacks operate as a single NAND string for read and programming operations. | 04-04-2013 |
| 20130083602 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a write control unit performs a condition verify operation of searching for a low level region and a high level region of memory cells, and sets a write voltage of the low level region and the high level region in common and individually sets bit line voltages of the low level region and the high level region in a write operation after the condition verify operation. | 04-04-2013 |
| 20130083603 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - One embodiment includes a write control unit that performs a first write operation with respect to a first threshold distribution, a first verify operation on the first threshold distribution, and a second write operation on the basis of a result of the first verify operation, and then starts a third write operation with respect to a second threshold distribution. | 04-04-2013 |
| 20130088920 | LOW VOLTAGE PROGRAMMING IN NAND FLASH WITH TWO STAGE SOURCE SIDE BIAS - A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The program operation is based on metering a flow of carriers between a first semiconductor body region on a first side of the selected cell in the NAND string and a second semiconductor body region on a second side of the selected cell. A program potential higher than a hot carrier injection barrier level is applied to the selected cell, and then the drain to source voltage across the selected cell and the flow of carriers in the selected cell reach a level sufficient to support hot carrier injection, which is controlled by a combination of a switch cell adjacent the selected cell and modulation of a source side voltage applied to the NAND string. | 04-11-2013 |
| 20130088921 | OPERATING METHOD OF NONVOLATILE MEMORY AND METHOD OF CONTROLLING NONVOLATILE MEMORY - An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation. | 04-11-2013 |
| 20130107628 | Selective Word Line Erase In 3D Non-Volatile Memory | 05-02-2013 |
| 20130107629 | NONVOLATILE MEMORY DEVICES AND OPERATING METHODS THEREOF | 05-02-2013 |
| 20130114342 | DEFECTIVE WORD LINE DETECTION - Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line. | 05-09-2013 |
| 20130121079 | NOR FLAH MEMORY CELL AND STRUCTURE THEREOF - The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a first transistor, a second transistor and at least one third transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal used to receive a word line signal and the first terminal used to receive a bit line signal. A gate of the first transistor comprises a silicon-rich nitride layer and an oxide layer, wherein the silicon-rich nitride layer is buried in the oxide layer. A control terminal of the second transistor used to receive a read signal. A second terminal of the second transistor used to transport a source line signal according to the read signal. The third transistor coupled between the first transistor and the bit line signal, and a control terminal of the third transistor receives a midway control signal. | 05-16-2013 |
| 20130128669 | OPERATION FOR NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES - A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential. | 05-23-2013 |
| 20130141977 | Page Buffer Circuit - A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data. | 06-06-2013 |
| 20130148427 | Z-Direction Decoding for Three Dimensional Memory Array - The switch transistors in the NAND strings have combinations of threshold voltage levels that vary across the levels of a three dimensional memory array. A bias arrangement is applied to the select lines electrically coupled to the switch transistors. The NAND strings on a particular level of a three dimensional memory array are selected. The NAND strings on other levels are deselected. | 06-13-2013 |
| 20130163336 | Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory - An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles. | 06-27-2013 |
| 20130163337 | Erase Inhibit For 3D Non-Volatile Memory - An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the remaining NAND strings is performed. The two-sided erase charges up the body of a NAND string from the source-side and drain-side ends, while the one-sided erase charges up the body of the NAND string from the drain-side end. The NAND strings associated with one bit line form a set. The switch to the one-sided erase can occur when the set meets a set erase-verify condition, such as one, all, or some specified portion of the NAND strings of the set passing the erase-verify test. The erase operation can end when no more than a specified number of NAND strings have not met the erase-verify test. As a result, erase degradation of the memory cells is reduced. | 06-27-2013 |
| 20130163338 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - Provided is a non-volatile semiconductor storage device including: a memory cell array where memory cells are arranged in a matrix shape; and a control unit which erases the memory cell by applying an erasing voltage to a well side of the memory cell and preliminarily erases the memory cell by applying a preliminary erasing voltage to the well side of the memory cell before the erasing while applying a voltage, which is higher than the voltage during the erasing, to a control gate electrode of the memory cell. | 06-27-2013 |
| 20130170300 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. | 07-04-2013 |
| 20130182505 | FLASH PROGRAMMING TECHNOLOGY FOR IMPROVED MARGIN AND INHIBITING DISTURBANCE - A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a program bias pulse by biasing the bit lines and string select lines in a first condition; setting a word line coupled to a target cell to a first voltage level while the bit lines and string select lines are in the first condition; thereafter, biasing the bit lines and string select lines in a second condition; and setting the word line coupled to the target cell to a second voltage level higher than the first voltage level while the bit lines and string select lines are in the second condition. Program bias pulses produced in this manner can be used in a modulated incremental stepped pulse programming sequence. | 07-18-2013 |
| 20130188423 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - According to example embodiments of inventive concepts, a nonvolatile memory device includes a first NAND string and a second NAND string. The first NAND string include a first string selection transistor, a first ground selection transistor having a threshold voltage higher than a threshold voltage of the first string selection transistor, and first memory cells stacked on a substrate. The a second NAND string includes a second string selection transistor, a second ground selection transistor having a threshold voltage higher than a threshold voltage of the second string selection transistor, and second memory cells stacked on the substrate. A first selection line may connect the first string selection line and the first ground selection line, and a second selection line may connect the second selection line and the second ground selection line. The first and second selection lines may be electrically isolated from each other. | 07-25-2013 |
| 20130194871 | NAND FLASH MEMORY UNIT, NAND FLASH MEMORY ARRAY, AND METHODS FOR OPERATING THEM - A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor. | 08-01-2013 |
| 20130194872 | NON-VOLATILE MEMORY DEVICE AND READ METHOD THEREOF - Disclosed is a nonvolatile memory device which includes a memory cell connected to a bit line and a word line; a page buffer electrically connected to the bit line and sensing data stored in the memory cell; and a control logic controlling the page buffer to vary a develop time of the bit line or a sensing node connected to the bit line according to a current temperature during a read operation. | 08-01-2013 |
| 20130201760 | Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory - A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non-conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling. | 08-08-2013 |
| 20130201761 | SENSE AMPLIFIER FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a comparator. The sensing voltage generator outputs a sensing voltage to a sensing node depending on a current flowing through a data line. A load transistor supplying a current to the data line is directly connected to a clamping node. The load transistor is included in a current mirror circuit. In a read operation, a low voltage drive operation is performed and a sensing speed and power consumption are properly controlled. | 08-08-2013 |
| 20130201762 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a control circuit of a memory cell array is configured to write data to a memory cell array by applying a first write pass voltage, which is lower than the program voltage, to a first group of nonselective word lines adjacent to a selective word line. The control circuit is further configured to apply a second write pass voltage, which is higher than the first write pass voltage, to a second group of second nonselective word lines, the second group not including the word lines of the first group. | 08-08-2013 |
| 20130215679 | NONVOLATILE MEMORY DEVICE AND A METHOD OF ADJUSTING A THRESHOLD VOLTAGE OF A GROUND SELECTION TRANSISTOR THEREOF - A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation. The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate. | 08-22-2013 |
| 20130223150 | APPARATUS AND METHODS FOR APPLYING A NON-ZERO VOLTAGE DIFFERENTIAL ACROSS A MEMORY CELL NOT INVOLVED IN AN ACCESS OPERATION - Apparatus and methods for applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data retention characteristics. | 08-29-2013 |
| 20130229873 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number| 09-05-2013 | |
| 20130235666 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACURING THE SAME - A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written. | 09-12-2013 |
| 20130235667 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A method is provided for programming a nonvolatile memory device, which includes multiple memory cells connected in series in a direction substantially perpendicular to a substrate. The method includes programming a first memory cell of the multiple memory cells, and programming a second memory cell of the multiple memory cells after the first memory cell is programmed, the second memory cell being closer to the substrate than the first memory cell. A diameter of a channel hole of the first memory cell is larger than a diameter of a channel hole of the second memory cell. | 09-12-2013 |
| 20130235668 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 09-12-2013 |
| 20130242660 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, in a write control unit that performs writing on a selected memory cell connected to a selected word line by making to apply a program voltage to the selected word line while making to apply an intermediate voltage to unselected word lines, an isolation voltage is controlled to be applied to any word line of the unselected word lines at a time of applying the program voltage and the isolation voltage is controlled to increase before the intermediate voltage is removed after applying the program voltage. | 09-19-2013 |
| 20130242661 | NON-VOLATILE STORAGE WITH READ PROCESS THAT REDUCES DISTURB - A apparatus and process for reading data from non-volatile storage includes applying a read compare signal to a selected data memory cell of a NAND string, applying a first set of one or more read pass voltages to unselected data memory cells at both ends of the NAND string and applying a second set of one or more read pass voltages to unselected data memory cells between both ends of the NAND string and on both sides of the selected data memory cell. The second set of one or more read pass voltages are all higher than the first set of one or more read pass voltages. | 09-19-2013 |
| 20130242662 | METHOD FOR DRIVING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device has source/drain diffusion layers spaced from each other in a surface portion of a semiconductor substrate, a laminated insulating film formed on a channel between the source/drain diffusion layers and including a charge storage layer, and a gate electrode formed on the laminated insulating film, the nonvolatile semiconductor memory device changing its data memory state by injection of charges into the charge storage layer. The method includes, before injecting charges to change the data memory state into the charge storage layer: injecting charges having a polarity identical to that of the charges to be injected; and further injecting charges having a polarity opposite to that of the injected charges. | 09-19-2013 |
| 20130250687 | SHARED-BIT-LINE BIT LINE SETUP SCHEME - Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings, wherein each pair of the one or more pairs of NAND strings shares a common bit line. In some embodiments, a pair of NAND strings includes an odd NAND string adjacent to an even NAND string. Prior to programming a memory cell associated with the even NAND string, an odd channel associated with the odd NAND string (i.e., the NAND string of the pair that is not selected for programming) is precharged to a bit line inhibit voltage, floated, and then boosted to a second voltage greater than the bit line inhibit voltage as an even channel associated with the even NAND string is precharged. Subsequently, the odd channel may be boosted (e.g., via self-boosting) prior to programming the memory cell. | 09-26-2013 |
| 20130250688 | SELECTED WORD LINE DEPENDENT PROGRAMMING VOLTAGE - Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines. | 09-26-2013 |
| 20130250689 | SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMMING - Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction. | 09-26-2013 |
| 20130250690 | SELECTED WORD LINE DEPENDENT SELECT GATE VOLTAGE DURING PROGRAM - Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines. | 09-26-2013 |
| 20130250691 | METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE - A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage. | 09-26-2013 |
| 20130258780 | METHOD OF PROGRAMMING SELECTION TRANSISTORS FOR NAND FLASH MEMORY - Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition. | 10-03-2013 |
| 20130258781 | MEMORY DEVICES AND BIASING METHODS FOR MEMORY DEVICES - Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells. | 10-03-2013 |
| 20130258782 | CONFIGURATION MEMORY - According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node. | 10-03-2013 |
| 20130265826 | MEMORY SYSTEM AND OPERATING METHOD OF CONTROLLER - A memory system including a first memory of a first type; a second memory of a second type; and a controller configured to control the first memory and the second memory. The first type and second type are different, and the controller is configured to control the first memory and the second memory according to substantially the same command sequence. | 10-10-2013 |
| 20130272069 | 3D NON-VOLATILE STORAGE WITH TRANSISTOR DECODING STRUCTURE - Disclosed herein are 3D stacked memory devices having WL select gates. The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors. 3D decoding may be provided in a 3D stacked memory device using the WL select gates. | 10-17-2013 |
| 20130279256 | Soft Erase Operation For 3D Non-Volatile Memory With Selective Inhibiting Of Passed Bits - An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits. | 10-24-2013 |
| 20130279257 | Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current - An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively. | 10-24-2013 |
| 20130279258 | PROGRAM CONDITION DEPENDENT BIT LINE CHARGE RATE - Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may be completion of a program loop. As another example, the program condition may be a certain program state completing or nearly completing programming. As one example, the bit lines may be charged at a faster rate prior to the program condition occurring than after the program condition. As another example, the bit lines may be charged at a slower rate prior to the program condition than after the program condition. Charging the unselected bit lines at a slower rate may reduce current consumption. Charging the unselected bit lines at a faster rate may allow for faster programming. | 10-24-2013 |
| 20130286738 | SEMICONDUCTOR MEMORY APPARATUS - According to one embodiment, a semiconductor memory apparatus includes an array, a source, a bit line, a sense, and current circuit. The array includes a NAND string. The NAND string includes memory cell. The sense includes a first transistor. One end of transistor is connected to a first node, and other end of the transistor is connected to a second. The first node is used for reading the data held by the memory cell. An internal voltage is smaller than the source voltage. The current circuit outputs a first voltage to a gate of the transistor, and the first voltage is smaller than the internal voltage. The transistor limits a first current from the source to the sense based on a threshold voltage of the memory cell to be read. | 10-31-2013 |
| 20130286739 | METHODS OF READING MEMORY CELLS - Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional memory array architectures. Reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device. | 10-31-2013 |
| 20130294165 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND CONTROL METHOD THEREOF - A semiconductor memory device includes first cell strings connected to first bit lines and second cell strings connected to second bit lines corresponding to the first bit lines, respectively. Data is stored in memory cells of the first cell strings, and the second cell strings are configured as a data non-storage region. At least one memory cell of each of the second cell strings is in a programmed state. | 11-07-2013 |
| 20130294166 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A non-volatile memory device and a method for driving the same are disclosed. During a precharge operation, the bit line is precharged on the basis of a voltage applied to a common source line. The bit line is precharged or not precharged based on whether or not a selected memory cell is in an erased state or a program state. | 11-07-2013 |
| 20130294167 | Erase Inhibit For 3D Non-Volatile Memory - An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the remaining NAND strings is performed. The two-sided erase charges up the body of a NAND string from the source-side and drain-side ends, while the one-sided erase charges up the body of the NAND string from the drain-side end. The NAND strings associated with one bit line form a set. The switch to the one-sided erase can occur when the set meets a set erase-verify condition, such as one, all, or some specified portion of the NAND strings of the set passing the erase-verify test. The erase operation can end when no more than a specified number of NAND strings have not met the erase-verify test. As a result, erase degradation of the memory cells is reduced. | 11-07-2013 |
| 20130294168 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings that shares a plurality of word lines connected to a plurality of memory cells, respectively. The memory region is disposed to one of the plurality of physical blocks. Each of the plurality of string units configures a first logical block, and when the first logical block is failed, information of the first failed logical block is stored in a first region of the memory region. | 11-07-2013 |
| 20130294169 | SIMULTANEOUS MULTI-LEVEL BINARY SEARCH IN NON-VOLATILE STORAGE - Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time. A binary search may be performed. | 11-07-2013 |
| 20130308385 | APPARATUSES AND METHODS FOR COUPLING LOAD CURRENT TO A COMMON SOURCE - Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described. | 11-21-2013 |
| 20130308386 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage; set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the first and second voltages being different; apply in the selected and unselected cell units a third voltage to a gate of at least one of dummy transistors in a dummy memory string; and apply a fourth voltage to a gate of another one of the dummy transistors in the dummy memory string, the fourth voltage being lower than the third voltage. | 11-21-2013 |
| 20130314995 | Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory - A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate. | 11-28-2013 |
| 20130314996 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a cell well in a row direction and a column direction in a matrix; word lines which select the memory cell in the row direction; bit lines which select the memory cell in the column direction; a sense amplifier which determines a value stored in the memory cell based on a potential of the bit line; a peripheral transistor in the memory cell array which is arranged in the periphery of the memory cell array; and an enhancement type transistor which drives a gate of the peripheral transistor. | 11-28-2013 |
| 20130314997 | Memory Access Method and Flash Memory Using the Same - A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase. | 11-28-2013 |
| 20130322177 | INTEGRATED CIRCUIT AND APPARATUSES INCLUDING THE SAME - An integrated includes a memory cell, a bit line connected to the memory cell, a boosting circuit to boost the bit line up to a boosting voltage during a pre-charge operation pre-charging the bit line, and a regulation circuit connected between the bit line and an output terminal and determines a logic level of the output terminal according to the voltage of the bit line. | 12-05-2013 |
| 20130322178 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a second dummy hookup transistor connected to second dummy word line. A group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistor, and the second dummy hookup transistor is aligned on either of one row and rows. The first dummy hookup transistor and the second dummy hookup transistor are arranged at least at one end of the group of hookup transistors. | 12-05-2013 |
| 20130322179 | HOT CARRIER PROGRAMMING IN NAND FLASH - A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field. Boosted channel hot carrier injection can be based on blocking flow of carriers between a first side of a selected cell and a second side of the selected cell in the NAND string, boosting by capacitive coupling the first semiconductor body region to a boosted voltage level, biasing the second semiconductor body region to a reference voltage level, applying a program potential greater than a hot carrier injection barrier level to the selected cell and enabling flow of carriers from the second semiconductor body region to the selected cell to cause generation of hot carriers. | 12-05-2013 |
| 20130329499 | MEMORY CELL STRING BASED ON GATED-DIODE CELL AND MEMORY ARRAY USING THE SAME - The present invention provides a nonvolatile memory cell string and a memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins and a memory cell string formed with memory cells having a gated diode structure along each fin are enabled to increase the degree of integration and basically prevent the interferences between adjacent cells. And a first semiconductor layer and a depletion region of a PN junction wrapped up by a gate electrode are enabled to remove GSL and CSL by GIDL memory operation and significantly increase the degree of integration for applying to a neuromorphic technology. | 12-12-2013 |
| 20130329500 | NONVOLATILE MEMORY DEVICE, ERASING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate. | 12-12-2013 |
| 20130336065 | ARCHITECTURE FOR 3-D NAND MEMORY - Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area. | 12-19-2013 |
| 20130343129 | EXTENDED SELECT GATE LIFETIME - A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command. | 12-26-2013 |
| 20130343130 | NAND FLASH BIASING OPERATION - A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation. | 12-26-2013 |
| 20140003148 | THREE DIMENSIONAL NAND FLASH WITH SELF-ALIGNED SELECT GATE | 01-02-2014 |
| 20140003149 | SEMICONDUCTOR STORAGE DEVICE | 01-02-2014 |
| 20140003150 | SYSTEM TO REDUCE STRESS ON WORD LINE SELECT TRANSISTOR DURING ERASE OPERATION | 01-02-2014 |
| 20140003151 | SELECT GATE PROGRAMMING IN A MEMORY DEVICE | 01-02-2014 |
| 20140022847 | NAND FLASH MEMORY PROGRAMMING - A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described. | 01-23-2014 |
| 20140029343 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array including memory cell transistors configured to store information in accordance with n (n is an integer larger than 2) threshold voltage levels, and a control circuit configured to control the memory cell array. In a write operation, the control circuit shifts a threshold voltage level of a write target memory cell transistor to a base threshold level of the n threshold levels, except for a threshold level having a highest voltage and a threshold level having a lowest voltage. Then the control circuit shifts the threshold voltage level of the write target memory cell transistor from the base threshold level to one of the n threshold levels. | 01-30-2014 |
| 20140029344 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages. | 01-30-2014 |
| 20140036592 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has a memory cell array including memory cells and a plurality of redundancy regions arranged in a first direction including flag cells, plural word lines extending in the first direction, and plural bit lines extending in a second direction crossing the first direction, and a controller configured to control writing of data to the memory cells and also to the flag cells. | 02-06-2014 |
| 20140043909 | WRITING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a writing method. The method includes setting potentials of a plurality of word lines to a first potential. The first potential is a potential to allow memory cells corresponding to a selective bit line to be in on state. The method also includes setting potentials of non-adjacent word lines to a second potential while maintaining potentials of adjacent word lines at a potential which allows the memory cells corresponding to the selective bit line to be in on state and setting a potential of a selective word line to a third potential. The second potential is a potential which is determined so as to allow the memory cells corresponding to the selective bit line to be in off state. The third potential is a potential where data is written in the selective memory cell corresponding to the selective bit line. | 02-13-2014 |
| 20140050027 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line. | 02-20-2014 |
| 20140056077 | COMPENSATING FOR OFF-CURRENT IN A MEMORY - A memory cell is accessed by determining an off-current of a set of memory cells, accessing a memory cell of the set of memory cells during an access period, and compensating for the off-current of the set of memory cells. | 02-27-2014 |
| 20140063959 | MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE - Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described. | 03-06-2014 |
| 20140063960 | MEMORY PROGRAM DISTURB REDUCTION - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed. | 03-06-2014 |
| 20140063961 | WRITE DATA PRESERVATION FOR NON-VOLATILE STORAGE - Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches. | 03-06-2014 |
| 20140063962 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array in which memory cells are arranged, and a first wiring connected to the memory cells. A discharging circuit discharges the voltage of the first wiring according to a first current. In addition, a charging circuit charges the voltage of the first wiring according to a second current. A control circuit detects the voltage of the first wiring and controls a magnitude of the second current based on the detected voltage. A current detection unit generates a third current proportional to the second current and generates a detection result based on a magnitude of the third current. The discharging circuit is configured to control a magnitude of the first current in accordance with the detection result. | 03-06-2014 |
| 20140063963 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory core including a memory cell array, and a peripheral circuit configured to transfer data input to a pad unit to the memory core, and transfer data transferred from the memory core to the pad unit. The peripheral circuit includes a first region including a first data bus having a first wiring resistance, and a second region including a second data bus having a second wiring resistance lower than the first wiring resistance. The first region transfers data parallel at a first operating speed, and the second region serially transfers data at a second operating speed higher than the first operating speed. | 03-06-2014 |
| 20140063964 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, sense amplifiers are arranged one by one within an arrangement width of k bit lines in a direction of the bit lines, and determine data stored in the memory cells, based on potentials of the respective bit lines. Transistors constituting the sense amplifier are arranged one by one within an arrangement width of the sense amplifier in the direction of the bit lines. A gate length direction of the transistors is identical to the direction of the bit lines. A longer side direction of a contact electrode connected to an active area of the transistor is identical to the direction of the bit lines. | 03-06-2014 |
| 20140063965 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. | 03-06-2014 |
| 20140071759 | NONVOLATILE MEMORY DEVICE - According to an embodiment, a nonvolatile memory device includes a plurality of memory cell strings disposed in parallel in a first direction, a bit line and a first contact plug. Each of the memory cell strings extends in a second direction orthogonal to the first direction and includes a plurality of memory cells disposed in parallel in the second direction. The bit line is shared by two adjacent memory cell strings of the memory cell strings, and the first contact plug is connected to the bit line and one of the two adjacent memory cell strings. The bit line includes a first transistor section controlling a current flowing in the one of the adjacent memory cell strings. | 03-13-2014 |
| 20140071760 | SYSTEMS AND METHODS FOR ERASING CHARGE-TRAP FLASH MEMORY - FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors. | 03-13-2014 |
| 20140078826 | Methods of Making Word Lines and Select Lines in NAND Flash Memory - A NAND flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits. | 03-20-2014 |
| 20140078827 | APPARATUSES AND METHODS INCLUDING MEMORY ARRAY AND DATA LINE ARCHITECTURE - Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described. | 03-20-2014 |
| 20140085982 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor. | 03-27-2014 |
| 20140085983 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on. | 03-27-2014 |
| 20140092685 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL. | 04-03-2014 |
| 20140092686 | VERTICALLY-INTEGRATED NONVOLATILE MEMORY DEVICES HAVING LATERALLY-INTEGRATED GROUND SELECT TRANSISTORS - Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines. | 04-03-2014 |
| 20140098612 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings, a voltage generating circuit configured to generate control voltages of different voltage levels, and a control circuit configured to control application of control voltages to the word lines and the back gate line. A control voltage applied to the back gate line may be varied depending on how far a selected word line is from the back gate line, and a control voltage applied to unselected word lines may be varied depending on how far the unselected word line is from the selected word line. | 04-10-2014 |
| 20140104951 | SENSING DATA STORED IN MEMORY - The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and configured to sense a page of memory cells coupled to an activated access line by pre-charging only a single subset of a number of data lines coupled to the page, wherein more than two subsets of data lines are coupled to the page and the single subset is coupled to those memory cells storing at least a portion of a single sector of data of the page, and sensing the single subset of the number of data lines to determine the at least a portion of the single sector of data. | 04-17-2014 |
| 20140104952 | INTEGRATED CIRCUIT DEVICE - A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor. | 04-17-2014 |
| 20140112075 | Pre-Charge During Programming For 3D Memory Using Gate-Induced Drain Leakage - In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end. | 04-24-2014 |
| 20140119122 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device and a method of programming the nonvolatile semiconductor memory device are disclosed. The programming method includes applying a first voltage greater than a ground voltage to a selected word line at a first time; applying a second voltage greater than the first voltage to the selected word line at a second time that occurs after a predetermined period from the first time; applying the ground voltage to a first unselected word line directly adjacent to the selected word line at the first time; and applying a third voltage greater than the ground voltage to the first unselected word line at the second time. | 05-01-2014 |
| 20140126291 | 3D STACKED NON-VOLATILE STORAGE PROGRAMMING TO CONDUCTIVE STATE - Programming NAND strings in a 3D stacked storage device to a conductive state is disclosed. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided. | 05-08-2014 |
| 20140133237 | On-Device Data Analytics Using NAND Flash Based Intelligent Memory - A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. The system can be applied to perform a wide range of analytics on data sets loaded into the NAND array. | 05-15-2014 |
| 20140133238 | METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY WITH JUNCTIONLESS CELLS - A non-volatile memory system that has junctionless transistors is provided that uses suppression of the formation of an inversion-layer source and drain in the junctionless transistors to cause a discontinuous channel in at least one string. The system may include NAND flash memory cells composed of junctionless transistors, and has a set of wordlines. During program operation, a selected wordline of the set of wordlines is biased at a program voltage, and wordline voltage low enough to suppress the formation of source/drains is applied on at least one word line on a source side of the selected wordline such that a channel isolation occurs thereby causing the discontinuous channel in the at least string. | 05-15-2014 |
| 20140133239 | MEMORY DEVICES HAVING SELECT GATES WITH P TYPE BODIES, MEMORY STRINGS HAVING SEPARATE SOURCE LINES AND METHODS - Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing. | 05-15-2014 |
| 20140140137 | NAND-TYPE NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a NAND-type non-volatile semiconductor storage includes a memory cell array and a control circuit. The memory cell array has a memory string in which more than one of memory cells are connected in series, a word line connected to more than one of memory cells, and a bit line connected to one end of the memory string. The control circuit performs a program operation, a verify operation, and a step-up operation in a program operation loop. The control circuit performs the program operation to apply a program voltage to the word line. The control circuit performs the verify operation after the program operation. The control circuit performs the step-up operation to program a memory cell judged to be insufficiently programmed at the verify-read operation using a step-up voltage. The control circuit sets the step-up voltage increasing, each time the step-up operation is performed. | 05-22-2014 |
| 20140146609 | Weighted Read Scrub For Nonvolatile Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced. | 05-29-2014 |
| 20140153334 | TERMINATION FOR COMPLEMENTARY SIGNALS - Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described. | 06-05-2014 |
| 20140160848 | SELECT GATE BIAS DURING PROGRAM OF NON-VOLATILE STORAGE - Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses. | 06-12-2014 |
| 20140160849 | METHOD AND APPARATUS FOR INDICATING BAD MEMORY AREAS - Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled. | 06-12-2014 |
| 20140160850 | STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME - Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed. | 06-12-2014 |
| 20140169095 | Select Transistor Tuning - In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range. | 06-19-2014 |
| 20140169096 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes: a memory array including a plurality of memory cells; and a peripheral circuit configured to change a voltage level of a bit line connected to a program target cell according to a threshold voltage of the program target cell among the memory cells during a program operation. | 06-19-2014 |
| 20140169097 | SEMICONDUCTOR MEMORY DEVICE, SYSTEM HAVING THE SAME AND PROGRAM METHOD THEREOF - The present invention relates to a semiconductor memory device and a program method thereof. The program method according to an embodiment of the present invention includes: precharging a plurality of cell strings by providing a positive voltage to the plurality of cell strings through a common source line; and performing a program operation on selected memory cells by applying a program pulse to the selected memory cells. | 06-19-2014 |
| 20140177339 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number. | 06-26-2014 |
| 20140185382 | ERASE FOR NON-VOLATILE STORAGE - Techniques are disclosed herein for erasing non-volatile storage elements. A sequence of increasing erase voltages may be applied to a substrate. The select line may be floated and many of the word lines may be held at a low voltage (e.g., close to 0V). However, the voltage applied to an edge word may be increased in magnitude relative to a previous voltage applied to the edge word line for at least a portion of the sequence of erase voltages. The edge word line could be the word line that is immediately adjacent to the select line. The increasing voltage applied to the edge word line may prevent or reduce damage to oxides between the select line and edge word line. It may also help to regulate the e-field across a tunnel oxide of memory cells on the edge word line. | 07-03-2014 |
| 20140185383 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first NAND string and a second NAND string are connected to a bit line. One of the first and second NAND strings is selected by first to fourth select memory cells. At the write time, data is written in a first memory cell of the first NAND string selected by of the first to fourth select memory cells, then data is written in a second memory cell of the second NAND string selected at the same time as the first memory cell, data is written in a third memory cell adjacent to the first memory cell of the first NAND string and finally data is written in a fourth memory cell of the second NAND string selected at the same time as the third memory cell. | 07-03-2014 |
| 20140185384 | NONVOLATILE MEMORY DEVICES INCLUDING SIMULTANEOUS IMPEDANCE CALIBRATION - An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the impedance calibration operation. | 07-03-2014 |
| 20140192596 | NONVOLATILE MEMORY WITH SPLIT SUBSTRATE SELECT GATES AND HEIRARCHICAL BITLINE CONFIGURATION - Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells. | 07-10-2014 |
| 20140192597 | CIRCUIT FOR CONTROLLING EEPROM CELL - An EEPROM cell control circuit is provided which includes a signal input circuit configured to receive control signals for controlling an EEPROM cell from an external device; a bit line control circuit configured to provide a positive voltage and a negative voltage to two bit lines connected with the EEPROM cell in response to the control signals; and a word line control circuit configured to control a sense gate line in response to the control signals at a sense operation and to apply a positive voltage and a negative voltage to a word line. | 07-10-2014 |
| 20140192598 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a second dummy hookup transistor connected to second dummy word line. A group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistor, and the second dummy hookup transistor is aligned on either of one row and rows. The first dummy hookup transistor and the second dummy hookup transistor are arranged at least at one end of the group of hookup transistors. | 07-10-2014 |
| 20140198575 | Method And Apparatus For Program And Erase Of Select Gate Transistors - Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. When an erase command is made to erase memory cells, the select gate transistors are read to determine whether their Vth is above an acceptable range. If their Vth is above the acceptable range, the select gate transistors can be erased concurrently with the erasing of the memory cells. | 07-17-2014 |
| 20140204674 | LINE VOLTAGE BOOST SYSTEM AND METHOD FOR NON-VOLATILE MEMORY DEVICES AND MEMORY DEVICES AND PROCESSOR-BASED SYSTEM USING SAME - The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array. | 07-24-2014 |
| 20140204675 | MULTI-PAGE PROGRAM METHOD, NON-VOLATILE MEMORY DEVICE USING THE SAME, AND DATA STORAGE SYSTEM INCLUDING THE SAME - A method of programming a non-volatile memory device including a plurality of strings arranged in rows and columns comprises activating all or a part of selection lines in one column at the same time depending upon data to be programmed, driving a bit line corresponding to the one column with a bit line program voltage, and repeating the activating and the driving until bit lines corresponding to the columns are all driven. | 07-24-2014 |
| 20140219027 | Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level - Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration. | 08-07-2014 |
| 20140233316 | MEMORY SYSTEM AND PROGRAMMING METHOD THEREOF - A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell. | 08-21-2014 |
| 20140241062 | Modular, Scalable Rigid Flex Memory Module - A memory card in a computer system includes a plurality of memory elements on a NAND flash board. The NAND flash board is connected to a controller board by a flexible connector. The flexible connector allows the memory elements and NAND flash controller to be physically separated so that waste heat from one does not impact the other. The flexible connector also allows elements to be organized to create an airflow channel. The airflow channel directs air in such a way as to enhance cooling. | 08-28-2014 |
| 20140241063 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory string including first and second selection transistors, and first and second groups of memory cell transistors connected in series between the first and second selection transistors; a bit line and a source line respectively connected to the first and second selection transistors; first word lines respectively connected to gates of the memory cell transistors in the first group; second word lines respectively connected to gates of the memory cell transistors in the second group; first transfer transistors respectively connected to the first word lines; second transfer transistors respectively connected to the second word lines; and a control unit configured to apply a first control voltage to gates of the first transfer transistors and a second control voltage lower than the first control voltage to gates of the second transfer transistors when data is being written to memory cell transistors in the first group. | 08-28-2014 |
| 20140241064 | NONVOLATILE MEMORY AND OPERATING METHOD OF NONVOLATILE MEMORY - An operating method of a nonvolatile memory is provided which includes adjusting a threshold voltage of at least one first memory cell adjacent to a substrate in each cell string to be higher than a threshold voltage distribution of an erase state; and reading a second memory cell located above the at least one first memory cell in each cell string, wherein the at least one first memory cell in each cell string is a dummy memory cell. | 08-28-2014 |
| 20140241065 | Vertically-Integrated Nonvolatile Memory Devices Having Laterally-Integrated Ground Select Transistors - Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines. | 08-28-2014 |
| 20140247663 | NON-VOLATILE STORAGE WITH PROCESS THAT REDUCES READ DISTURB ON END WORDLINES - A system for reducing read disturb on edge word lines in non-volatile storage is disclosed. In one embodiment, the memory cells on edge word lines are programmed using a series of pulses that have an initial magnitude and step size between pulses that are lower than for memory cells on word lines that are not edge word lines. Additionally, when reading memory cells on word lines that are not edge word lines, the edge word lines receive a lower pass voltage than the default pass voltage applied to other unselected word lines. In another embodiment, the system applies a higher than normal bias on a neighboring word lines when reading memory cells on an edge word line. | 09-04-2014 |
| 20140247664 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell array includes a plurality of memory strings divided into a plurality of sub-blocks, each memory string including a plurality of memory cells which are connected to word lines and each sub-block being erasable independently with respect to the other sub-blocks. During writing, a control unit changes a verification level to be applied to a selected word line included in a selected sub-block depending on whether or not data has been written in a non-selected sub-block. | 09-04-2014 |
| 20140247665 | Select Transistor Tuning - In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range. | 09-04-2014 |
| 20140254274 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell and a control circuit. The memory cell is such that a ferroelectric film is provided as a gate dielectric film. When data is stored in the memory cell, the control circuit applies a first voltage to the gate dielectric film and thereafter applies a second voltage, whose amplitude is smaller than that of the first voltage and whose polarity is opposite to that of the first voltage. | 09-11-2014 |
| 20140254275 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a memory cell, a word line, and a peripheral circuit are provided. In the memory cell, a ferroelectric film is provided for a gate insulating film. The word line is connected to a control gate electrode of the memory cell. In the peripheral circuit, ferroelectric films are provided for gate insulating films and the peripheral circuit is provided near the memory cell. Here, between the same conductive type transistors of the peripheral circuit, a channel impurity concentration of a transistor to which a driving voltage which drives the word line is applied is different from a channel impurity concentration of a transistor to which a voltage which is lower than the driving voltage is applied. | 09-11-2014 |
| 20140254276 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer. | 09-11-2014 |
| 20140254277 | Method And Apparatus For Program And Erase Of Select Gate Transistors - Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. When an erase command is made to erase memory cells, the select gate transistors are read to determine whether their Vth is above an acceptable range. If their Vth is above the acceptable range, the select gate transistors can be erased concurrently with the erasing of the memory cells. | 09-11-2014 |
| 20140269075 | 2T AND FLASH MEMORY ARRAY - Flash memory arrays are described. In one embodiment, a flash memory array includes memory sectors of Two-Transistor (2T) AND memory cells. Within each of the memory sectors, a row of sector selection transistors is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line, independent from the row of sector selection transistors. Other embodiments are also described. | 09-18-2014 |
| 20140269076 | NON-VOLATILE MEMORY AND PROGRAMMING IN THEREOF - A non-volatile memory system includes a bit line and a plurality of memory cells associated with the bit line and coupled in a serial manner. The system further has a control circuitry in communication with the memory cells, wherein the control circuitry programs a target cell selected from the memory cells by applying a bit line voltage on the bit line in order to promote hot carrier injection into the target cell. The circuit also applies a programming voltage on the target cell under a hot carrier injection mechanism. Moreover, the circuit also applies a control voltage on a control cell, which is adjacent to the target cell when programming the target cell, wherein the control voltage is dependant on the threshold voltage of the control cell and the control voltage is less than the programming voltage. | 09-18-2014 |
| 20140269077 | ARRAY ARRANGEMENT FOR 3D NAND MEMORY - A semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at another end by a conductive line. The device includes memory cells at cross-points between the plurality of active strips and a plurality of word lines. The device includes string select structures arranged in an interlaced configuration as side gates for active strips. The device includes control circuitry, configured to turn on a particular active strip by applying a turn-on voltage to two string select structures arranged as side gates for the particular active strip, and to turn off a second particular active strip by applying a turn-off bias to at least one string select structure arranged as a side gate for the second particular active strip. The turn-off bias includes one of a ground voltage, a non-negative voltage, and a floating condition. | 09-18-2014 |
| 20140269078 | MEMORY ARCHITECTURE OF THIN FILM 3D ARRAY - A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias. | 09-18-2014 |
| 20140269079 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array that includes NAND cell units; and a write/erase circuit configured to execute a select gate write operation, the select gate write operation executing a programming operation for setting a threshold voltage of a drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, and, when it is judged by the verify operation on the drain side select gate that the threshold voltage of the drain side select gate has not reached the certain value, repeatedly executing a programming operation for setting a threshold voltage of a drain side dummy cell connected to the drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, until the threshold voltage of the drain side dummy cell has reached the certain value. | 09-18-2014 |
| 20140269080 | NON-VOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A non-volatile memory device includes a memory cell array and a voltage generator. The memory cell array has a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor. The voltage generator generates a program voltage, a first pass voltage, and a second pass voltage. A first boost channel voltage applied when programming an outermost memory cell from among the memory cells of each of non-selected cell strings of the cell strings is lower than a second boost channel voltage applied when programming one of remaining memory cells except for the outermost memory cell. The non-volatile memory device prevents programming disturb caused by hot carrier injection. | 09-18-2014 |
| 20140269081 | SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS - An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits. | 09-18-2014 |
| 20140269082 | OPERATION FOR NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES - A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential. | 09-18-2014 |
| 20140269083 | BIT LINE CURRENT TRIP POINT MODULATION FOR READING NONVOLATILE STORAGE ELEMENTS - Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value. | 09-18-2014 |
| 20140269084 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. | 09-18-2014 |
| 20140286101 | BACK BIAS DURING PROGRAM VERIFY OF NON-VOLATILE STORAGE - Different back bias (or body bias) conditions are applied to a non-volatile storage system during different program verify operations of a programming operation. A back bias may be applied during verify of an intermediate state (e.g., a lower page, middle page). The intermediate state is a state that exists during a program operation, but is not one of the final states. A lower back bias or no back bias is applied during verify of a final state (e.g., an upper page). Thus, a different back bias may be used when verifying an intermediate state than the back bias used when verifying a final state. Using the back bias makes it easier to verify a low V | 09-25-2014 |
| 20140293699 | High Endurance Nonvolatile Memory - A nonvolatile memory recycles previously written blocks by reassigning binary logic states and further programming memory cells with modified parameters. Cells are written twice between erase operations, thus reducing wear, and providing higher endurance. Flags indicate whether blocks are recycled, and what parameters to use in programming and reading the blocks. | 10-02-2014 |
| 20140293700 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array including a plurality of stacked memory cells, a plurality of first wirings electrically connected to the plurality of memory cells, a plurality of first contacts electrically connected to part of the plurality of first wirings and arranged in a first direction parallel to the semiconductor substrate, a plurality of second contacts electrically connected to part of the plurality of first wirings and arranged in the first direction alternately with the first contacts, a plurality of third contacts electrically connected to the first contacts and displaced from the first contacts in the first direction, and a plurality of fourth contacts electrically connected to the second contacts and displaced from the second contacts in a second direction perpendicular to the first direction. | 10-02-2014 |
| 20140293701 | Adjusting Control Gate Overdrive Of Select Gate Transistors During Programming Of Non-Volatile Memory - In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different control gate overdrive voltages so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a lower control gate overdrive voltage so that the channel potential under it is lower, and the next SGD transistor has a higher control gate overdrive voltage so that the channel potential under it is higher. The different control gate overdrive voltages can be provided by programming different threshold voltages, or by providing different control gates voltages, for the SGD transistors. Undesirable reductions in a Vsgd window due to drain-induced barrier lowering can be avoided. | 10-02-2014 |
| 20140293702 | Select Gate Materials Having Different Work Functions In Non-Volatile Memory - In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different work functions in their control gates so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a higher work function so that the channel potential under it is lower, and the next SGD transistor has a lower work function so that the channel potential under it is higher. The different work functions can be provided by using different control gate materials for the SGD transistors. One option uses p+ polysilicon and n+ polysilicon to provide higher and lower work functions, respectively. Metal or metal silicide can also be used. A single SGD transistor with different control gate materials could also be used. | 10-02-2014 |
| 20140293703 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME - A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string. | 10-02-2014 |
| 20140307508 | U-Shaped Common-Body Type Cell String - A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source. | 10-16-2014 |
| 20140313832 | ENHANCED DATA STORAGE IN 3-D MEMORY USING STRING-SPECIFIC SOURCE-SIDE BIASING - A method includes storing data in a memory, which includes multiple strings of analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines and a third dimension associated with sections, such that each string is associated with a respective bit line and a respective section and includes multiple memory cells that are connected to the respective word lines. For a group of the strings, respective values of a property of the strings in the group are evaluated. Source-side voltages are calculated for the respective strings in the group, depending on the respective values of the property, and respective source-sides of the strings in the group are biased with the corresponding source-side voltages. A memory operation is performed on the strings in the group while the strings are biased with the respective source-side voltages. | 10-23-2014 |
| 20140313833 | MEMORY DEVICES WITH A CONNECTING REGION HAVING A BAND GAP LOWER THAN A BAND GAP OF A BODY REGION - Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation. | 10-23-2014 |
| 20140328128 | NAND String Utilizing Floating Body Memory Cell - NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. | 11-06-2014 |
| 20140334232 | 3D FLASH MEMORY DEVICE HAVING DIFFERENT DUMMY WORD LINES AND DATA STORAGE DEVICES INCLUDING SAME - A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line. | 11-13-2014 |
| 20140347933 | NOR-BASED BCAM/TCAM CELL AND ARRAY WITH NAND SCALABILITY - This invention discloses a 2T-string NOR-based CAM logic cell comprising two physical NAND cells connected in series with two horizontal WLs and one vertical BL and one vertical SL. Additionally, a sector of NOR-based CAM logic cell array is configured with N vertical cell strings each including M 2T-string NOR-based CAM logic cells connected in parallel sharing a local vertical SL and one dedicated vertical ML as an Operand word vertical page. Each 2T-string NOR-based CAM logic cell can be either a binary or ternary CAM cell associated with two or three physical states assigned to NAND cells' Vt levels for defining CAM logic states. Logic match of M-logic-bit inputs is found for at least one vertical page if the corresponding M 2T-string NOR-based CAM logic cells are in non-conduction state, providing M times faster Compare performance over the NAND-based CAM and 2 time faster than SRAM-based CAM. | 11-27-2014 |
| 20140347934 | MEMORY DEVICES HAVING SELECT GATES WITH P TYPE BODIES, MEMORY STRINGS HAVING SEPARATE SOURCE LINES AND METHODS - Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing. | 11-27-2014 |
| 20140347935 | METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE - A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage. | 11-27-2014 |
| 20140355351 | CONTROLLER - A controller for a memory device having a bit line, a source line, and a plurality of strings of memory cell transistors connected between the bit line and the source line, is configured to update first and second values for each string when read and write operations are carried out on the strings, the first value for a first string being updated when a read or write operation is carried out on a memory cell transistor of the first string and the second value being updated when a read or write operation is carried out on a memory cell transistor of a second string that is different from the first string. | 12-04-2014 |
| 20140355352 | MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE - Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described. | 12-04-2014 |
| 20140362641 | Program And Read Operations For 3D Non-Volatile Memory Based On Memory Hole Diameter - Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at the lower word line layers is modified. In one approach, threshold voltage (Vth) distributions of one or more data states are narrowed during programming so that a lower read pass voltage can be used in a subsequent sensing operation. A sufficient spacing is maintained between the read pass voltage and the upper tail of the highest data state. The Vth distributions can be downshifted as well. In another approach, the read pass voltage is not lowered, but the lowest programmed state is upshifted to provide spacing from the upper tail of the erased state. | 12-11-2014 |
| 20140362642 | 3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter - A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb. | 12-11-2014 |
| 20140362643 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of electrically rewritable memory transistors arranged therein; and a control unit configured to govern control that repeats a voltage application operation and a step-up operation, the voltage application operation applying an applied voltage to a selected memory transistor to change a threshold voltage at which the selected memory transistor is conductive, and the step-up operation, in the case where a threshold voltage of the selected memory transistor has not changed to a desired value, raising the applied voltage by an amount of a certain step-up value. The control unit is configured to control the step-up operation to monotonically decrease the step-up value as the number of times of the voltage application operations increases. | 12-11-2014 |
| 20140362644 | DUAL-MODE MEMORY DEVICES AND METHODS FOR OPERATING SAME - A memory structure comprises a semiconductor strip having a multi-gate channel region, the p-type terminal region adjacent a first side of the channel region and an n-type terminal region adjacent the second side of the channel region. A plurality of word lines is arranged to cross the semiconductor strip at cross points in the channel region. The bit line is coupled to a first end of the semiconductor strip, and a reference line is coupled to a second end of the semiconductor strip. Charge storage structures are disposed between the word lines in the plurality word lines and the channel region of the semiconductor strip, whereby memory cells are disposed in series along the semiconductor strip between the bit line and the reference line. Biasing unselected word lines can be used to select n-channel or p-channel modes in a single selected cell for read, program or erase. | 12-11-2014 |
| 20140362645 | 3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter - A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb. | 12-11-2014 |
| 20140362646 | READING SOFT BITS SIMULTANEOUSLY - Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time. A binary search may be performed. | 12-11-2014 |
| 20140369126 | SIMPLIFIED NONVOLATILE MEMORY CELL STRING AND NAND FLASH MEMORY ARRAY USING THE SAME - The present invention provides a nonvolatile memory cell string and a NAND flash memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins can increase the degree of integration and basically prevent the interferences between adjacent cells. And gate electrodes formed to cover depletion regions between the channel and source regions or between the channel and drain regions enable GIDL to be used for a memory operation without GSL and CSL which are necessarily needed in the conventional NAND flash memory array and can significantly increase the degree of integration. | 12-18-2014 |
| 20140369127 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data. | 12-18-2014 |
| 20140369128 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell. | 12-18-2014 |
| 20140369129 | Method And Apparatus For Program And Erase Of Select Gate Transistors - Techniques are provided for programming select gate transistors in connection with the programming of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. | 12-18-2014 |
| 20140376313 | APPARATUSES AND METHODS FOR LIMITING STRING CURRENT IN A MEMORY - Apparatuses, current control circuits, and methods for limiting string current in a memory are described. An example apparatus includes a memory cell string including a memory cell. The example apparatus further includes a sense circuit configured to sense a current through the memory cell string, and a select gate configured to couple the memory cell string to a source based on a select gate voltage. The example apparatus further includes a current control circuit coupled to the select gate. The current control circuit is configured to limit current through the memory cell string during a memory access operation based on a reference current. | 12-25-2014 |
| 20150009756 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods and apparatus for sensing operations in memory devices are disclosed. In at least one embodiment, a sensing operation to determine negative threshold voltages in memory cells by an elevated source potential applied to a string of memory cells and an elevated data line potential applied to the string of memory cells is disclosed. A ramped sense potential is incorporated into the sense operation according to at least one embodiment. A sense circuit diode allows a sense potential to fall below a data line potential during a sensing operation according to another embodiment. | 01-08-2015 |
| 20150009757 | ARRAY ARRANGEMENT INCLUDING CARRIER SOURCE - A source of charge carriers in thin film transistor-based memory devices is provided for a memory. The source of charge carriers can include a diode having a first and second terminal. A NAND string coupled on a first end via a first switch to a bit line, is coupled on a second end via a second switch to the first terminal of the diode. Separately drivable first and second supply lines are coupled to the first and second terminals, respectively of the diode. Circuitry is included that is coupled to the first and second supply lines, that is configured to bias the first and second supply lines with different bias conditions depending on the mode of operation, including forward bias conditions and reverse bias conditions. | 01-08-2015 |
| 20150009758 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes memory cells stacked on a substrate. The method includes applying a reference voltage to an unselected drain select line, applying a drain selection voltage to a selected drain select line, and applying a word line voltage to a normal word line. Before the word line voltage is applied to the normal word line, a positive voltage is applied to a dummy word line to bounce the unselected drain select line. | 01-08-2015 |
| 20150009759 | SUBSTRATE CONNECTION OF THREE DIMENSIONAL NAND FOR IMPROVING ERASE PERFORMANCE - A memory includes a doped substrate well, a substrate connector coupled to the doped substrate well, and a set of interlayer connectors insulated from the doped substrate well. A series arrangement including a plurality of memory cells is coupled on a first end by a first switch to a bit line and coupled on a second end by a second switch to a source line contact pad. The source line contact pad is connected to the substrate connector and to at least one of the interlayer connectors in the set of interlayer connectors. A supply line is connected to the set of interlayer connectors. A plurality of word lines is coupled to the plurality of memory cells. Circuitry is coupled to the supply line and to the doped substrate well and configured to bias the supply line and the doped substrate well with different bias conditions. | 01-08-2015 |
| 20150016190 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings, a voltage generating circuit configured to generate control voltages of different voltage levels, and a control circuit configured to control application of control voltages to the word lines and the back gate line. A control voltage applied to the back gate line may be varied depending on how far a selected word line is from the back gate line, and a control voltage applied to unselected word lines may be varied depending on how far the unselected word line is from the selected word line. | 01-15-2015 |
| 20150029792 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. When threshold voltages of memory cells are boosted to use the memory cells as a selection transistor, a threshold voltage of an outermost memory cell may be boosted to the highest level so that a leakage current can be reduced and a channel boosting level can be increased to reduce the influence of program disturbance. | 01-29-2015 |
| 20150029793 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device including: a memory cell array including NAND strings; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to execute a write operation. The control circuit is configured to, when charging an unselected memory string prior to the write operation, execute both first and second charging operations, the first charging operation applying to the bit line connected to the unselected memory string a first voltage and rendering conductive a first select transistor to charge the unselected memory string, and the second charging operation applying to the source line connected to the unselected memory string a second voltage and rendering conductive a second select transistor to charge the unselected memory string, the first and second charging operations being executed at different timings. | 01-29-2015 |
| 20150036434 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the multiplexed data at a startup. The arithmetic operation circuit performs operations by use of the multiplexed data. | 02-05-2015 |
| 20150043278 | Group Word Line Erase And Erase-Verify Methods For 3D Non-Volatile Memory - An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately. | 02-12-2015 |
| 20150049551 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array includes a plurality of memory cell layers that are stacked. Each memory cell layer comprises a plurality of memory cells formed on a semiconductor layer. The plurality of memory cell layers include: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon. The control circuit, when controlling write or read of data to/from a memory cell belonging to the first memory cell layer, performs control based on a first parameter, and when controlling write or read of data to/from a memory cell belonging to the second memory cell layer, performs control based on a second parameter that differs from the first parameter. | 02-19-2015 |
| 20150063032 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - This nonvolatile semiconductor memory device comprises: a word line connected to a control gate; a bit line electrically connected to one end of a NAND cell unit; a source line electrically connected to the other end of the NAND cell unit; and a control circuit that controls a voltage applied to a semiconductor layer, the control gate, the bit line, and the source line. | 03-05-2015 |
| 20150063033 | Selective Word Line Erase In 3D Non-Volatile Memory - An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling. | 03-05-2015 |
| 20150070998 | VREAD BIAS ALLOCATION ON WORD LINES FOR READ DISTURB REDUCTION IN 3D NON-VOLATILE MEMORY - Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter. | 03-12-2015 |
| 20150070999 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a nonvolatile semiconductor memory device includes a plurality of memory cells and a control circuit. The memory cell includes a semiconductor layer, a gate insulating layer, a floating gate, a lower control gate, and an upper control gate. The semiconductor layer extends in a certain direction. The lower control gate is formed on the floating gate via an insulating layer. The upper control gate is formed on the lower control gate via an insulating layer. In addition, the control circuit, when performing a write operation, applies a first pass voltage to the upper control gate in a selected memory cell, and applies a first write voltage which is larger than the first pass voltage to the upper control gate in an adjacent memory cell formed on an identical semiconductor layer to the selected memory cell and adjacent to the selected memory cell. | 03-12-2015 |
| 20150071000 | SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE JUDGING METHOD THEREOF - A semiconductor memory device is provided with a plurality of memory cells connected to a plurality of word lines, a word-line leakage detector configured to detect a leakage current generated on at least one of the plurality of word lines, and a controller configured, when a leakage current is detected by the word-line leakage detector, to determine that a block including a memory cell connected to a word line through which the leakage current is flowing is defective. The word-line leakage detector has a detection voltage generator configured to generate a detection voltage in accordance with the leakage current, a comparator configured to generate a flag signal having output logic that is inverted depending on whether the detection voltage exceeds a predetermined threshold voltage, and an adjuster configured to adjust a current amount by diverting part of the leakage current in accordance with an ambient temperature. | 03-12-2015 |
| 20150071001 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment is provided with a plurality of first latch circuits that latch setting-data at different timings, a plurality of hold circuits provided corresponding to the respective plurality of first latch circuits, each holding data latched by the corresponding first latch circuit, and an address decoder that decodes an address that specifies a destination to hold data. Each of the plurality of hold circuits has one or more holding parts that hold data latched by the corresponding first latch circuit based on a decode signal decoded by the address decoder. | 03-12-2015 |
| 20150078089 | METHODS AND APPARATUSES HAVING STRINGS OF MEMORY CELLS AND SELECT GATES WITH DOUBLE GATES - An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front control gate and a back control gate. The front and back control gates can be coupled together such that they are biased at the same voltage or separate such that they can be biased at different voltages. | 03-19-2015 |
| 20150078090 | 3D Non-Volatile Storage With Transistor Decoding Structure - Disclosed herein are 3D stacked memory devices having WL select gates. The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors. 3D decoding may be provided in a 3D stacked memory device using the WL select gates. | 03-19-2015 |
| 20150085579 | CONTACT STRUCTURE AND FORMING METHOD - Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second buffer layer under the first sub stack. An upper layer of the first sub stack is exposed through a set of vias by first and second etching processes. The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack. A third etching process etches through the first set of etch vias, through the first sub stack and stops at or in the second buffer layer. A fourth etching process and etches through the second buffer layer. | 03-26-2015 |
| 20150098274 | Cell Array with a Manufacturable Select Gate for a Nonvolatile Semiconductor Memory Device - A three-dimensional integrated circuit non-volatile memory array includes a memory array with first and second NAND memory cell string stacks having opposite orientations, where each NAND memory cell string includes a plurality of transistors and a source line contact connected in series between a bit line and string extension region which extends from the source line contact and past a first self-aligned SSL gate electrode located on a peripheral end of the NAND memory cell string, and also includes a string select transistor formed with a second self-aligned SSL connected in series between the bit line and the plurality of transistors, where the first and second self-aligned SSL gate electrodes are shared between adjacent NAND memory cell strings having opposite orientations. | 04-09-2015 |
| 20150103600 | Nonvolatile Semiconductor Memory Device - A non-volatile memory device, comprising: a substrate; a plurality of string stacks disposed over the substrate, each string stack comprising a long axis and a short axis in a plane parallel to the substrate, the long axis extending along a y-direction and the short axis extending along an x-direction, each string stack comprising a plurality of strings being stacked in a direction vertical to the substrate and having a first end and a second end at different locations in the y-direction, the plurality of string stacks comprising a first and a second set of string stacks, at least some of the string stacks of the first set of string stacks being offset along the x-direction from at least some of the string stacks of the second set of string stacks. | 04-16-2015 |
| 20150109864 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING AND OPERATING THE SAME - An integrated circuit and methods for manufacturing and operating the same are provided. The integrated circuit comprises a fork architecture and a first conductive structure. The fork architecture comprises a handle portion and prong portions extending from the handle portion. The fork architecture comprises a stacked structure and a dielectric layer. The dielectric layer is between the first conductive structure and the handle portion of the stacked structure. | 04-23-2015 |
| 20150124530 | MEMORY STRING AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to k | 05-07-2015 |
| 20150131381 | Three Dimensional Nonvolatile Memory Cell Structure with Upper Body Connection - A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines. | 05-14-2015 |
| 20150294729 | COMPENSATING FOR OFF-CURRENT IN A MEMORY - A memory cell is accessed by determining an off-current of a set of memory cells, accessing a memory cell of the set of memory cells during an access period, and compensating for the off-current of the set of memory cells. | 10-15-2015 |
| 20150371709 | Three Dimensional Vertical NAND Device With Floating Gates - A monolithic three dimensional NAND string including a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a substrate. The first material layers include a plurality of control gate electrodes and the second material layers include an insulating material and the plurality of control gate electrodes extend in a first direction. The NAND string also includes a semiconductor channel, a blocking dielectric, and a plurality of vertically spaced apart floating gates. Each of the plurality of vertically spaced apart floating gates or each of the second material layers includes a first portion having a first thickness in the second direction, and a second portion adjacent to the first portion in the first direction and having a second thickness in the second direction which is different than the first thickness. | 12-24-2015 |
| 20150371996 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes an array of floating gate memory cells. Adjacent memory cells are separated by a plurality of air gaps that electrically decouple respective active regions of adjacent memory cells from one another. Additionally, the air gaps electrically decouple an active region of a memory cell from a floating gate of an adjacent memory cell. | 12-24-2015 |
| 20150380092 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S | 12-31-2015 |
| 20150380422 | Vertical Floating Gate NAND with Selectively Deposited ALD Metal Films - A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide. | 12-31-2015 |
| 20160005474 | MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF - An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line. | 01-07-2016 |
| 20160012897 | NONVOLATILE MEMORY DEVICE, A STORAGE DEVICE HAVING THE SAME AND AN OPERATING METHOD OF THE SAME | 01-14-2016 |
| 20160012898 | MEMORY SYSTEM AND PROGRAMMING METHOD THEREOF | 01-14-2016 |
| 20160019971 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to an embodiment, a non-volatile semiconductor memory device comprises a NAND cell unit, a bit-line, a source-line, word-lines and a control circuit. The NAND cell unit comprises memory cells connected in series. The bit-line is connected to an end of the NAND cell unit. The source-line is connected to the other end of the NAND cell unit. The word-lines are connected to respective control gates of the memory cells. The control circuit applies, to a non-selected word-line on the bit-line side of a predetermined boundary in the NAND cell unit, a first read-pass voltage turning on the memory cell regardless of the cell data. The control circuit applies, to a non-selected word-line on the source-line side of the predetermined boundary, a second read-pass voltage less than the first read-pass voltage. The control circuit provides a read bit-line voltage between the bit-line and the source-line. | 01-21-2016 |
| 20160027512 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD OF THE SAME - A nonvolatile semiconductor memory device according to an embodiment includes a control unit, during the read sequence performed to an interested cell, performing a first read operation to detect that a threshold voltage of an adjacent cell is higher than a second reference voltage higher, performing a second read operation to detect that the threshold voltage of the interested cell is higher than a first reference voltage while applying a first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are lower than the second reference voltage, and to detect that the threshold voltage of the interested cell is higher than the first reference voltage while applying a second bit line voltage higher than the first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are higher than the second reference voltage, after the first read operation. | 01-28-2016 |
| 20160027514 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the horizontal semiconductor layer. According to example embodiments, a programming method of the nonvolatile memory device includes setting up bitlines corresponding the cell strings, setting up a plurality of string select lines connected to the cell strings, and applying a negative voltage lower to a ground select line. The ground select line is connected to a plurality of ground select transistors between the memory cells and the semiconductor layer. The string select lines extend in a direction intersecting the bitlines. The negative voltage is lower than a ground voltage. | 01-28-2016 |
| 20160027520 | SEMICONDUCTOR MEMORY DEVICE INCLUDING THREE-DIMENSIONAL MEMORY CELL ARRAY STRUCTURE AND OPERATING METHOD THEREOF - An operating method includes biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines; floating the channel regions of the unselected cell strings; increasing the first pass voltage to a second pass voltage during the floating of the channel regions; and reading data from selected memory cells of selected cell strings among the cell strings. | 01-28-2016 |
| 20160035424 | Systems and methods for trimming control transistors for 3D NAND flash - Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation. | 02-04-2016 |
| 20160042771 | TIMED MULTIPLEX SENSING - Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation. | 02-11-2016 |
| 20160055911 | Techniques for Programming of Select Gates in NAND Memory - In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage. | 02-25-2016 |
| 20160055915 | Avoiding Unintentional Program Or Erase Of A Select Gate Transistor - Techniques are provided for preventing inadvertent program or erase of select gate transistors and dummy memory cells during an erase operation involving data-storing memory cells in a three-dimensional memory device. The erase operation charges up a channel of a NAND string using gate-induced drain leakage from the select gate transistors. An erase voltage waveform and a select gate waveform are ramped up to intermediate levels which allow some charging of the channel to occur. The intermediate level of the select gate waveform is low enough to avoid inadvertent programming of the select gate transistors. Subsequently, the erase voltage waveform and the select gate waveform are ramped up to peak levels which allow additional charging of the channel to occur. The peak levels are set to avoid inadvertent erasing of the select gate transistors. | 02-25-2016 |
| 20160064087 | Charge Redistribution During Erase In Charge Trapping Memory - Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole. | 03-03-2016 |
| 20160064088 | SEMICONDUCTOR MEMORY DEVICE AND DATA ERASING METHOD - A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein. | 03-03-2016 |
| 20160064090 | Charge Redistribution During Erase In Charge Trapping Memory - Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole. | 03-03-2016 |
| 20160071595 | Controlling Pass Voltages To Minimize Program Disturb In Charge-Trapping Memory - Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer, either in a two-dimensional or three-dimensional configuration. In such a NAND string, regions between the memory cells can be inadvertently programmed as parasitic cells due to the program voltage and pass voltages on the word lines. For programmed cells, an upshift in threshold voltage due to a parasitic cell can be avoided by providing a higher pass voltage on an adjacent later-programmed word line than on an adjacent previously-programmed word line. For erased cells, an upshift in threshold voltage due to the parasitic cells can be reduced by progressively lowering the pass voltage on the adjacent later-programmed word line. The lowering can occur when memory cells of a lowest target data state complete programming. | 03-10-2016 |
| 20160071876 | MULTI-CHARGE REGION MEMORY CELLS FOR A VERTICAL NAND DEVICE - A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are positioned adjacent to two different control gate electrodes. Alternately, the pair of charge storage regions can be two disjoined structures located on opposite sides of a portion of a semiconductor channel. Yet alternately, the pair of charge storage regions can be two disjoined structures located at the same level, and on two laterally split semiconductor channel. The memory cell can be employed to store two bits of information within the pair of charge storage regions located at the same level within a vertical memory string that employs a single memory opening. | 03-10-2016 |
| 20160078941 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A NAND STRING - A semiconductor memory device includes a first NAND string and a second NAND string are connected to a bit line. One of the first and second NAND strings is selected by first to fourth select memory cells. At the write time, data is written in a first memory cell of the first NAND string selected by of the first to fourth select memory cells, then data is written in a second memory cell of the second NAND string selected at the same time as the first memory cell, data is written in a third memory cell adjacent to the first memory cell of the first NAND string and finally data is written in a fourth memory cell of the second NAND string selected at the same time as the third memory cell. | 03-17-2016 |
| 20160078953 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory cell and a second memory cell having a parasitic capacitance smaller than a parasitic capacitance of the first memory cell, a first bit line that is electrically connected to the first memory cell, a second bit line that is electrically connected to the second memory cell, a first sense module that is electrically connected to the first bit line through a first transistor, and a second sense module that is electrically connected to the second bit line through a second transistor. During sensing of the first and second bit lines, the first and second transistors are turned on for first and second periods of time, respectively, to electrically connect the first and second sense modules to the corresponding first and second bit lines. The first period of time is longer than the second period of time. | 03-17-2016 |
| 20160086665 | MEMORY ARCHITECTURE OF THIN FILM 3D ARRAY - A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias. | 03-24-2016 |
| 20160086666 | MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE - Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described. | 03-24-2016 |
| 20160086674 | TEMPERATURE DEPENDENT SENSING SCHEME TO COUNTERACT CROSS-TEMPERATURE THRESHOLD VOLTAGE DISTRIBUTION WIDENING - Methods for reducing cross-temperature threshold voltage distribution widening by applying a temperature dependent sensing scheme during read operations are described. In some embodiments, during a read operation, the sensing conditions applied to memory cells within a memory array (e.g., the sensing time and the read voltage applied to the memory cells during the sensing time) may be set and/or adjusted based on a temperature of the memory cells during the read operation, a previous temperature of the memory cells when the memory cells were programmed, and the programmed states of neighboring memory cells. In some cases, the sensing time for sensing a memory cell of a NAND string and the source voltage applied to a source line connected to the NAND string may be set based on the temperature of the memory cells during sensing and the previous temperature of the memory cells when the memory cells were programmed. | 03-24-2016 |
| 20160099056 | PAGE BUFFER CIRCUIT FOR NAND FLASH MEMORY - A page buffer for a NAND flash memory array includes a pre-charge switch, a first switch, a read switch, a write switch, a latch, and a data switch. The pre-charge switch is coupled between a supply node with a supply voltage and a bit line that is coupled to a selected cell of the NAND flash memory array. The first switch is coupled between the bit line and a data node. The read switch is coupled between the data node and an I/O node. The write switch is coupled between an inverse data node, which is out of phase with the data node, and the I/O node. The latch is coupled between the data node and the inverse data node. The data switch is coupled between the inverse data node and a first node. The enable switch is coupled between the first node and a ground. | 04-07-2016 |
| 20160099059 | NON-VOLATILE MEMORY AND METHOD WITH ADJUSTED TIMING FOR INDIVIDUAL PROGRAMMING PULSES - A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a group of memory cells associated with a selected word line. Individual timing of the programming pulses such as rise and fall times of the pulse is optimally and dynamically adjusted according to the relative numbers of program-enabled and program-inhibited memory cells in the group associated with that pulse. | 04-07-2016 |
| 20160099064 | NON-VOLATILE SEMICONDUCTOR MEMORY WITH HIGH RELIABILITY AND DATA ERASING METHOD THEREOF - A non-volatile semiconductor memory apparatus and a data erasing method thereof are provided to suppress deterioration in reliability due to data rewriting. An erasing method of a flash memory is provided, which includes the following steps. A control gate is maintained at 0V, a high-voltage erase pulse is applied to a P well, such that electrons is emitted from a floating gate to the P well. Then, the control gate is again maintained, and a weak erase pulse with a voltage lower than the erase pulse is applied to the P well. | 04-07-2016 |
| 20160099066 | Bit Line Pre-Charge With Current Reduction - Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line. | 04-07-2016 |
| 20160118122 | VERTICAL STRUCTURE SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes. | 04-28-2016 |
| 20160118133 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL. | 04-28-2016 |
| 20160125944 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a drain selection line, word lines and a source selection line. The semiconductor device may include an operation circuit configured for performing a program operation. The operation circuit may be configured for sequentially performing a first operation, a second operation, and a third operation. In the first operation memory cells adjacent to the drain selection transistor may be programmed. In the second operation memory cells adjacent to the source selection transistor may be programmed. In the third operation remaining memory cells may be programmed. | 05-05-2016 |
| 20160133327 | MEMORY DEVICES AND BIASING METHODS FOR MEMORY DEVICES - Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source, where the data line is biased to a potential greater than a potential to which the source is biased during a programming operation performed on the selected memory cell. | 05-12-2016 |
| 20160141039 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit ( | 05-19-2016 |
| 20160163389 | THREE-DIMENSIONAL MEMORY STRUCTURE HAVING A BACK GATE ELECTRODE - A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell. | 06-09-2016 |
| 20160163391 | FLASH MEMORY AND PROGRAMMING METHOD THEREOF - A programming method of an NAND flash memory is provided, for narrowing a distribution width of a threshold voltage. The method includes a step of verification reading for verifying a threshold voltage of a selected memory cell after a programming voltage is applied to a selected word line. The verification reading further includes a step of pre-charging a voltage to a bit line, a step of discharging the pre-charged bit line to a source line, and a step of reading the voltage of the bit line after the discharging step. Regarding the discharge period from starting the discharging of the bit line to starting the read out, the discharge period of the verification reading after the initial programming voltage is applied is set longer than the discharge period of the verification reading after the subsequent programming voltage is applied. | 06-09-2016 |
| 20160172040 | MEMORY DEVICE AND DATA ERASING METHOD THEREOF | 06-16-2016 |
| 20160189777 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - A semiconductor storage device has a memory string including a memory cell, a bit line electrically connected to one end of the memory string, and a sense amplifier electrically connected to the bit line. The sense amplifier has a first transistor, one end of which is connected to a first node on an electric current path of the bit line, and another end of which is electrically connected to a second node, a second transistor electrically connected between the second node and a sense node, and a third transistor, a gate of which is connected to the first node, and the third transistor being electrically connected between the second node and a third node whose voltage can be adjusted. | 06-30-2016 |
| 20160189778 | TECHNIQUES FOR PROGRAMMING OF SELECT GATES IN NAND MEMORY - In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage. | 06-30-2016 |
| 20160254053 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME | 09-01-2016 |
| 20160379717 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value. | 12-29-2016 |
| 20190147962 | REDUCING PROGRAM DISTURB BY MODIFYING WORD LINE VOLTAGES AT INTERFACE IN TWO-TIER STACK AFTER PROGRAM-VERIFY | 05-16-2019 |
