| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365185160 | Virtual ground | 13 |
| 20090046514 | SEMICONDUCTOR MEMORY DEVICE - A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line. | 02-19-2009 |
| 20090059668 | Virtual ground array memory and programming method thereof - A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails. | 03-05-2009 |
| 20090103363 | APPARATUS AND ASSOCIATED METHOD FOR MAKING A VIRTUAL GROUND ARRAY STRUCTURE THAT USES INVERSION BIT LINES - A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging. | 04-23-2009 |
| 20090109757 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device. | 04-30-2009 |
| 20090116289 | DECODING SYSTEM CAPABLE OF REDUCING SECTOR SELECT AREA OVERHEAD FOR FLASH MEMORY - Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods arc disclosed for selecting a memory cell sector to be erased and adjacent sectors to be protected, which may be used in single bit and dual bit memory devices, and which enable column decoder circuitry to reduce the number of sector select circuits. | 05-07-2009 |
| 20090129164 | SEMICONDUCTOR NON-VOLATILE MEMORY - A semiconductor non-volatile memory, wherein a memory cell can be read accurately without having to discharge bit lines before the read operation. When reading a memory cell, the first bit line connected to the drain thereof is connected to the voltage source to receive a predetermined voltage, and the second bit line connected to the source thereof is connected to the sense amplifier. In this process, the third bit line in the vicinity of the second bit line is connected to the ground power supply. Thus, since the third bit line in the vicinity of the second bit line being sensed is forcibly set to the ground level, no charge flows in therefrom, thus preventing a current flowing into the second bit line. | 05-21-2009 |
| 20090135651 | CURRENT OR VOLTAGE MEASUREMENT CIRCUIT, SENSE CIRCUIT, SEMICONDUCTOR NON-VOLATILE MEMORY, AND DIFFERENTIAL AMPLIFIER - In a wire pair | 05-28-2009 |
| 20100195394 | NONVOLATILE MEMORY DEVICE - A page buffer of a nonvolatile memory device according to the present disclosure comprises a first data latch unit configured to store data for program or program inhibition, a second data latch unit configured to store data for setting threshold voltage states of cells to be programmed, and a 1-bit pass determination unit configured to determine whether a cell to be programmed has been programmed to exceed a verification voltage by grounding or making floating a first verification signal output terminal in response to data set to a first node of the first data latch unit and data applied to a sense node. | 08-05-2010 |
| 20110286273 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device. | 11-24-2011 |
| 20130094297 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device. | 04-18-2013 |
| 20130114341 | Method and Apparatus for Indicating Bad Memory Areas - Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled. | 05-09-2013 |
| 20140036591 | MEMORY DEVICE - A memory device includes a memory cell array including a plurality of memory cells, a common source line to which sources of the plurality of memory cells are commonly connected, and a second electrical connection path further connecting the common source line to a ground voltage using erase-mode memory cells when the common source line forms a first electrical connection path and is connected to the ground voltage. | 02-06-2014 |
| 20140241061 | FAST ACCESS WITH LOW LEAKAGE AND LOW POWER TECHNIQUE FOR READ ONLY MEMORY DEVICES - A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption. | 08-28-2014 |
