| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365185130 | Global word or bit lines | 63 |
| 20080219054 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING OF THE SAME - A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of two active areas neighboring in a second direction that crosses the first direction, and a second extension portion which is provided between other-side terminal end portions of the two active areas neighboring in the second direction, the first and second extension portions connecting the two active areas in a loop configuration. | 09-11-2008 |
| 20080239813 | Method of Compensating Variations along a Word Line in a Non-Volatile Memory - Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter. | 10-02-2008 |
| 20080239814 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of memory cells coupled in series, a plurality of word lines coupled to the respective memory cells, and a plurality of spacers interposed between the word lines and having different dielectric constants according to line widths of the word lines. | 10-02-2008 |
| 20080239815 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a memory cell area of a semiconductor device, first, second, and third inter-layer insulating films respectively cover a cell transistor, a bit wiring line, and a capacitor which are connected to each other. In an adjacent peripheral circuit area, a peripheral-circuit transistor is covered with the first inter-layer insulating film, a first-layer wiring line connected to the peripheral-circuit transistor is provided on the first inter-layer insulating film and covered with the second inter-layer insulating film, and a second-layer wiring line is provided on the third inter-layer insulating film. In the memory cell area, a landing pad is provided on the second inter-layer insulating film and between the capacitor and a contact plug for connecting the capacitor to the cell transistor. An assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided. | 10-02-2008 |
| 20080247234 | FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A flash memory device includes a plurality of memory cell blocks, an operating voltage generator, a block switching unit and a voltage supply circuit. Each of the plurality of memory cell blocks includes select lines and word lines, and has pass word lines included between the select lines and the word lines. The operating voltage generator outputs operating voltages to global select lines, global word lines and global pass word lines. The block switching unit connects the global word lines to the word lines and the select lines in response to a block select signal. The voltage supply circuit is connected to the select line and the pass word line, and is configured to supply the select line and the pass word line with a ground voltage in response to a block select inverse signal. | 10-09-2008 |
| 20080285348 | Nonvolatile semiconductor memory device having assist gate - In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision. | 11-20-2008 |
| 20080304321 | Serial Flash Memory Device and Precharging Method Thereof - Provided herein is a serial flash memory device and precharging method thereof in which a single local bit-line data is sensed in synchronization with a clock. The method includes precharging two or more local bit-lines in synchronization with a first clock; and disprecharging one of the two local bit-lines in synchronization with a second clock and sensing and amplifying data of the other local bit-line. Accordingly, two precharged local bit-lines are not adjacent to each other, thereby eliminating a coupling noise effect. In addition, the time for performing the precharging operation and the sensing operation is easily secured, compared to the prior precharging method in which corresponding local bit-lines are precharged at every clock. | 12-11-2008 |
| 20080304322 | NAND FLASH MEMORY CELL PROGRAMMING - A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block. Methods for pre-charging word lines in unselected array blocks are described. | 12-11-2008 |
| 20080310231 | OPTIMIZATION OF CRITICAL DIMENSIONS AND PITCH OF PATTERNED FEATURES IN AND ABOVE A SUBSTRATE - A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region. | 12-18-2008 |
| 20080316826 | Semiconductor device having transistor and capacitor of SOI structure and storing data in nonvolatile manner - In a semiconductor device, a first transistor of an SOI structure has a source region, a drain region, a body region positioned between the source region and the drain region, and a gate electrode positioned above the body region. A first capacitor of the SOI structure has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal. The semiconductor device stores data in a nonvolatile manner in accordance with carriers accumulated in a first node electrically connecting the gate electrode of the first transistor and the first terminal of the first capacitor. | 12-25-2008 |
| 20090003067 | Non-volatile memory device for reducing layout area of global wordline decoder and operation method thereof - A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder. | 01-01-2009 |
| 20090016109 | Semiconductor device and its control method - A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal. | 01-15-2009 |
| 20090034335 | Semiconductor device and its control method - A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal. | 02-05-2009 |
| 20090040829 | LATERAL POCKET IMPLANT CHARGE TRAPPING DEVICES - A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trapping structure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes. | 02-12-2009 |
| 20090040830 | BLOCK DECODER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal. | 02-12-2009 |
| 20090052250 | SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD - A semiconductor memory device has a plurality of word line provided on a semiconductor region, extending in a row direction, a plurality of bit lines provided in the semiconductor region, extending in a column direction, and a plurality of memory elements provided at intersections between the plurality of word lines and the plurality of bit lines. Each word line provides a first gate electrode in the corresponding memory element. A lower portion of a side surface of each word line in a direction parallel to an extending direction of the word line is perpendicular to a main surface of the semiconductor region. An upper portion of the side surface is inclined so that a width thereof becomes smaller toward a top thereof. | 02-26-2009 |
| 20090080257 | SEMICONDUCTOR DEVICE - The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged. | 03-26-2009 |
| 20090097315 | Multibit electro-mechanical memory device and method of manufacturing the same - A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites. | 04-16-2009 |
| 20090097316 | FLASH MEMORY DEVICE - The flash memory device includes a block switch, first and second cell strings, first and second source lines, drain contacts, and first and second source contacts. The first cell string is connected to a first bit line and a second cell string is connected to a second bit line. The first and second cell strings each include a drain select transistor, a plurality of cell transistors, and a source select transistor connected in series. The drain contacts connect the first and second bit line to a semiconductor substrate. The first and second source contacts connect the first and second source lines to the semiconductor substrate. The first and second source lines in the same block are not adjacent and separated from each other by a predetermined interval. | 04-16-2009 |
| 20090116286 | OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE - A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells. | 05-07-2009 |
| 20090116287 | OPERATION METHODS FOR MEMORY CELL AND ARRAY THEREOF IMMUNE TO PUNCHTHROUGH LEAKAGE - An integrated circuit includes a memory cell structure including a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. The second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell and is coupled to a first source. A second doped region is configured within the substrate and adjacent to the second cell. The second doped region is coupled to a second source. At least one third doped region is between the first cell and the second cell, wherein the third doped region is floating. | 05-07-2009 |
| 20090116288 | Method, device and apparatus for accessing a non-volatile memory array - A non-volatile memory (NVM) having an array of memory cells and a unidirectional multiplexer (UMUX), the UMUX may be comprised of two or more address line ports adapted to receive addressing signals corresponding with elements in the memory array, and a set of switching transistors adapted to switch a supply voltage in accordance with the addressing signal such that current only flows into the array. | 05-07-2009 |
| 20090168529 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD FOR MANUFACTURING THE SAME, AND NONVOLATILE MEMORY ARRAY - A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate. A first impurity diffusion layer, which occupies a space within the semiconductor substrate, is provided separately apart from the floating gate by a predetermined distance. A second impurity diffusion layer, which occupies a space within the semiconductor substrate, overlaps with the floating gate. Electrons are injected into the floating gate by applying a high voltage to the second impurity diffusion layer in capacitive coupling with the floating gate. | 07-02-2009 |
| 20090168530 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING DATA THEREFROM - A semiconductor memory device comprises a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register, and a second address register which receives an output address from the first address register and outputs an address signal in response to an address control signal from the sequencer. In reading from the memory cells, the sequencer reads a page n in accordance with the address stored in the second address register, then transfers an address stored in the first address register to the second address register concurrently with outputting data read from the page n to outside and reads data from an arbitrary page m in accordance with the address transferred to the second address register. | 07-02-2009 |
| 20090175083 | Nonvolatile Semiconductor Memory Device - The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines. | 07-09-2009 |
| 20090201737 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a write circuit including a latch circuit configured by two inverters having a positive side power supply terminal supplied with a first voltage and a negative side power supply terminal supplied with a second voltage; and a write state machine controlling the first and second voltages. When writing data to a memory cell, the first voltage is changed to a second value that is lower than a first value. When writing data to a memory cell, the second voltage is changed to a third value that is lower than the second value. The write state machine lowers the second voltage to an intermediate value between the second value and the third value and, while maintaining this intermediate value, lowers the first voltage from the first value to the second value. | 08-13-2009 |
| 20090213656 | FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS - A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions. | 08-27-2009 |
| 20090213657 | Electronic Device Comprising Non Volatile Memory Cells and Corresponding Programming Method - A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first select signal and by at least one second select signal generated by a decoder, these columns being associated with at least one program load PL controlled by a logic circuit and suitable for applying a programming pulse to a plurality of cells belonging to the enabled bit-lines, comprising a plurality of discharge transistors, each associated with a corresponding column controlled by a control signal complementary to the control signal of the adjacent discharge transistor. | 08-27-2009 |
| 20090231919 | SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD IN THE SAME - A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder. | 09-17-2009 |
| 20090238000 | SYSTEMS AND DEVICES INCLUDING MULTI-GATE TRANSISTORS AND METHODS OF USING, MAKING, AND OPERATING THE SAME - Disclosed are methods, systems and devices, including a device having a digit line and a plurality of transistors each having one terminal connected to the digit line and another terminal disposed on alternating sides of the digit line. In some embodiments, each transistor among the plurality of transistors comprises a fin. | 09-24-2009 |
| 20090285026 | PROGRAM AND VERIFY METHOD OF NONVOLATILE MEMORY DEVICE - A program and verify method of a nonvolatile memory device, which can minimize the time taken for program and verify operations. The program and verify method includes precharging an output terminal of a block selector to a second level, making the output terminal of the block selector float, and, in the state where the output terminal floats, sequentially applying a program voltage and a verify voltage through a global word line. | 11-19-2009 |
| 20090290420 | PROGRAM METHOD OF NONVOLATILE MEMORY DEVICE - A program method of nonvolatile memory devices, which can solve an under program problem by preventing a drop of a verify voltage in the program, and verify operations. According to an aspect of the method, a program operation is performed on a selected memory cell block. Electric charges charged to a channel of memory cell strings included in unselected memory cell blocks are discharged. A verify operation is performed on the selected memory cell block. | 11-26-2009 |
| 20090296473 | Method of Forming an Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers and Corresponding Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers - The present invention provides an integrated circuit including N1 NAND flash array segments with N2 local bit lines, N1 intra array multiplexers and N2/2 global bit lines. Further, the present invention provides a method of producing an integrated circuit including N1 NAND flash array segments with N2 local bit lines, N1 intra array multiplexers and N2/2 global bit lines. | 12-03-2009 |
| 20090303793 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 12-10-2009 |
| 20100054039 | High speed flash memory - For realizing high speed flash memory, bit line is multi-divided for reducing parasitic capacitance, so that local bit line is quickly discharged when reading a memory cell and multi-stage sense amps are used, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as a local sense amp connecting to the local bit line through a read transistor, a second dynamic circuit serving as a segment sense amp for reading the local sense amp, and a tri-state inverter serving as an amplify circuit of a global sense amp for reading the segment sense amp. When reading data, a cell current difference is converted to a time difference for differentiating low threshold data and high threshold data by the multi-stage sense amps. And a buffered data path is connected to the global sense amp for achieving fast data transfer. Additionally, alternative circuits and memory cell structures are described. | 03-04-2010 |
| 20100142279 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ASSIST GATE - In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision. | 06-10-2010 |
| 20100226180 | MEMORY ARRAY AND METHOD OF OPERATING A MEMORY - A memory array is described, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read. | 09-09-2010 |
| 20100302853 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device includes a high voltage generation unit configured to generate a program voltage and a pass voltage, a block selection unit coupled to the high voltage generation unit through global word lines, a memory cell array coupled to the block selection unit through word lines, a discharge unit coupled to the global word lines and configured to change a level of voltage supplied to the global word lines, and a discharge control unit configured to generate a discharge signal, and transfer the discharge signal to the discharge unit in response to the program voltage. | 12-02-2010 |
| 20100322004 | SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD IN THE SAME - A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder. | 12-23-2010 |
| 20110051516 | Semiconductor Device - A semiconductor device comprises a transistor comprising a gate, a source, a drain, and a gate insulating layer, and an auxiliary line formed over the drain and electrically insulated from the drain. During a turn-off operation of the transistor, voltage to increase a resistance of the drain is supplied to the auxiliary line. | 03-03-2011 |
| 20110170351 | Memory Cell Array of Memory - A memory cell array of a memory comprises a main memory cell array, including local bit lines, word lines and memory cells, and a selected array, including a global bit line, a bit line transistor (BLT) control line, a transistor and a fixed value memory cell. The local bit lines comprise first and second local bit lines. Each memory cell for storing data corresponds and is connected to one local bit line and one word line. The transistor is coupled to the global bit line, first local bit line and BLT control line, and selectively turns on to connect the global bit line to the first local bit line. The fixed value memory cell coupled to the global bit line, second local bit line, and BLT control line is programmed to a fixed value so that a threshold voltage thereof is greater than a threshold voltage of the transistor. | 07-14-2011 |
| 20110188311 | Efficient Memory Sense Architecture - Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups. | 08-04-2011 |
| 20110242891 | OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE - A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells. | 10-06-2011 |
| 20110292730 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS HAVING CONFIGURATION THAT ENABLES PLANE AREA REDUCTION - Various embodiments of a semiconductor integrated circuit apparatus are disclosed. In one exemplary embodiment, the apparatus may include a memory cell array having a plurality of memory cell blocks, a plurality of word line selection sections corresponding to the plurality of memory cell blocks, a block selection unit configured to provide a driving signal to the plurality of word line selection sections for driving the plurality of memory cell blocks, and a plurality of global line groups, each corresponding to one of the plurality of word line selection sections. Each of the global line groups may include a plurality of signal lines configured to provide a voltage signal to the corresponding word line selection section. | 12-01-2011 |
| 20120008398 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a plurality of global word lines, a plurality of transistors configured to transfer voltages of the global word lines to a plurality of local word lines inside a cell block, and a voltage control unit configured to supply a first negative voltage to a global word line of the plurality of global word lines and configured to charge a bulk region of the plurality of transistors with a second negative voltage. | 01-12-2012 |
| 20120044765 | WORD LINE ACTIVATION IN MEMORY DEVICES - Memory devices and methods are disclosed, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address spaces. Each address space has a corresponding configuration control bus. By identifying the address space to which a word line belongs, its appropriate configuration control bus may be selected and the control signals from the selected bus used to select the appropriate potentials for driving the word lines. | 02-23-2012 |
| 20120057406 | FLASH MEMORY APPARATUS - A flash memory apparatus includes a plurality of memory sectors and a plurality of path transistors, and each memory sector has a local low voltage line, and each path transistor corresponds to one of the memory sectors, and the path transistors are installed in an alignment direction of the memory sectors. One of the path transistors is installed between two adjacent memory sectors, whose gate is connected to a sector select signal line, and whose drain is connected to the local low voltage line of the corresponding memory sector, and whose source is connected to a global low voltage line, and the global low voltage line is installed at an angle substantially equal to 90 degrees across the gate, so as to save the area occupied by peripheral circuits in the path transistors, and lower the manufacturing cost of the flash memory apparatus. | 03-08-2012 |
| 20120106253 | THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY - A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased. | 05-03-2012 |
| 20120182804 | ARCHITECTURE FOR A 3D MEMORY ARRAY - Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines. | 07-19-2012 |
| 20120188822 | CONTROL VOLTAGE GENERATION CIRCUIT AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME - A control voltage generation circuit for generating a control voltage for controlling a high-voltage transistor includes an input node configured to receive a first enable signal; an output node configured to generate the control voltage, a transferor configured to transfer a voltage of the input node to the output node in response to a transfer signal, an enabling voltage driver configured to drive the output node with a high voltage when the first enable signal is enabled, and a disabling voltage driver configured to drive the output node with a negative voltage when a second enable signal is enabled in a negative mode. | 07-26-2012 |
| 20120262990 | MEMORY DEVICE - A memory device comprises a main memory array having a plurality of bit lines, and a select array having a plurality of transistors coupled to the bit lines. Wherein one of the plurality of transistors is electrically programmed to a threshold voltage greater than a threshold voltage of another one of the plurality of transistors. | 10-18-2012 |
| 20130121078 | THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES AND A SINGLE-SIDED WORD LINE ARCHITECTURE - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line. | 05-16-2013 |
| 20130170299 | SHARING LOCAL CONTROL LINES ACROSS MULTIPLE PLANES IN A MEMORY DEVICE - Memory devices, methods for accessing a memory cell, and memory systems are disclosed. One such memory device includes a plurality of planes of memory cells. Each plane of memory cells includes series strings of memory cells that each have a select gate drain transistor. Control gates of corresponding select gates are coupled together by a shared local control line. Each of a plurality of global control lines are coupled to their corresponding local control line with only a single global select gate. | 07-04-2013 |
| 20130176786 | 2-TRANSISTOR FLASH MEMORY AND PROGRAMMING METHOD OF 2-TRANSISTOR FLASH MEMORY - Disclosed is a 2-transistor flash memory that includes a memory cell array, a row driver, a read/write circuit, a charge pump generating a high voltage, and control logic configured to transfer the high voltage to the row driver, the read/write circuit, and the memory cell array. If programming, the row driver and the read/write circuit apply voltages such that a control gate of a cell transistor in an unselected memory cell on a different row from a selected memory cell is floated. | 07-11-2013 |
| 20130336064 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. | 12-19-2013 |
| 20140092684 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. | 04-03-2014 |
| 20140098611 | BIASING SYSTEM AND METHOD - Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system is in a non-operation state. The access device is selected when the memory system is in the non-operation state, and the access device is deselected when the memory system is in an other state. Further embodiments provide, for example, a method that includes coupling a global access line to a local access line, biasing the local access line to a voltage other than a negative supply voltage while a memory device is in a first state and uncoupling the global access line from the local access line while the memory device is in an other state. | 04-10-2014 |
| 20140286100 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line. | 09-25-2014 |
| 20150009755 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. | 01-08-2015 |
| 20150340096 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF - A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group. | 11-26-2015 |
| 20150380090 | Nonvolatile Memories Having Data Input/Output Switches and Data Storage Devices and Methods Using the Same - A nonvolatile memory includes a memory cell array including a plurality of memory cells, a pad configured to be connected to a data input/output line, and an input/output circuit configured to receive data to be programmed in the memory cell array and to transmit data read from the memory cell array. The nonvolatile memory further includes a switch configured to couple and decouple the pad and the input/output circuit responsive to a switch control signal and a control circuit configured to generate the switch control signal responsive to a chip enable signal. Data storage devices and methods using such nonvolatile memories are also described. | 12-31-2015 |
| 20160020217 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal. | 01-21-2016 |
| 20160035422 | TRANSISTOR AND CIRCUIT USING SAME - A transistor is described including a fly-over conductor. The transistor has a gate, a channel and a source/drain terminal. The fly-over conductor is disposed over the source/drain terminal. A circuit is connected to the fly-over conductor to apply a bias voltage tending to offset effects on the transistor of charge trapped in insulating material. A word line driver can include a transistor with a fly-over conductor. | 02-04-2016 |
