| Entries |
| Document | Title | Date |
|---|
| 20080205027 | ASSEMBLY OF TWO PARTS OF AN INTEGRATED ELECTRONIC CIRCUIT - A process for assembling two parts of an integrated electronic circuit has two successive steps. During a first step, the two circuit parts are made into a single unit by molecular bonding, realized on respective application surfaces of the two parts. During a second step, electrical connections are formed from connection portions already present in the application surfaces of the two circuit parts. The connections formed extend across the bonding interface, and are compatible with a high reliability and a high level of integration of the circuit. | 08-28-2008 |
| 20080225505 | Method of producing a MEMS device - A method of producing a MEMS device removes the bottom side of a device wafer after its movable structure is formed. To that end, the method provides the device wafer, which has an initial bottom side. Next, the method forms the movable structure on the device wafer, and then removes substantially the entire initial bottom side of the device wafer. Removal of the entire initial bottom side effectively forms a final bottom side. | 09-18-2008 |
| 20080247148 | Semiconductor Device - A semiconductor device | 10-09-2008 |
| 20080247149 | CHIP PACKAGE STRUCTURE - A chip package structure including a carrier, a chip, and an underfill layer is disclosed. The carrier has a number of bumps disposed thereon. The chip has an active surface. The chip is flip-chip bonded and electrically connected to the carrier through the bumps such that the active surface of the chip faces the carrier. The underfill layer is disposed on the carrier between the chip and the carrier such that a gap is maintained between the underfill layer and the chip. | 10-09-2008 |
| 20080291655 | Wiring substrate, semiconductor device package including the wiring substrate and methods of fabricating the same - Provided is a wiring substrate, a semiconductor device package including the wiring substrate, and methods of fabricating the same. The semiconductor device package may include a wiring substrate which may include a base film. The base film may include a mounting region and a non-mounting region. The wiring substrate may further include first wiring patterns on the non-mounting region and extending into the mounting region, second wiring patterns on the first wiring patterns of the non-mounting region, and an insulating layer on the non-mounting region, and a semiconductor device which may include bonding pads. At least one of side surfaces of the second wiring patterns adjacent to the mounting region may be electrically connected to at least one of the bonding pads of the semiconductor device. | 11-27-2008 |
| 20090002973 | Mount Board and Electronic Device - An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board | 01-01-2009 |
| 20090002974 | Power Converter Unit - A power converter unit has a metal case; a power module having a plurality of power semiconductor devices that is provided inside the metal case; a gate drive circuit board having a circuit for driving the plurality of the power semiconductor devices that is mounted on the power module; a voltage sensor that is mounted on the gate drive circuit board; a metal plate for electrically connecting the metal case with the gate drive circuit board; screws and soldered parts for fixing the metal plate to the gate drive circuit board; a first wiring that is set up on the gate drive circuit board for electrically connecting the voltage sensor with the soldered parts; and a second wiring that is set up on the gate drive circuit board for electrically connecting the screws and the soldered parts. | 01-01-2009 |
| 20090016040 | IC device and method of manufacturing the same - An IC device includes a base plate, a plurality of terminal pins, a functional component such as an IC chip, and a resin package for protection of the functional component. The base plate is generally flat and formed with a plurality of through-holes into which the terminal pins are inserted. The functional component, disposed away from the base plate, is mounted on a printed circuit board to be electrically connected to at least one of the terminal pins. While enclosing the functional component, the resin package is held in contact with the upper surface of the base plate. | 01-15-2009 |
| 20090109645 | Power Semiconductor Module Comprising Load Connection Elements Applied To Circuit Carriers - A power semiconductor module is disclosed including a housing for receiving at least one essentially board-type circuit carrier, the circuit carrier being provided with a metallization on at least one part of its surface and being populated with and electrically connected to at least one power semiconductor, rigid, integral and essentially straight load connection elements being applied on the metallized part of the metallized surface of the circuit carrier, which load connection elements are electrically and mechanically fixedly connected to the circuit carrier by one of their ends and project essentially perpendicularly into the housing interior, separate connection terminal elements for electrical conduct-making being placed onto the free end of the load connection elements. | 04-30-2009 |
| 20090109646 | PACKAGED GALLIUM NITRIDE MATERIAL TRANSISTORS AND METHODS ASSOCIATED WITH THE SAME - The invention provides semiconductor material (e.g., gallium nitride material) devices (e.g., transistors) and methods associated with the same. The devices may be supported within a package that is formed, in part, of a polymeric material. In other embodiments, the devices may be mounted to a support (e.g., circuit board) and a polymeric material may encapsulate a portion of the device extending from the support. | 04-30-2009 |
| 20090141472 | Adhesive composition for die bonding in semiconductor assembly, adhesive film prepared therefrom, device including the same, and associated methods - An adhesive film for semiconductor assembly includes a binder portion | 06-04-2009 |
| 20090161336 | TWO-BEAM SEMICONDUCTOR LASER APPARATUS - A two-beam semiconductor laser device | 06-25-2009 |
| 20090168390 | DIRECTING THE FLOW OF UNDERFILL MATERIALS USING MAGNETIC PARTICLES - Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate and a die, and coupling the die to the substrate, wherein a gap remains between the die and the substrate. The method also includes placing an underfill material on the substrate and delivering at least part of the underfill material into the gap. The method also includes controlling the flow of the underfill material in the gap using magnetic force. Other embodiments are described and claimed. | 07-02-2009 |
| 20090168391 | SUBSTRATE FOR MOUNTING DEVICE AND METHOD FOR PRODUCING THE SAME, SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE SAME, AND PORTABLE APPARATUS PROVIDED WITH THE SAME - A substrate for mounting a device comprises: an insulating resin layer; a plurality of projected electrodes that are connected electrically to a wiring layer provided on one major surface of the insulating resin layer, and that project toward the insulating resin layer from the wiring layer; and a counter electrode provided at a position corresponding to each of the plurality of projected electrodes on the other major surface of the insulating resin layer. Among the projected electrodes, a projected length of part of the projected electrodes is smaller than that of the other projected electrodes; and the projected electrode and the counter electrode corresponding thereto are capacitively-coupled, and the projected electrode and the counter electrode are connected electrically. | 07-02-2009 |
| 20090175022 | MULTI-LAYER PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for allowing an easier electric connection between layers of a multi-layer package structure using a metal pin fabricated based on semiconductor device processes is provided. A metal pin having a high aspect ratio is formed on a lower substrate, while a via hole is formed in an upper substrate. The metal pin is inserted into the via hole and adhered together to make an electric connection between the lower and upper substrates. The metal pin is obtained by patterning a thick photoresist material and plating a material thereon. The metal pin may have a core member obtained by performing a plating process on the surface of a patterned polymer based pin. Solder or gold is used for adhesion and electric connection between the signal line and the metal pin. The above electric connection method can be simpler and have improved structural stability compared with the typical connection method. | 07-09-2009 |
| 20090175023 | INTERPOSER AND METHOD FOR MANUFACTURING INTERPOSER - An interposer includes an inorganic insulating layer, a first wiring formed in or on a surface of the inorganic insulating layer, an organic insulating layer formed over the inorganic insulating layer and on the first wiring, a second wiring formed on the organic insulating layer, and a conductor portion connecting the first wiring and the second wiring. | 07-09-2009 |
| 20090196009 | Semiconductor module, wiring board , and wiring method - A semiconductor module includes a plurality of rectangular shaped semiconductor devices which are arranged in two rows such that each pair of adjacent semiconductor devices is in orientations differed by 90 degrees from each other. A plurality of wirings connect the semiconductor devices included in one of the two rows to the semiconductor devices included in the other row such that the semiconductor devices arranged in the same orientations are connected to each other. | 08-06-2009 |
| 20090196010 | DEVICE MOUNTING BOARD, AND SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREFOR - A device mounting board includes: an insulating resin layer; a wiring layer provided on one main surface of the insulating resin layer; and a bump electrode, electrically connected to the wiring layer, which is protruded from the wiring layer toward the insulating resin layer. Asperities are formed on the side surface of the bump electrode and the surface roughness of the side surface of the bump electrode is greater than that of the top surface of the bump electrode. | 08-06-2009 |
| 20090196011 | DEVICE MOUNTING BOARD AND MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR MODULE - A device mounting board includes: an insulating resin layer; a wiring layer disposed on one main surface of the insulating resin layer; and a bump electrode connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A side surface of the bump electrode is curved inwardly toward the center axis of the bump electrode as viewed in a cross section including the center axis of the bump electrode, and the radius of curvature of the side surface changes continuously from a wiring layer end to a head end of the bump electrode. | 08-06-2009 |
| 20090207580 | Submount and Method of Manufacturing the Same - A submount with an electrode layer having excellent wettability in soldering and method of manufacturing the same are disclosed. A submount ( | 08-20-2009 |
| 20090231826 | Method of forming a permanent carrier and spacer wafer for wafer level optics and associated structure - A carrier wafer for wafer level fabrication of imager structures comprising a substrate with trenches corresponding to locations of imager arrays on an imager wafer. A method of fabricating such a carrier wafer and a method of fabricating an imager module employing such a carrier wafer are also provided. | 09-17-2009 |
| 20090231827 | INTERPOSER AND METHOD FOR MANUFACTURING INTERPOSER - An interposer and a method of manufacturing the same are provided. The interposer includes a substrate and a conductor portion formed inside the substrate. At least one insulating layer is formed on the substrate and on the conductor portion. A signal wiring portion is formed inside the insulating layer or on the insulating layer. A first pad is configured to receive an electronic part, and is formed on an outermost insulating layer of the at least one insulating layer. A connection conductor is formed in the at least one insulating layer so as to electrically connect the conductor portion to the first pad. | 09-17-2009 |
| 20090251878 | Electronic Assembly and Method for Making Electronic Devices - An electronic assembly includes: a circuit substrate with a first mounting surface that has a plurality of spaced apart first mounting regions and at least one second mounting region spaced apart from the first mounting regions; a plurality of first electronic components mounted on the first mounting regions, respectively; and at least one dummy of a non-electronic component mounted on the second mounting region and having dimensions simulating those of the first electronic components. A method for making electronic devices is also disclosed. | 10-08-2009 |
| 20090251879 | DIE THINNING PROCESSES AND STRUCTURES - Microelectronic dies are thinned according to a variety of approaches, which may include bonding the dies to a substrate under vacuum, disposing a film over the dies and the substrate, and/or changing a center of pressure during thinning. | 10-08-2009 |
| 20090273913 | CIRCUIT ARRANGEMENT HAVING TWO SEMICONDUCTOR SWITCHING ELEMENTS AND ONE FREEWHEELING ELEMENT - One aspect is a circuit arrangement including a first semiconductor switching element, a second semiconductor switching element connected in series with the first semiconductor switching element and a freewheeling element connected in parallel with the second semiconductor switching element. | 11-05-2009 |
| 20090273914 | Apparatus and methods of forming an interconnect between a workpiece and substrate - Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed. | 11-05-2009 |
| 20090296364 | WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE - A wiring substrate includes: an insulating layer; a wiring formed on the insulating layer; and a solder resist layer formed on the insulating layer so as to cover at least a portion of the wiring, the solder resist layer being constituted by a plurality of layers, wherein the plurality of layers contain fillers of different grain diameters, a layer thickness of an innermost layer for constituting the plurality of layers is thicker than a layer thickness of the wiring, and a grain diameter of the filler contained in the innermost layer is smaller than a shortest interval between adjacent lines of the wiring. | 12-03-2009 |
| 20100020524 | PROTECTIVE PACKAGE FOR AN ELECTROMECHANICAL MICRO-SYSTEM COMPRISING A WIRING RELAY - The field of the invention is that of the wiring of electromechanical micro-systems also called MEMS (the acronym standing for Micro Electro Mechanical Systems) and more particularly micro-systems carrying out measurements of physical quantities such as for example micro-gyrometers, micro-accelerometers or pressure micro-sensors. More precisely the subject of the invention is a wiring relay for an electromechanical micro-system enclosed in a protective package. A first end of a wire bond of electrically conducting material is fixed to the micro-system electrical contact. The relay is fixed to at least one internal wall. The relay consists of an electrically insulating material. According to the invention, it comprises tracks of electrically conducting material, and one track is linked electrically with at least one internal electrical contact and with a second end of a wire bond. | 01-28-2010 |
| 20100091477 | PACKAGE, AND FABRICATION METHOD FOR THE PACKAGE - A package includes a conductive base plate; a ceramic wall configured to house a semiconductor device and a circuit board disposed adjoining of the semiconductor device, the ceramic wall configured to be disposed on the conductive base plate, the ceramic wall configured to include a frame shape having a screw hole in four corners; a metal seal ring configured to include a framed shape and be disposed on the ceramic wall; and a ceramic cap configured to be disposed on the metal seal ring, and the ceramic wall is screwed to the conductive base plate through the screw hole, and the package can radiate heat satisfactory in the heat generation from the semiconductor device, and can improve reliability, and can be applied to the high frequency of the microwave/millimeter wave/sub-millimeter wave band. | 04-15-2010 |
| 20100142174 | INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming an indent, having a flange and an indent side, from a peripheral region of the active side; and forming a conformal interconnect, having an elevated segment, a slope segment, and a flange segment, over the indent. | 06-10-2010 |
| 20100157568 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices. | 06-24-2010 |
| 20100172117 | POWER MODULE - Provided is a power module capable of welding a snubber capacitor without causing melting damage to a resin housing by welding heat. When leads of a snubber capacitor are respectively welded to upper surfaces of the specific portions of a P-pole bus bar and an N-pole bus bar, the welding heat generated at the specific portions of the P-pole bus bar and the N-pole bus bar is respectively radiated from openings, through which the lower surfaces of the specific portions of the P-pole bus bar and the N-pole bus bar are exposed. As a result, the snubber capacitor can be later appended by welding without causing melting damage to the resin housing due to the welding heat. During welding, a separate cooling head is inserted into the openings to forcibly cool the lower surfaces of the specific portions of the P-pole bus bar and the N-pole bus bar respectively, so that the melting damage to a resin housing can be more reliably avoided. | 07-08-2010 |
| 20100254113 | ELECTRONIC BOARD, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE - An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material. | 10-07-2010 |
| 20100271797 | CAR FAN CONTROLLER - This invention patent is a utility type of car fan controller. The controller has a housing and inside the housing is a circuit. The housing has a top cover forming a cavity and flat bottom plate. The circuit has a circuit board and an adjustment device with other electronic components. The circuit board has a socket connector and a wire harness connector. The top cover has socket connector aligned with socket connector opening. The top cover also has a wire harness connector aligned to wire harness connector socket. The modular practical new type of invention design facilitates faster assembly and more convenient flexible use. | 10-28-2010 |
| 20100296261 | ELECTRICAL CONNECTORS FOR OPTOELECTRONIC DEVICE PACKAGING - Packaged optoelectronic device include a first barrier layer having a plurality of feedthrough apertures communicating with at least one electrode layer of the device, and a plurality of conductive patches disposed on at least one of the plurality of feedthrough apertures for electrically connecting the device to a power supply. Each conductive patch includes a conductive metal surface layer and a non-conducting surface layer having an opening exposing the metal surface layer. | 11-25-2010 |
| 20110019386 | Multimode Signaling on Decoupled Input/Output and Power Channels - A multimode system with at least two end points may include a multimode signaling path that, in some embodiments, is a multimode cable or a multimode board and is pluggably connectable to packages at each end point. Each end point may include a processor die package coupled to a socket. The socket may also receive a connector that couples the cable to the package. Power supply signals and input/output signals may be decoupled at each end point. | 01-27-2011 |
| 20110026236 | GLASS LAMINATE, DISPLAY PANEL WITH SUPPORT, METHOD FOR PRODUCING GLASS LAMINATE AND METHOD FOR MANUFACTURING DISPLAY PANEL WITH SUPPORT - Disclosed is a glass laminate comprising a thin glass substrate having a first main surface and a second main surface, a supporting glass substrate having a first main surface and a second main surface, and a resin layer and an outer frame layer arranged between the thin glass substrate and the supporting glass substrate. The resin layer is fixed to the first main surface of the supporting glass substrate and is in close contact with the first main surface of the thin glass substrate, while having easy releasability from the first main surface of the thin glass substrate. The outer frame layer surrounds the resin layer on the first main surface of the supporting glass substrate so that the outside air does not come into contact with the resin layer. | 02-03-2011 |
| 20110103034 | ELECTRONIC CHIP AND SUBSTRATE PROVIDING INSULATION PROTECTION BETWEEN CONDUCTING NODES - An electronic chip includes a plurality of conducting pins and a plurality of insulating blocks. The conducting pins are disposed on an outer side of the electronic chip to provide electrical connections between the electronic chip and an external circuit. Each of the insulating blocks is disposed between two adjacent conducting pins. | 05-05-2011 |
| 20110110068 | COMPOSITE SEMICONDUCTOR DEVICE - To provide a composite semiconductor device capable of preventing malfunction of preventing electrical circuits and contributing to miniaturization of a power converter. | 05-12-2011 |
| 20110176288 | ADHESIVE COMPOSITION, CIRCUIT CONNECTING MATERIAL, CONNECTING STRUCTURE FOR CIRCUIT MEMBER, AND SEMICONDUCTOR DEVICE - The adhesive composition of the invention comprises a thermoplastic resin, a radical polymerizing compound, a radical polymerization initiator and a radical polymerization regulator. According to the present invention it is possible to provide an adhesive composition, a circuit connecting material, a connection structure for a circuit member and a semiconductor device whereby curing treatment can be carried out with sufficient speed at low temperature, curing treatment can be carried out with a wide process margin, and adequately stable adhesive strength can be obtained. | 07-21-2011 |
| 20110182048 | ELECTRONIC ASSEMBLY AND METHOD FOR ITS MANUFACTURE - An electronic assembly has at least one conductor substrate carrying components, which conductor substrate is surrounded by a mechanical protection. The conductor substrate is encased using a molding compound as a mechanical protection and is contacted by at least one intrinsically stiff, spring-elastic electrical connection conductor, the connection conductor being embedded in the molding compound, at least in sections. | 07-28-2011 |
| 20110216518 | Self-Cooled Thyristor Valve - The present invention relates to a self-cooled thyistor device for ultra-high voltage fault current limiter. a self-cooled thyristor valve, it adopts horizontal structure consisted by frames, frames is divided into upper and below two spaces by crossbeams, the bottom of frames is supported by insulators. There is a cross plate between two vertical said frames, the cross plate mounts resistors connect with a high potential plate and capacitor through two wires. There is a thyistor string in said frame upper space, which is constituted of thyistors and cooler series. The thyistor string is compressed tightly by press-fit mechanism, thyistor string crosses current transformers. There are high potential plates on both sides of the thyistor, the number of the potential plates is equal to that of thyistor. One side of the high potential plates links frames, said current transformers connects with high potential plates. There are capacitors and resistors connected with the bottom plate of said frames in the below space. The small and well-structured invention meets the requirement of the energy on continuous trigger condition, improves the global reliability of thyristor valve. | 09-08-2011 |
| 20110235304 | IC PACKAGE STIFFENER WITH BEAM - Various exemplary embodiments relate to a stiffener for use with and integrated circuit (IC). The stiffener can be attached to the IC, and can utilize a planar portion and one or more beam portions that project from the planar portion at a non-zero angle. The stiffener can alternatively include a frame formed of beam portions that are adjacent the sides of the IC. The stiffener can provide added stiffness to the IC package to resist warping of the IC during soldering. | 09-29-2011 |
| 20110267796 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a matrix and a semiconductor element bonded to the matrix via a bonding layer. The bonding layer includes a first layer and a second layer having a viscosity lower than a viscosity of the first layer at a bonding temperature. The first layer has a portion in which an end of the first layer is set further back to an inside than an end of the semiconductor element. At least a part of the portion set back to the inside is filled with a part of the second layer extruded from a periphery of the first layer to an outside. | 11-03-2011 |
| 20110273861 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor mounting substrate, a mother case having an opening and housing the semiconductor mounting substrate, a plurality of securing members provided along a rim of the mother case, a screw terminal, and a lid member. The screw terminal has a flat plate portion, an insertion portion extending from the flat plate portion, and a terminal bottom portion, is secured to the securing members by insertion of the insertion portion between adjacent securing members, and is electrically connected to the semiconductor mounting substrate on the terminal bottom portion side. The lid member closes the opening with the screw terminal secured to the securing members. The screw terminal is bent such that the flat plate portion faces an upper surface of the lid member closing the opening. The semiconductor device that can achieve reduction in size of the entire device is obtained. | 11-10-2011 |
| 20110279996 | SEMICONDUCTOR ASSEMBLY AND MULTILAYER WIRING BOARD - A multilayer wiring board is inhibited from being warped when flip-chip bonding a semiconductor device to the multilayer wiring board, thereby increasing the reliability of connecting the semiconductor assembly to a motherboard. | 11-17-2011 |
| 20110292632 | METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE THEREFOR - A semiconductor component and a method of manufacturing the semiconductor component that reduces parasitic elements. A semiconductor chip is coupled to a semiconductor chip receiving area of a support structure. The semiconductor chip has at least two power semiconductor devices. A drain contact of a first power semiconductor device is coupled to a source contact of a second power semiconductor device and the drain and source contacts of the first and second power semiconductor devices are joined to the semiconductor chip receiving area. Another semiconductor chip may be bonded to a second semiconductor chip receiving area of the support structure. An energy storage element may be coupled between the source contact of the first power semiconductor device and the drain contact of the second semiconductor device. A protective structure may be formed over the semiconductor chips and the energy storage element. | 12-01-2011 |
| 20110292633 | METHOD OF MANUFACTURING A PACKAGE CARRIER FOR ENCLOSING AT LEAST ONE MICROELECTRONIC ELEMENT AND METHOD OF MANUFACTURING A DIAGNOSTIC DEVICE - A package enclosing at least one microelectronic element ( | 12-01-2011 |
| 20110299265 | Power Module, Power Converter Device, and Electrically Powered Vehicle - A power module and a power converter device including the power module include: two base plates with their main surfaces facing each other; a semiconductor circuit unit disposed between the two base plates; a connecting member that is connected to the two base plates and forms a housing region in which the semiconductor circuit unit is housed; and an insulating member that is placed between the base plate and the semiconductor circuit unit and secures electrical insulation of the base plate and the semiconductor circuit unit. A rigidity or thickness of the connecting member is less than a rigidity or thickness of the base plate. | 12-08-2011 |
| 20110310585 | Power Semiconductor Device and Power Conversion Device - A power semiconductor device includes a plurality of power semiconductor elements constituting upper and lower arms of an inverter circuit, a first sealing member sealing the plurality of power semiconductor elements, a positive electrode-side terminal and a negative electrode-side terminal each connected with any of the plurality of power semiconductor elements and protruding from the first sealing member, a second sealing member sealing at least a part of the positive electrode-side terminal and at least a part of the negative electrode-side terminal, and a case in which the power semiconductor elements sealed with the first sealing member are housed. | 12-22-2011 |
| 20120002392 | ELECTRO-STATIC DISCHARGE PROTECTION FOR DIE OF A MULTI-CHIP MODULE - Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance. | 01-05-2012 |
| 20120026716 | PACKAGE ASSEMBLY AND METHOD OF TUNING A NATURAL RESONANT FREQUENCY OF A PACKAGE - A package assembly comprises an electronic device; a package body; at least a first plurality of leads having a first geometrical shape and a second plurality of leads having a second geometrical shape, protruding from the package body; each of the first plurality of leads being located in corners of the package body; or the first and the second plurality of leads arranged in at least a first row and a second row located in parallel to the first row; each of the rows comprising at least two leads; the first row being transformable into the second row by mirroring the first row along a symmetry plane of the package body; each of the first plurality of leads having the first geometrical shape different from the second geometrical shape. | 02-02-2012 |
| 20120106120 | TRANSMISSION LINE FOR ELECTRONIC CIRCUITS - A transmission line formed in a device including a stack of first and second chips having their front surfaces facing each other and wherein a layer of a filling material separates the front surface of the first chip from the front surface of the second chip, this line including: a conductive strip formed on the front surface side of the first chip in at least one metallization level of the first chip; and a ground plane made of a conductive material formed in at least one metallization level of the second chip. | 05-03-2012 |
| 20120113615 | SYSTEMS AND METHODS FOR IMPROVED CHIP DEVICE PERFORMANCE - Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assists in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assists in impedance matching. | 05-10-2012 |
| 20120127689 | INTEGRATED PACKAGE CIRCUIT WITH STIFFENER - The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. | 05-24-2012 |
| 20120155055 | SEMICONDUCTOR CHIP ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly. | 06-21-2012 |
| 20120176763 | CRYSTAL OSCILLATOR - A crystal oscillator is configured by accommodating a crystal blank that functions as a crystal unit and an IC chip that includes at least an oscillator circuit using the crystal blank into a container in an integrated manner. In the IC chip, the oscillator circuit is connected to the crystal unit via a pair of crystal connecting terminals, an output from the oscillator circuit is supplied to a plurality of output buffers. In relation to the crystal connecting terminal having a phase opposite to that of an output from the on/off controllable output buffer, an output terminal of this output buffer is disposed farther than an output terminal of the output buffer that is not subjected to the on/off control. | 07-12-2012 |
| 20120176764 | METHOD FOR GENERATING AN ELECTRONIC SYSTEM, METHOD FOR GENERATING A FREEFORM SURFACE HAVING SUCH A SYSTEM, AND ELECTRONIC SYSTEM AND FREEFORM SURFACES HAVING SUCH A SYSTEM - The invention relates to a method for generating an electronic system for application to freeform surfaces, a method for producing freeform surfaces having an electronic system, and an electronic system and a combination of a freeform surface having at least one such system. According to the invention, an elastic interconnect device having an elastic substrate and an elastic, fanned-out contact structure with contact surfaces comprised of conductor lines is generated first. Then, electronic components are mounted on the interconnect device. Finally, the interconnect device is encapsulated. If a freeform surface with an electronic system is to be generated, the electronic system produced in this way is then mounted on the previously provided freeform surface. | 07-12-2012 |
| 20120206899 | SEMICONDUCTOR SWITCH - According to one embodiment, a semiconductor switch includes a main element including a switching element and an antiparallel diode, and a reverse voltage application circuit. The reverse voltage application circuit includes an auxiliary electric-power supply, a high-speed free wheeling diode, an auxiliary element, and a capacitor. The high-speed free wheeling diode comprises a plurality of diodes connected in series. | 08-16-2012 |
| 20120250286 | Apparatus and Method for Increasing Bandwidths of Stacked Dies - A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies. | 10-04-2012 |
| 20120293977 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a package structure is provided. A substrate having an upper surface and a lower surface opposite to each other and an opening communicating the surfaces is provided. An electronic device is configured in the opening. An adhesive layer and a patterned metal layer located on the adhesive layer are laminated on the lower surface and expose a bottom surface of the electronic device. A heat-dissipating column is formed on the bottom surface exposed by the adhesive layer and the patterned metal layer and connects the patterned metal layer and the bottom surface. A first and a second laminated structures are laminated on the upper surface of the substrate and the patterned metal layer, respectively. The first laminated structure covers the upper surface of the substrate and a top surface of the electronic device. The second laminated structure covers the heat-dissipating column and the patterned metal layer. | 11-22-2012 |
| 20130016492 | DUAL-AXIS HINGE STRUCTURE AND ELECTRIC DEVICE HAVING THE SAMEAANM WANG; Chun-WenAACI Tainan CityAACO TWAAGP WANG; Chun-Wen Tainan City TWAANM CHANG; Shan-FengAACI Taoyuan CountyAACO TWAAGP CHANG; Shan-Feng Taoyuan County TW - A dual-axis hinge structure and electric device having the same are provided, and the dual-axis hinge structure includes a hinge base having a pushed portion, a first pivot portion having a first cam and a first shaft, a second pivot portion having a second cam and a second shaft, and a restoring member connected both the first pivot portion and the second pivot portion. The first shaft is pivoted on the hinge base, and the first cam is fixed on the first shaft, and the first cam is contacted with one lateral side of the pushed portion. The second shaft is parallel to the first shaft, and is pivoted on the hinge base, and the second cam is fixed on the second shaft, and the second cam is contacted with another lateral side of the pushed portion. | 01-17-2013 |
| 20130027899 | EMBEDDED PASSIVE INTEGRATION - System and method for embedded passive integration relating to a multi-chip packaged device. The packaged device includes a capacitance layer that is configured for electrical coupling to a power supply and to a reference power supply. Further, the capacitance layer is configured for filtering the power supply and providing a filtered power supply. A semiconductor layer including a logic device is configured for electrical coupling to the filtered power supply. | 01-31-2013 |
| 20130050977 | HOUSING AND PORTABLE ELECTRONIC DEVICE USING SAME - A housing for a portable electronic device is transparent and U-shaped. The housing includes a first section, a second section opposite to the first section, and a connection portion connecting the first section to the second section. | 02-28-2013 |
| 20130058067 | SYSTEM WITH A HIGH POWER CHIP AND A LOW POWER CHIP HAVING LOW INTERCONNECT PARASITICS - An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system. | 03-07-2013 |
| 20130058068 | POWER CONVERTER PERMITTED TO BE REDUCED IN SIZE AND MANUFACTURED AT DECREASED COST - A power converter equipped with a semiconductor stack made up of semiconductor modules, bus bars coupled to power terminals of the semiconductor modules, a capacitor, and an input terminal table. The capacitor is disposed in alignment with a first direction in which the semiconductor modules are stacked. The capacitor has a first end and a second end opposed to the first end in a second direction in which the power terminals extend from the semiconductor modules. The first end faces in the second direction. The input terminal table is located near the second end of the capacitor. This structure permits the power converter to be reduced in size and produced at a decreased cost. | 03-07-2013 |
| 20130128488 | Lithium Battery, Method for Manufacturing a Lithium Battery, Integrated Circuit and Method of Manufacturing an Integrated Circuit - A lithium battery includes a cathode, an anode including a component made of silicon, a separator element disposed between the cathode and the anode, an electrolyte, and a substrate. The anode is disposed over the substrate or the anode is integrally formed with the substrate. | 05-23-2013 |
| 20130128489 | DEVICE HOUSING PACKAGE AND ELECTRONIC APPARATUS EMPLOYING THE SAME - A device housing package includes a base body ( | 05-23-2013 |
| 20130155641 | RELAY MODULE - Disclosed herein is an improved relay for replacing an electro-mechanical relay and converting the original electro-mechanical relay to a solid state relay. The improved relay includes a housing module having an interior. The interior includes a plurality of existing relay tabs and wires. The wires electrically connect the tabs to a connection member. The invention also includes a solid state relay member having a solid state relay module. The module includes a plurality of solid state relay contacts, each corresponding to the existing tabs. The plurality of solid state relay contacts are mounted on, for example, a PC board and adapted for connection to the housing module connection member. Additionally, the existing relay includes a power tab and the wires and connection member are adapted to provide power to the solid relay module for powering each of the solid state relay contacts. | 06-20-2013 |
| 20130155642 | MODIFIED TRANSISTOR OUTLINE (TO)-CAN ASSEMBLY FOR USE IN OPTICAL COMMUNICATIONS AND A METHOD - A modified TO-can assembly is provided that has greater versatility with respect to spatial constraints than known TO-can assemblies and that is suitable for use in a wider range of applications than known TO-can assemblies. The modified TO-can assembly has a receptacle that has been modified to receive an optical fiber through its side instead of through its end. Within the TO-can assembly, the optical path is folded in order to couple the light between the optoelectronic component of the TOSA or ROSA and the end of the optical fiber. The combination of these features provides the modified TO-can assembly with a compact profile that makes it more versatile with respect to spatial constraints and therefore suitable for use in a wider range of applications. | 06-20-2013 |
| 20130176703 | Thermally-Insulated Micro-Fabricated Atomic Clock Structure and Method of Forming the Atomic Clock Structure - A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to −40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell. | 07-11-2013 |
| 20130250541 | ELECTRONIC DEVICE HAVING SENSOR WINDOW COVER - An electronic device includes a housing defining an opening, a signal receiving unit received in the housing, a sensor window cover secured to the opening and corresponding to the signal receiving unit, and a stopping mechanism. The stopping mechanism includes a resisting member secured to the sensor window cover, a first stopping member and a second stopping member arranged on opposite sides of the opening. The resisting member defines a receiving portion. The receiving portion receives the first stopping member to allow the sensor window cover to be secured to the opening, and abuts the second stopping member to prevent the sensor window cover from being secured to the opening when the sensor window is installed reversely. | 09-26-2013 |
| 20130279145 | GROUP III-N NANOWIRE TRANSISTORS - A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions. | 10-24-2013 |
| 20130308291 | ROTATING RECTIFIER ASSEMBLY BUS BAR - A rectifier assembly includes a diode pack. A bus bar includes a first layer electrically connected to the diode pack. The first layer has a first yield strength and a first coefficient of thermal expansion. A second layer of copper is joined to the first layer and includes a second yield strength less than the first yield strength. In one example, the second layer has a second coefficient of thermal expansion within 5% of the first coefficient of thermal expansion. | 11-21-2013 |
| 20140029234 | RELIABLE SURFACE MOUNT INTEGRATED POWER MODULE - A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto. | 01-30-2014 |
| 20140071652 | TECHNIQUES FOR REDUCING INDUCTANCE IN THROUGH-DIE VIAS OF AN ELECTRONIC ASSEMBLY - An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly. | 03-13-2014 |
| 20140078711 | ULTRASONIC WELDING - The described embodiments relate generally to ultrasonic welding and more particularly to performing an ultrasonic welding operation while rotating one part relative to a mating part. A non-uniform energy director can be disposed along a mating surface of a first part. The energy director can maintain a constant cross-sectional area while having a smaller height near a pivot point for the rotation and a larger height away from the pivot point. The varying height of the energy director can allow the tip of the energy director to come in contact with a second part rotating relative to the first part at approximately the same time during the ultrasonic welding process. | 03-20-2014 |
| 20140140034 | POWER CONVERSION APPARATUS - A power conversion apparatus includes at least one semiconductor module including a main electrode terminal, a capacitor including at least one capacitor terminal member connected to the main electrode terminal of the semiconductor module, and an apparatus case housing the semiconductor module and the capacitor. The capacitor includes a capacitor body disposed in a capacitor case and shielded by a potting resin, the capacitor terminal member projecting from a potting surface of the capacitor body. The capacitor is fixed to the capacitor case such that the potting surface faces the semiconductor module. The capacitor terminal member is supported by and fixed to a fixing/supporting member fixed to the apparatus case. | 05-22-2014 |
| 20140185266 | POWER CONVERTER - A positive-electrode connecting plate ( | 07-03-2014 |
| 20140233204 | Electric Circuit Device, Electric Circuit Module, and Power Converter - The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces. | 08-21-2014 |
| 20140240949 | SUBSTRATE STRIP - Disclosed herein is a substrate strip including: a substrate region having a plurality of substrate units formed therein; a dummy region enclosing the substrate region; a plurality of metal patterns formed at a predetermined size in the dummy region; and rib patterns formed between the metal patterns. | 08-28-2014 |
| 20150016083 | Thermocompression bonding apparatus and method - A multi-layer aluminum nitride ceramic, multi-heating element substrate is provided for forming electrical bonds between integrated circuits and an interposer structure using a thermocompression bonding process. The individually energizable heater element traces can be run through common regions of the heater surface platform. A network of cooling vias can be run through other parts of the substrate. The traces are then separately controlled and energized during a predetermined routine resulting in a temperature profile that maintains a substantially constant temperature plateau phase near a reflow temperature, and a more uniform temperature across the spaced apart surface regions of the heater substrate, thus imparting a more precisely uniform heating to the parts being bonded. | 01-15-2015 |
| 20150043190 | EMBEDDED PACKAGING WITH PREFORMED VIAS - Microelectronic assemblies and methods of making the same are disclosed. In some embodiments, a microelectronic assembly includes a microelectronic element having edge surfaces bounding a front surface and contacts at the front surface; rigid metal posts disposed between at least one edge surface and a corresponding edge of the assembly, each metal post having a sidewall separating first and second end surfaces, the sidewalls have a root mean square (rms) surface roughness of less than about 1 micron; a encapsulation contacting at least the edge surfaces and the sidewalls; an insulation layer overlying the encapsulation; connection elements extending through the insulation layer, wherein at least some connection elements have cross sections smaller than those of the metal posts; a redistribution structure deposited on the insulation layer and electrically connecting first terminals with corresponding metal posts through the first connection elements, some metal posts electrically coupled with contacts of microelectronic element. | 02-12-2015 |
| 20150109753 | Omedia Panel - An Omedia panel may be provided that includes an at least one network interface device, a housing, and a front panel. The at least one network interface device might be in communication with a service provider network. The housing may be integrated into a wall of a customer premises and positioned within a wall cavity of the wall. The housing might be configured to support the at least one network interface device. The front panel may be communicatively interfaced with the at least one network interface device such that a user can access one or more ports of the at least one network interface device via the front panel. | 04-23-2015 |
| 20160007492 | Power Semiconductor Device and Power Conversion Device - A power semiconductor device includes a plurality of power semiconductor elements constituting upper and lower arms of an inverter circuit, a first sealing member sealing the plurality of power semiconductor elements, a positive electrode-side terminal and a negative electrode-side terminal each connected with any of the plurality of power semiconductor elements and protruding from the first sealing member, a second sealing member sealing at least a part of the positive electrode-side terminal and at least a part of the negative electrode-side terminal, and a case in which the power semiconductor elements sealed with the first sealing member are housed. | 01-07-2016 |
| 20160049898 | MOUNTING SYSTEM FOR PHOTOVOLTAIC ARRAYS - Photovoltaic (PV) systems are disclosed, to include mounting brackets and mounting systems. In one embodiment, a PV array mounting system with brackets comprising pairs of panel connectors and panel connector receivers is disclosed. | 02-18-2016 |
| 20160066426 | Packaged Semiconductor Devices And Methods of Packaging Thereof - Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device. | 03-03-2016 |
| 20160150594 | Thermocompression bonding apparatus and method - A multi-layer aluminum nitride ceramic, multi-heating element substrate ( | 05-26-2016 |
| 20160157366 | ELECTRONIC COMPONENT HOUSING PACKAGE AND ELECTRONIC APPARATUS | 06-02-2016 |
| 20160172134 | Power Semiconductor Module | 06-16-2016 |
| 20190143638 | WINDOW MEMBER AND DISPLAY DEVICE INCLUDING THE SAME | 05-16-2019 |
