| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 348536000 | Automatic phase or frequency control | 44 |
| 20090167944 | Video-signal receiving apparatus and method - A video-signal receiving method is provided. First, receive an analog video signal, wherein the analog video signal comprises a specific video signal and a synchronization signal. Next, at least perform an analog-to-digital conversion on the synchronization signal of the analog video signal according to a sampling signal to generate a digital signal. Then, receive the digital signal and decoding the digital signal to obtain a digital synchronization signal corresponding to the synchronization signal. Afterward, adjust a phase of the sampling signal according to the digital synchronization signal. | 07-02-2009 |
| 20090284654 | SYNCHRONIZING SIGNAL CONTROL CIRCUIT AND SYNCHRONIZING SIGNAL CONTROL METHOD - A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization compensation period and the detected phase difference; a synchronization phase correcting section configured to correct the phase of the input synchronizing signal on the basis of the output signal of the adding section; a gate signal generating section configured to generate a gate signal representing the synchronization compensation period based on the display synchronizing signal; a synchronization determining section configured to determine whether the synchronization can be effected, by detecting whether the input synchronizing signal exists within the synchronization compensation period; and a selecting section configured to perform switching to the corrected input synchronizing signal on the basis of the determination result of the synchronization determining section. | 11-19-2009 |
| 20100053431 | METHOD AND DEVICE FOR PROCESSING A SEQUENCE OF SOURCE PICTURES - The invention relates to a method for combating the copying of source pictures by means of a camera while they are being displayed, for example using a camcorder in a movie theatre. To this end, it is known, in classical projection systems, to modulate by a carrier wave the brightness of some pixels of the pictures. The frequency of the carrier wave is usually constant and generally half the refresh frequency. The main problem with such systems is that once a pirate has figured out what the modulation frequency is, he can configure his camcorder shutter to filter out this frequency and bypass the anti-camcorder method. According to the invention, the frequency of the carrier is changed at least once throughout the displaying of the sequence pictures or the movie, to defeat all camcorders standards (PAL/NTSC) and shutter configurations. | 03-04-2010 |
| 20100214477 | PLL LOOP ABLE TO RECOVER A SYNCHRONISATION CLOCK RHYTHM COMPRISING A TEMPORAL DISCONTINUITY - The present invention relates to the domain of video equipment. It relates to a phase-locked loop able to recover the timing of a synchronization signal comprising a temporal discontinuity of a maximum amplitude equal to PCR_Modulus, the loop comprising: | 08-26-2010 |
| 20110050998 | Digital Phase Lock Loop Configurable As A Frequency Estimator - In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost. | 03-03-2011 |
| 20110285907 | TELEVISION BROADCAST RECEIVING APPARATUS - A television broadcast receiving apparatus has a demodulating unit including a PLL part synchronizing a phase of an IF signal with a phase of an internally generated carrier signal and outputting an out-of-synchronization flag signal when the IF signal and the carrier signal are in an unsynchronized state, and a muting part muting a sound intermediate frequency signal and outputting a noise signal of a predetermined level when the out-of-synchronization flag signal is outputted from the PLL part. Therefore, even when an IF amplifier of a tuning unit amplifies a noise at the maximum gain when there is no signal, an abnormal sound can be prevented from being outputted from a speaker of a decode and output unit. | 11-24-2011 |
| 20120081606 | VIDEO SYNCHRONIZATION - A method of synchronizing the phase of a local image synchronization signal generator of a local video data processor in communication with an asynchronous switched packet network to the phase of a reference image synchronization signal generator of a reference video data processor also coupled to the network, the local and reference processors having respective clocks, the reference and local image synchronization signal generators generating periodic image synchronization signals in synchronism with the reference and local clocks respectively including: frequency synchronizing the local and reference clocks; sending an image timing packet providing reference image synchronization data indicating the difference in timing, measured with respect to the reference processor's clock, between the time at which the image timing packet is launched onto the network and the time of production of a reference image synchronization signal; and controlling the timing of the production of the local image synchronization signal. | 04-05-2012 |
| 20130063661 | PHASE SYNCHRONICATION CIRCUIT AND TELEVISION SIGNAL RECEPTION CIRCUIT - A phase synchronization circuit includes a low-pass filter configured to integrate the pulse signal output from a charge pump, and a line filter configured to be provided on a control voltage supply line for supplying the control voltage from the low-pass filter to a voltage controlled oscillation circuit. Here, one end of a capacitor of the line filter is connected, through resistance of a CP current switching circuit, from an output terminal of the charge pump to the ground in terms of high frequencies. | 03-14-2013 |
| 20130169870 | FRONT-END INTEGRATED CIRCUIT, BROADCAST RECEIVING SYSTEM AND OPERATING METHOD - The front-end integrated circuit includes a first clock unit receiving a reference clock signal from an oscillator and generating a first clock signal, a first analog front end module receiving and processing a first broadcast signal using the first clock signal, a second clock unit receiving the reference clock signal and generating a second clock signal, and a second analog front end module receiving and processing a second broadcast signal using the second clock signal. | 07-04-2013 |
| 20140002739 | METHOD AND APPARATUS FOR REDUCING POWER USAGE DURING VIDEO PRESENTATION ON A DISPLAY | 01-02-2014 |
| 20140022457 | SYSTEMS AND METHODS FOR LATENCY STABILIZATION OVER AN IP NETWORK - An exemplary embodiment of the present invention provides a latency stabilization system for stabilizing the display latency between a source and a renderer over an IP network. The latency stabilization system comprises a frequency syntonization module, a frequency lock detection module, and a phase correction module. The frequency syntonization module can be configured to syntonize a frequency of a source signal from the source and a frequency of a display signal to be displayed on the renderer. The frequency lock detection module can be configured to detect whether the frequency of the source signal and the frequency of the display signal are locked. The phase correction module can be configured to, synchronize a phase of the source signal and a phase of the display signal, and generate correction data based in part on synchronization of the phase of the source signal and the phase of the display signal. | 01-23-2014 |
| 20150109530 | LOW LATENCY AND LOW COMPLEXITY PHASE SHIFT NETWORK - A high performance, low complexity phase shift network may be created with one or more non-first-order all-pass recursive filters that are built on top of a plurality of first-order and/or second-order all-pass recursive filters and/or delay lines. A target time delay, whether large or small, may be specified as a constraint for a non-first-order all-pass recursive filter. A target phase response may be determined for the non-first-order all-pass recursive filter. Phase errors between the target phase response and a calculated phase response with filter coefficients of the non-first-order all-pass recursive filter may be minimized to yield a set of optimized values for the filter coefficients of the non-first-order all-pass recursive filter. | 04-23-2015 |
| 348537000 | Of sampling or clock | 20 |
| 20080231749 | Image data processing apparatus - An image data processing apparatus of the present invention includes: a base clock output circuit for outputting a base clock; a plurality of image processors; and a plurality of external PLL circuits provided for each one of the plurality of image processors. The plurality of external PLL circuits each synchronize an output clock given from a corresponding one of the plurality of image processors with the base clock. | 09-25-2008 |
| 20080278626 | PHASE ADJUSTMENT METHOD AND DIGITAL CAMERA - A signal change differential value detector detects a signal change differential value between two digital signals obtained when the analog imaging signal is converted into the digital value for each pixel using two phase adjustment sampling pulses. An analog imaging signal waveform estimator estimates a waveform of the analog imaging signal based on the signal change differential value. A timing adjuster calculates an optimal phase of the imaging pulse based on the waveform of the analog imaging signal estimated by the analog imaging signal waveform estimator. | 11-13-2008 |
| 20080309818 | IMAGE-CLOCK ADJUSTING CIRCUIT AND METHOD - An image-clock adjusting circuit is provided and includes a phase comparator, a clock controller, and a timing generator. The phase comparator receives a power source signal and a vertical synchronous signal and compares a phase of the power source signal with that of the first vertical synchronous signal for producing at least a phase comparison signal. The clock controller receives the phase comparison signal and the vertical synchronous signal, produces a pixel clock signal and intermittently adjusts a clock width of the pixel clock signal. The timing generator receives the pixel clock signal and adjusts the vertical synchronous signal into an adjusted vertical synchronous signal being nearly in phase with the power source signal. Therefore, The effect suppressing the phenomenon of the color rolling with the simpler circuit is accomplished. | 12-18-2008 |
| 20090009662 | Method and Apparatus for Wireless Clock Regeneration - Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock difference are transmitted to a wireless clock receiver which also receives the same reference clock frames. Source clock frames are re-constructed using the reference clock frames, clock difference information and the receiver's local clock system. | 01-08-2009 |
| 20090096924 | Method and Apparatus for Providing a Stable Clock Signal - The disclosed embodiments relate to a low cost signal adjustment or calibration method and apparatus for generating a stable clock signal that is used to drive a communications interface (e.g., a UART port). More specifically, a processor within a microcontroller uses a low frequency crystal oscillator and a scaling module to remove a frequency offset error contained in an unstable clock signal generated by a high frequency RC oscillator. The processor detects and removes the frequency offset error when specific triggering events occur such as when the microcontroller is powered up, awaken from a sleep or stand by mode, or experiences a communications error. | 04-16-2009 |
| 20090190032 | Noise elimination device for the detection of the vertical sync pulse in video signals - In order to create a noise elimination device for the detection of the vertical sync pulse in video signals, which has a very fast locking behavior and in which additional components can be integrated easily, which components can measure fundamental parameters of the underlying composite video signal, it is proposed that the device comprises a vertical pulse detector ( | 07-30-2009 |
| 20100201874 | Image display apparatus and method of adjusting clock phase - An image display apparatus includes a controller for dividing at least a portion of an image displayed based on a digital video signal, into a plurality of image areas defined by display lines, and establishing different delays for the divided image areas, a clock adjuster generating a clock in synchronism with the dot clock, delaying a phase of the clock according to the delays established by the controller, for the respective divided image areas, and outputting the delayed clock as the reproduced dot clock, and a delay evaluating unit converting differential data between adjacent signal levels into absolute values and accumulatively adding the absolute values based on the reproduced dot clock output from the clock adjuster, with respect to the display lines which define the divided image areas, thereby producing accumulated sums. The controller judges the delay established for the divided area with the maximum accumulated sum, as optimum. | 08-12-2010 |
| 20100231789 | ANALOG-DIGITAL CONVERTING APPARATUS AND CLOCK SIGNAL OUTPUT APPARATUS - An apparatus includes a voltage controlled oscillator for outputting a clock signal having an oscillation frequency in accordance with an input voltage; a convertor for converting the analog video signal inputted from the exterior into the digital video signal synchronizing with the clock signal outputted from the voltage controlled oscillator; a phase difference detector for detecting a phase difference between the composite synchronizing signal in the analog video signal and a feedback signal which corresponds to the clock signal from the voltage-controlled oscillator; and a voltage control unit for controlling the input voltage of the voltage controlled oscillator to change in response to the phase difference detected by the phase difference detector when the phase difference is within the certain range, and to maintain the input voltage intact when the phase difference is in exceed of the certain range. | 09-16-2010 |
| 20100289955 | DATA LINK CONFIGURATION BY A RECEIVER IN THE ABSENCE OF LINK TRAINING DATA - A receiver is enabled to perform self-configuration of the main data link to receive and display video data. A video data signal is received through a data link having multiple channels or lanes at a specific bit rate. No link configuration data normally associated with the video signal is received. It is then determined which one or more of the channels of the data link are active in transmitting the data signal. A symbol pattern in the data signal is then identified. The symbol rate of the data signal is then synchronized with the local clock frequency. The local clock frequency is set to correspond to the actual bit rate of the data signal, thereby creating a signal-based clock frequency. This local clock frequency is set using only the data signal since no link configuration data associated with the signal is received. In this manner, the receiver configures or trains the link itself using only the video data signal and therefore, the receiver may be described as self-sufficient. | 11-18-2010 |
| 20110019091 | Method and System of Automatically Correcting a Sampling Clock in a Digital Video System - A method and system of automatically correcting a sampling clock in a digital video system are disclosed. Sampling clocks with different phases are generated and subjected in turn to analog-to-digital conversion (ADC). A difference of at least a pair of neighboring data out of the ADC with respect to each phase is determined. A maximum difference is determined, and the sampling clock with the phase corresponding to the maximum difference is thus generated. | 01-27-2011 |
| 20110063505 | APPARATUS AND METHOD FOR DRIVING LIGHT SCANNER - An apparatus for driving a light scanner and method thereof are disclosed. The present invention includes an apparatus for driving a light scanner, which scans an image on a screen, the apparatus comprising the light scanner driven by a drive signal, a sensing unit sensing a driving of the light scanner, a pixel clock signal generating unit generating a pixel clock signal by detecting a 90-degree phase difference between the drive signal and a sensing signal sensed by the sensing unit, a sync signal adjusting unit adjusting vertical and horizontal sync signals of an input video according to the pixel clock signal and a driving unit driving the light scanner according to the adjusted horizontal and vertical sync signals. | 03-17-2011 |
| 20110181777 | AUTOMATIC QUANTIZATION CLOCK PHASE ADJUSTABLE DISPLAY APPARATUS - The method adjusts the phase of a quantization clock signal for a video signal automatically based on a received analogue video signal. The method includes a step of determining a horizontal start position and a horizontal end position of a pixel-level transition within the analogue video signal, a step of determining a stable-period start position and a stable-period end position at each transition by sequentially changing an adjustable phase of the quantization clock signal, a step of calculating an appropriate phase of the quantization clock signal based on the determined timings of the beginning and end of the stable periods within the analogue signal, and a step of setting the phase of the quantization clock signal to the calculated appropriate phase. | 07-28-2011 |
| 20110304768 | METHOD OF SAMPLING PHASE CALIBRATION AND DEVICE THEREOF - A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum. | 12-15-2011 |
| 20120069245 | Video System Sampling Phase Determination - A phase for an analog-to-digital converter sampling clock is determined. The analog-to-digital converter samples a video signal to generate pixel values. Differences of successive pixel values are compared to a threshold. The number of times the threshold is exceeded is counted for multiple phase values to create a phase profile. The threshold may be dynamic. | 03-22-2012 |
| 20130027611 | METHOD AND APPARATUS FOR REGENERATING A PIXEL CLOCK SIGNAL - A method and device regenerating a pixel clock signal, the method comprising, and the device being configured for: determining a first drift value D | 01-31-2013 |
| 20130113992 | METHODS OF GENERATING A PIXEL CLOCK SIGNAL FROM A TRANSMISSION CLOCK SIGNAL AND RELATED DATA TRANSMISSION METHODS FOR MULTIMEDIA SOURCES - Methods of generating a pixel clock signal for a multimedia source are provided in which a transmission clock signal having a first frequency is generated from a reference clock signal that has a second frequency. The generated transmission clock signal is multiplied by a multiple to generate the pixel clock signal. The pixel clock signal has a third frequency that is the product of the second frequency and the multiple, | 05-09-2013 |
| 20140085539 | VIDEO SIGNAL PROCESSING APPARATUSES - A video signal processing apparatus may include a first analog-to-digital converter (ADC) configured to convert an analog video signal into a first digital video signal according to a first clock; and/or a second ADC configured to convert the analog video signal into a second digital video signal according to a second clock that is different from the first clock. The first and second clocks may have a first phase difference in a first section of the analog video signal, such that the first and second ADCs operate alternately, first ADC then second ADC, and the first and second clocks may be generated to have a second phase difference, that is different from the first phase difference, in a second section of the analog video signal that is different from the first section, such that the first and second ADCs operate alternately, second ADC then first ADC. | 03-27-2014 |
| 20150109531 | CLOCK TRANSFER CIRCUIT, VIDEO PROCESSING SYSTEM, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A clock transfer circuit receives input data synchronized with a first clock, and outputs, as output data, data synchronized with a second clock having a frequency different from that of the first clock. A write address controller is operating according to the first clock, and provides a write address to a memory. A read address controller is operating according to the second clock, and provides a read address to the memory. A cycle comparator compares the cycle of a predetermined event between the input data and the output data. Based on such a comparison result, the clock adjuster adjusts the frequency of the second clock. | 04-23-2015 |
| 348538000 | With data interpolation | 1 |
| 20100321571 | Scaling Process System, Video Output Apparatus and Replay Apparatus - Disclosed is a scaling process system including a replay apparatus and a video output apparatus which are connected via a HDMI, wherein each of the video output apparatus and the replay apparatus respectively comprises a between-pixel interpolation method table for deciding a superiority/inferiority of a between-pixel interpolation method which is used when carrying out a scaling process in the scaling process system, wherein the video output apparatus including a version request signal transmission device, a version information receiving device, a determining device, a control device, a between-pixel interpolation method table receiving device and a first update execution device, wherein the replay apparatus including a version request signal receiving device, a version information return device, a receiving device, a between-pixel interpolation method table transmission device and a second update executing device. | 12-23-2010 |
| 348539000 | Color | 1 |
| 20110310296 | METHOD FOR RECOVERING PIXEL CLOCKS BASED ON INTERNAL DISPLAY PORT INTERFACE AND DISPLAY DEVICE USING THE SAME - A method for recovering pixel clocks based on an iDP interface includes selecting a prime factor closest to VA or HA from prime factors of X, and selecting a value obtained by subtracting VA from the selected prime factor, as VB, in | 12-22-2011 |
| 348540000 | Horizontal sync component | 7 |
| 20100238349 | Image display apparatus and frequency adjustment method thereof - A format of an inputted video signal is estimated to be based on the total number of vertical lines, and a frequency dividing ratio of a PLL unit is provisionally set at a predetermined value corresponding to the estimated format. Next, the frequency dividing ratio is calculated so that a measured value of a horizontal display width that is measured by a video detecting unit matches a capture width which is the horizontal display width capturable by a frame memory, and the calculated frequency dividing ratio is converted to a multiple of 4. A phase adjustment of the regenerative dot clock is performed against the video signal based on the converted frequency dividing ratio by using the regenerative dot clock generated by the PLL unit. Furthermore, the frequency dividing ratio is recalculated so that the measured value of the horizontal display width that is measured by the video detecting unit matches the capture width by using the regenerative dot clock after finishing the phase adjustment, and the calculated frequency dividing ratio is reset to the PLL unit. | 09-23-2010 |
| 20110085081 | VIDEO HORIZONTAL SYNCHRONIZER - A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed. | 04-14-2011 |
| 20120236203 | HORIZONTAL SYNCHRONIZATION SIGNAL DETECTION SYSTEM AND METHOD - A horizontal synchronization signal detection system includes a coarse period estimator and a fine period time estimator. The coarse period estimator estimates a minimum value and corresponding position of each period of a CVBS signal to calculate a coarse period of a horizontal synchronization signal. The fine period time estimator divides the horizontal synchronization signal into a first part and a second part so as to generate a first sum and a second sum by adding signals of the first part and the second part, and detects a middle point of the horizontal synchronization signal when the first sum equals the second sum. The steps of fine-tuning the coarse period to generate a fine-tuned coarse period, extracting the horizontal synchronization signal according to the fine-tuned coarse period, and determining whether the first sum is equal to the second sum are repeatedly executed until the first sum equals the second sum. | 09-20-2012 |
| 20120262627 | METHOD FOR SYNCHRONIZING A DISPLAY HORIZONTAL SYNCHRONIZATION SIGNAL WITH AN EXTERNAL HORIZONTAL SYNCHRONIZATION SIGNAL - Adjust a vertical blanking interval of a display horizontal synchronization signal, according to a difference between an external horizontal synchronization signal and the display horizontal synchronization signal, for synchronizing the display horizontal synchronization signal to the external horizontal synchronization signal. This only requires one or two frames to synchronize the display horizontal synchronization signal to the external horizontal synchronization signal, and will not cause the user to perceive display pauses or flickers. | 10-18-2012 |
| 20120287342 | HORIZONTAL SYNCHRONIZATION DETECTION DEVICE - A horizontal synchronization detection device includes a pulse detection portion that detects a pulse in a horizontal synchronization signal contained in a video signal and acquires a pulse width of the detected pulse, a synchronization pulse decision portion that determines the pulse satisfying a condition that a difference between its pulse width and a reference pulse width is within a first predetermined range as a synchronization pulse, a mean pulse width acquisition portion that averages out a pulse width of the synchronization pulse for each field and obtains a mean pulse width thereof, and a reference pulse width correction portion that determines, for each synchronization pulse in a current field, whether a difference between its pulse width and the mean pulse width in a previous field is within a second predetermined range, and corrects the reference pulse width and/or the first predetermined range based on the determination result. | 11-15-2012 |
| 20140036150 | PIXEL CLOCK GENERATOR, METHOD OF OPERATING THE SAME, AND APPARATUSES INCLUDING THE PIXEL CLOCK GENERATOR - A method of operating a pixel clock generator (PCG), the method including generating N clock signals according to a control voltage signal, the N clock signals having different phases and N being a natural number; generating M frequency-divided clock signals based on the N clock signals, the M frequency-divided clock signals having different phases and M being a natural number greater than N; and generating a pixel clock signal based on at least two selected ones of the M frequency-divided clock signals. | 02-06-2014 |
| 20150062432 | PIXEL CLOCK GENERATOR, DIGITAL TV INCLUDING THE SAME, AND METHOD OF GENERATING PIXEL CLOCK - A pixel clock generator is provided. The pixel clock generator includes a phase-locked-loop (PLL) circuit that generates, from an oscillation signal having a first frequency of tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz; and a frequency/phase adjusting circuit that synchronizes the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal, frequency-divides the first oscillation signal to generate a second oscillation signal, and adjusts a phase of the second oscillation signal to generate the pixel clock. | 03-05-2015 |
| 348547000 | Vertical sync component | 5 |
| 20080266454 | VIDEO SINK DEVICE - The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal. | 10-30-2008 |
| 20130194498 | DISPLAY APPARATUS - A display apparatus includes a first determiner configured to determine a terminal into which a video signal inputs and to determine a terminal into which a synchronizing signal type inputs, a frequency measuring unit, a switch configured to connect one of first and second input terminals to the frequency measuring unit, and a second determiner configured to determine a video signal type input into the input terminal which is connected by the switch to the frequency measuring unit on the basis of a determination result of the synchronizing signal type in the first determiner and a measurement result of the frequency in the frequency measuring unit and to determine a video signal type input into the input terminal which is not connected by the switch to the frequency measuring unit on the basis of the determination result of the synchronizing signal type in the first determiner. | 08-01-2013 |
| 20140028916 | IMAGE TRANSMITTING/RECEIVING SYSTEM, IMAGE TRANSMITTING APPARATUS, RECEIVED IMAGE DISPLAYING APPARATUS, WIRELESS CONTROL APPARATUS, AND IMAGE TRANSMITTING/RECEIVING METHOD - A received image displaying apparatus comprises: a wireless communication unit that wirelessly receives the frame images transmitted by the image transmitting apparatus with which the received image displaying apparatus has established a connection of wireless communication; and a displaying unit that displays the frame images, which were wirelessly received by the wireless communication unit, in an order in which the frame images were captured. At least one of the image transmitting apparatus and the received image displaying apparatus comprises: a reference sync signal generating unit that generates the reference sync signals; and a control unit that, if the wireless communication unit has received no reference sync signals for a certain time interval, controls the reference sync signal generating unit to generate reference sync signals and that further controls the wireless communication unit to wirelessly transmit the reference sync signals to the other apparatus included in the image transmitting/receiving system. | 01-30-2014 |
| 20140362292 | DISPLAY DEVICE AND DRIVING METHOD THEREOF - A display device including a display panel which displays a video signal is disclosed. The display device includes a panel driver configured to drives the display panel; a light source configured to provide light to the display panel; a light source driver configured to control the brightness of the light source in accordance with a pulse width modulation dimming signal in synchronization with a vertical sync signal; and a controller configured to receive the vertical sync signal, determine whether the frequency of the vertical sync signal is normal or abnormal, and provide the dimming signal (PWM pulses) to the light source driver in non-synchronization with the vertical sync signal during at least one frame, in response to the frequency of the vertical sync signal being abnormal. | 12-11-2014 |
| 348548000 | Countdown | 1 |
| 20110019092 | SYSTEM OF PROGRAMMABLE TIME INTERVALS USED FOR VIDEO SIGNAL SYNCHRONIZATION - A circuit and a method for using the circuit to provide synchronization between a first video signal and a second video signal are provided, comprising a circuit to capture a first video signal, a circuit to measure the timing format of the first video signal including an input clock and count input Vsync pulses, a circuit to measure a phase difference between the first video signal and the second video signal, a circuit to generate an output video signal comprising a number of output Vsync pulses and an output clock, and a PLL circuit to control the output clock period as a constant ratio of the input Vsync period, and maintain a constant number of output clock periods per a number of input clock periods. Also provided is a system to perform the method as above using the circuit as above, maintaining a constant ratio between the output clock period and a number of input clock periods. | 01-27-2011 |
