| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 345564000 | Addressing | 40 |
| 20090073179 | ADDRESSING ON CHIP MEMORY FOR BLOCK OPERATIONS - A method for circularly accessing a plurality of memory addresses, using a sequence of values comprises determining a plurality of values, the number of values in the plurality of values being m, each value being represented by a predefined number of bits n. The method further comprises identifying in a register ( | 03-19-2009 |
| 20090284539 | SYSTEM AND METHOD FOR DISPLAYING DIGITAL IMAGE FILES - A digital image displaying system includes a DPF and an electronic device communicating with the DPF. The DPF has identification information. The electronic device includes a DPF detecting submodule, a image storing submodule for storing digital image files, a DPF managing submodule, and an information transmitting submodule. The DPF detecting submodule detects identification information of the at least one DPF, the DPF managing submodule stores the identification information therein, the information transmitting submodule transmits network location paths of the digital image files of the image storing submodule to the at least one DPF, the at least one DPF receives the network location paths and displays the digital image files stored in the image storing submodule according to the network location paths. A method for displaying digital image files is also provided. | 11-19-2009 |
| 20100026697 | PROCESSING RASTERIZED DATA - Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks. | 02-04-2010 |
| 20100085370 | DISPLAY CONTROL DEVICE TO DISPLAY IMAGE DATA - In the display of an image including a fixed background image and a variation image of the background image, at least one of the amount of data to be held and the amount of work to be processed is reduced. A display control device acquires pixel description data including a combination of position information for specifying a position on a pixel array and address information for specifying an address in an image storage unit of image data which is displayed at the position specified by the position information. Furthermore, the display control device reads out the image data from the address of the image storage unit specified by the address information and specifies the position on the pixel array specified by the image description data to the display to input the read out image data. | 04-08-2010 |
| 20100141668 | ADDRESS CALCULATION UNIT - The invention relates to a address calculation unit ( | 06-10-2010 |
| 20100225659 | DISPLAY CONTROL DEVICE, DISPLAY CONTROL PROGRAM AND METHOD - A display control device includes a memory that stores display data to be displayed on a display section, an operation section that specifies a display area of the display section where the display data is displayed, an address setting section that sets a setting address value with respect to a memory address of the display data stored in the memory, an address specifying section that specifies a read start address value of the display area with respect to the memory address based on a first operation amount of the operation section, and a specified address changing section that changes, when the read start address value is equal to the setting address value, the read start address value to a different address value. | 09-09-2010 |
| 20110018888 | ADDRESSING METHOD AND STRUCTURE FOR MULTIPLE CHIPS AND DISPLAY SYSTEM THEREOF - Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of a previous stage is connected to the input enable terminal of a next stage. The method includes setting an initial address to an address of each chip via a system; setting a state of each chip to a disable state; enabling the state of a first-one chip among the chips to an enable state, and setting the first chip as a previous-stage chip; updating the address of the previous-stage chip; enabling a next-stage chip connected after the previous-stage chip, in which the system controls the output enable terminal of the previous-stage chip to output an enable signal to enable the next-stage chip, according to the address of the previous-stage chip; and the updating the address of the next-stage chip. | 01-27-2011 |
| 20110074802 | Architecture and Instructions for Accessing Multi-Dimensional Formatted Surface Memory - One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions. | 03-31-2011 |
| 20110279465 | MEMORY SYSTEM HAVING MULTIPLE ADDRESS ALLOCATION FORMATS AND METHOD FOR USE THEREOF - A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array. | 11-17-2011 |
| 20120086717 | INSTANT REMOTE RENDERING - Cross-environment rendering and user interaction support provide a seamless computing experience in a multi-operating system computing environment. The multi-operating system computing environment may include a mobile operating system and a desktop operating system running concurrently and independently on a mobile computing device. Real-time or instant display of an application running in the mobile operating system within an environment of the desktop operating system is provided by rendering application graphics for the application within the desktop operating system. A console application of the desktop operating system may access surface information for the application from shared memory and render the application within a console window of the computing environment associated with the desktop operating system. The mobile computing device may be a smartphone running the Android mobile operating system and a full desktop Linux distribution on a modified Android kernel. | 04-12-2012 |
| 20120256937 | DATA MANAGEMENT FOR IMAGE PROCESSING - A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed. | 10-11-2012 |
| 20130249925 | Shared Virtual Memory Between A Host And Discrete Graphics Device In A Computing System - In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed. | 09-26-2013 |
| 20130300757 | Volumetric Display - A method including storing a data structure that defines at least part of a surface within a volume, including a non-overlapping set of sub-volumes, by specifying, for different first positions of a first straight line, a distance along the first straight line of a sub-volume of a sub-set of sub-volumes that defines the at least part of the surface; and using the data structure to control a first scanner, configured to address sub-volumes that lie along a first straight line at different positions of the first straight line, and to control a second scanner, configured to address sub-volumes that lie along a second straight line for different positions of the second straight line, to address co-operatively the sub-set of sub-volumes that defines the at least part of the surface. | 11-14-2013 |
| 20130328899 | RENDERING DEVICE, RENDERING METHOD AND RECORDING MEDIUM - A DMA controller reads image information recorded on a ROM by address unit from a front reading start position. A shift operator shifts a first data sequence of one row of the reading by only a designated number of bits, and generates a second data sequence. A DMA controller reads a third data sequence already stored in a VRAM writing start position. A controller performs a prescribed operation on the second data sequence and the third data sequence, and generates a fourth data sequence. The controller writes the generated fourth data sequence successively in a horizontal direction by address unit from the VRAM writing start position. | 12-12-2013 |
| 20130342554 | METHOD, SYSTEM AND ELECTRONIC DEVICE FOR ASSOCIATION BASED IDENTIFICATION - A method for association based identification. The method includes providing at least one identifier and communicating identification information based on the at least one identifier. The method further includes receiving and processing identification information. Each of the at least one identifier can be associated with a color code. Identification information can be processed in a manner so as to produce association data. The association data can be associated with at least a characteristic data from a set of library data. The set of library data can correspond to a library of color codes and a characteristic data from the set of library data can correspond to a color code from the library of color codes. The association data is based upon to produce output signals. The output signals can be based on characteristic data associable with the association data. | 12-26-2013 |
| 20140320512 | QUERY PROCESSING FOR TILE-BASED RENDERERS - Systems, methods, and apparatus for performing queries in a graphics processing system are disclosed. These systems, methods, and apparatus may be configured to read a running counter at the start of the query to determine a start value, wherein the running counter counts discrete graphical entities, read the running counter at the end of the query to determine an end value, and subtract the start value from the end value to determine a result. | 10-30-2014 |
| 20150302834 | ADDRESS CONFIGURING METHOD AND DEVICE FOR A PARALLEL DISPLAY CONTROL SYSTEM - The present invention relates to a lamp controlling field and provides an address configuring method and device for a parallel display control system. The method includes: receiving address data sent from a controller of the parallel display control system by each address data port, each address data port respectively locates on each parallel display unit, each address data port is connected to each other in a step serial connection manner, the address data comprises at least one address data package; intercepting the address data package of the address data that arrives first to the address data port thereof in turn to configure address and generating address data of the intercepted address data package successively according to the sequence of the step serial connection by each address data port; sending the remaining address data of the whole address data package to a next address data port connected serially to the address data port to enable the next address data port to configure address. In the present invention, a plurality of parallel display control unit can be configured in one address configuring operation, thereby improving address configuring efficiency. | 10-22-2015 |
| 345565000 | Using memory for storing address information | 7 |
| 20090237414 | Storage method for gamma value look-up table - A storage method for a gamma value look-up table comprises storing gamma values corresponding to grays exceeding or equaling a 33rd gray in the gamma value look-up table, and calculating gamma values corresponding to a 1st gray to a 32nd gray by a formula. | 09-24-2009 |
| 20090262124 | DRIVE CIRCUIT AND DISPLAY DEVICE - In one embodiment of the present invention, LUTs (T | 10-22-2009 |
| 20100073389 | Display device - In a display device which arranges a memory part for every display pixel, an erroneous operation of the memory part and the power consumption can be reduced. In a display device provided with a display panel which includes a plurality of display pixels, video lines which apply video data to the display pixels, and scanning lines which apply a scanning voltage to the display pixels, the display pixel includes a memory part which stores the video data, a pixel electrode, and a switching part which selectively applies a first video voltage or a second video voltage which differs from the first video voltage to the pixel electrode in response to the video data stored in the memory part. | 03-25-2010 |
| 20130314430 | DRAWING PROCESSING APPARATUS AND METHOD - A drawing processing apparatus is disclosed. A graphic index of a graphic included in a display screen or graphic description information which includes a setting parameter to be applied to the graphic is determined for each of regions dividing the display screen. A data size of the graphic description information is aggregated for the regions. A start address in a memory is determined to store the graphic description information into a successive storage area in the memory, based on the aggregated data size. The data size of an area of an overflow occurrence target is stored when the overflow occurs. The graphic description information of the regions is successively written from the start address when the overflow does not occur. A write process is stopped, and resumed from the area of the overflow occurrence target by using the data size when the overflow occurs. | 11-28-2013 |
| 20140055478 | METHOD AND SYSTEM FOR STORING AND RETRIEVING WIDE-AREA MOTION IMAGERY FRAMES AS OBJECTS ON AN OBJECT STORAGE DEVICE - A method, implemented by a computer system, and a system of organizing data of a wide area motion imagery frame and a method and a system of retrieving objects that match a user defined AOI from an image in a WAMI frame in a WAMI collection are described. The method of organizing includes dividing, by the computer system, an image of a WAMI frame into a plurality of tiles, each tile in the plurality of tiles comprising a plurality of pixels and having a pixel width and a pixel height; storing, by the computer system, the plurality of tiles as objects in an OSD, each object having an object identifier (OID); collecting, by the computer system, object identifiers (OIDs) of the objects; and storing, by the computer system, the OIDs in the OSD. | 02-27-2014 |
| 20140118382 | METHOD FOR PROGRAMMING EXTENDED DISPLAY IDENTIFICATION DATA AND DISPLAY DEVICE - A method for programming extended display identification data (EDID) adapted to a display device is provided. The display device has at least one EDID chip, a microcontroller unit chip, and a flash memory chip. in the method, a first EDID corresponding to the EDID chip is written into a firmware stored in the flash memory chip. The display device is powered on. The first EDID in the firmware is automatically written into the corresponding EDID chip as a second EDID by the microcontroller unit chip. | 05-01-2014 |
| 20160189337 | DATA STORAGE DEVICE AND DATA STORAGE METHOD FOR DISPLAY DEVICE - A data storage device to be coupled to a display device including a display unit including a plurality of blocks, each including a plurality of pixels, the data storage device including: a memory device to store a first address value and a second address value including information on a position of one of the plurality of blocks, store a first indication value to be utilized to determine whether the first address value is effective and a second indication value to be utilized to determine whether the second address value is effective, and store compensation data including information on the blocks; an effective address determinator to determine whether the first address value and the second address value are effective corresponding to the first indication value and the second indication value; and an updater to update the first and second indication values, the first and second address values, and the compensation data. | 06-30-2016 |
| 345566000 | Address manipulation | 8 |
| 20090147015 | Aperture Compression for Multiple Data Streams - A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request. | 06-11-2009 |
| 20120327098 | METHOD AND DEVICE FOR PROCESSING INFORMATION DISPLAYED ON TOUCH SCREEN OF MOBILE TERMINAL AND MOBILE TERMINAL THEREOF - The present invention relates to a mobile terminal technology. The present invention discloses a method for processing information displayed on a touch screen of a mobile terminal, and said method comprises steps of: determining whether a touch gesture received by the touch screen is made by at least two contact points; determining whether sliding motions made by each contact point onto the touch screen satisfy criteria set in the mobile terminal; deleting the information displayed on current interface; wherein the criteria are that the at least two contact points on the touch screen are slid parallel to each other, associated sliding motions for each contact point are oriented in opposite directions, and an angle between the associated sliding motions is within an angle threshold. The present invention can delete the information displayed on the interface quickly and conveniently and improve the interactivity of the mobile terminal and the user. | 12-27-2012 |
| 345567000 | Using decoding | 3 |
| 20080266306 | MEMORY SYSTEM HAVING MULTIPLE ADDRESS ALLOCATION FORMATS AND METHOD FOR USE THEREOF - A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array. | 10-30-2008 |
| 20160125852 | Ternary Addressable Select Scanner - A method of writing image data to a pixel array includes decoding an address and activating, based on the decoded address, two or more row selection signals. The address may be a ternary address having at least one trit. The method further includes providing the two or more row selection signals to the pixel array to select two or more rows of the pixel array, the activation of which writes the image data to pixels in the two or more rows of the pixel array. | 05-05-2016 |
| 20160180823 | SCANLINE DRIVER CHIP AND DISPLAY DEVICE INCLUDING THE SAME | 06-23-2016 |
| 345568000 | Address translation (e.g., between virtual and physical addresses) | 3 |
| 20080204467 | GRAPHICS MEMORY SWITCH - A graphics device delivers a graphics address to a graphics memory switch that includes a graphics random access memory translator and a graphics memory page table. The graphics memory address is delivered to the graphics memory switch via a point-to-point, packet based interconnect. The graphics memory switch generates a physical system memory address and delivers the physical address to a root complex. The physical system memory address is delivered to the root complex via a point-to-point, packet based interconnect. | 08-28-2008 |
| 20140354667 | GPU ACCELERATED ADDRESS TRANSLATION FOR GRAPHICS VIRTUALIZATION - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing GPU (Graphics Processing Unit) accelerated address translation for graphics virtualization. In one embodiment, such a system includes a main memory having a plurality of machine physical addresses; a graphics processor unit having graphics memory therein; an address translation service integrated with the graphics processor unit; a hypervisor to manage one or more guest machines; wherein the hypervisor is to configure a lookup table within the graphics memory of the graphics processor unit; and further wherein the address translation service of the graphics processor unit is to translate a guest physical address for one of the one or more guest machines to a corresponding machine physical address within the main memory. Such a graphics processor unit may be implemented separate from a system, for example, embodied within a silicon integrated circuit. | 12-04-2014 |
| 20180025465 | GPU ACCELERATED ADDRESS TRANSLATION FOR GRAPHICS VIRTUALIZATION | 01-25-2018 |
| 345569000 | For 2D coordinate to linear address conversion | 2 |
| 20090073180 | GRAPHICS DRAWING APPARATUS, METHOD, AND PROGRAM AND RECORDING MEDIUM ON WHICH THE PROGRAM IS RECORDED - A graphics drawing apparatus drawing a graphic, including: a generation unit, where a sequence of two-dimensional coordinates of vertices is input, generating the coordinates of each of the vertices and virtual vertex coordinates for the coordinates of each of the vertices on a memory, the virtual vertex coordinates being generated by converting the X-coordinate value of the coordinates of each of the vertices to the X-coordinate value of the coordinates of the leading vertex of the sequence; and a setting unit that sets the coordinates of two vertices of a partial graphic that is to be created as the coordinates of two adjacent vertices, in sequence starting from the leading vertex, and, after setting the coordinates of the trailing vertex of the sequence, setting the coordinates of two vertices of the partial graphic that is to be created as the coordinates of the leading and trailing vertices. | 03-19-2009 |
| 20140253575 | TRANSPOSE OF IMAGE DATA BETWEEN A LINEAR AND A Y-TILED STORAGE FORMAT - Systems, apparatus, articles, and methods are described including operations to transpose image data between a linear-type storage format and a Y-tiled-type storage format. | 09-11-2014 |
| 345570000 | Page mode | 1 |
| 20110102447 | MEMORY ADDRESS MAPPING METHOD FOR CONTROLLING STORAGE OF IMAGES IN MEMORY DEVICE AND MEMORY ADDRESS MAPPING CIRCUIT THEREOF - A memory address mapping method of controlling storage of images in a memory device is provided. The memory device includes banks each having a plurality of pages. The memory address mapping method includes: receiving a first image; and referring to an image partition setting to generate a first memory address setting for each horizontal line partition in the first image, wherein the image partition setting defines that one image is divided into horizontal line groups each having at least one horizontal line, and each of the horizontal line groups is divided into horizontal line partitions in a horizontal line direction. First memory address settings of the horizontal line partitions in each horizontal line group of the first image control that a corresponding horizontal line group having the horizontal line partitions included therein is not stored into a same bank of the memory device. | 05-05-2011 |
| 345571000 | Memory addresses arranged in matrix row and column addresses) | 2 |
| 20090295817 | METHOD FOR READING AND WRITING IMAGE DATA IN MEMORY - A method for reading and writing a memory having n rows and A columns includes a first step of writing data in 0th to (n−2)th rows by a first technique; a second step of writing data in (n−1)th row per column and reading data in the 0th section by a second technique; a third step of writing data in 0th to (n−2)th sections by a third technique and reading data in 1st to (n−1)th sections by the second technique, a fourth step of writing data in the (n−1)th section by the third technique and reading data in 0th row by a fourth technique; a fifth step of writing data in 0th to (n−2)th rows by the first technique and reading data in 1st to (n−1)th rows by the fourth technique; and a sixth step of returning to the second step. | 12-03-2009 |
| 20120262469 | Methods and apparatus for driving matrix display panels - Systems and methods for realizing display drivers, especially OLED drivers having a high efficiency. With a single pass, using an algorithm based on simple equations based on gathered maximum display data, the driver can split an image to be displayed into multiple planes and tiles thus balancing peak current consumption. Furthermore the driver is able to optimize drive time periods in regard of many parameters. | 10-18-2012 |
| 345572000 | Address generator | 3 |
| 20090066709 | DISPLAY DRIVER - A display driver for sending display data to a display panel includes a sampling circuit and a selector. The sampling circuit receives moving image data and a sampling signal generated by a write signal and an address designated with an address decoder and captures the moving image data on the basis of the sampling signal. The selector receives still image data, a selecting signal and the moving image data captured by the sampling circuit and selects one of the still image data and the moving image data on the basis of the selecting signal. | 03-12-2009 |
| 20140347382 | METHOD AND APPARATUS FOR PERFORMING ADAPTIVE MEMORY BANK ADDRESSING - A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings. | 11-27-2014 |
| 345574000 | Read/Write address generator | 1 |
| 20160203801 | LOW CAPACITANCE DISPLAY ADDRESS SELECTOR ARCHITECTURE | 07-14-2016 |
