| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 345541000 | Shared memory | 27 |
| 20080218525 | MEMORY SYSTEM AND METHOD FOR IMPROVED UTILIZATION OF READ AND WRITE BANDWIDTH OF A GRAPHICS PROCESSING SYSTEM - A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored in memory page format. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory concurrently with reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to the bank of memory from which the pre-processed data was read. The processing pipeline is capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed. | 09-11-2008 |
| 20080303837 | Batching graphics operations with time stamp tracking - A method and an apparatus for updating graphics resource usage according to a stream of graphics commands atomically submitted to a graphics processing unit (GPU) are described. The stream of graphics commands may be received from a plurality of graphics APIs (application programming interfaces) by a graphics driver. Availability of graphics resources of the GPU may be monitored by the graphics driver for submitting the stream of graphics commands. A single notification from the GPU may indicate that all graphics commands submitted to the GPU have been executed for updating a usage of graphics resources associated with the executed graphics commands. | 12-11-2008 |
| 20090128574 | Multiprocessor System, Library Module And Rendering Processing Method - A multiprocessor system in which a CPU ( | 05-21-2009 |
| 20100149199 | SYSTEM AND METHOD FOR VIDEO MEMORY USAGE FOR GENERAL SYSTEM APPLICATION - A system and method for facilitating access to graphics memory wherein the graphics memory can be shared between a graphics processor and general system application. The method includes detecting an idle state of a graphics processing unit (GPU). The GPU uses graphics memory operable for storing graphics data. The method further includes determining an amount of available memory of the graphics memory of the GPU and signaling an operating system regarding the available memory. Memory data transfers are then received to store data into the available memory of the graphics memory wherein the data is related to general system application. Memory accesses to the available memory of the GPU are translated into a suitable format and executed so that the graphics memory is shared between the GPU and the operating system. | 06-17-2010 |
| 20100171748 | Motion Desktop - A motion desktop, including a moving image, may be presented on a display screen of a processing device. Foreground items such as, for example, icons and associated text, or other information, may appear on a surface of the motion desktop. In embodiments consistent with the subject matter of this disclosure, foreground content may be rendered to a composing surface, which may be an alpha-enabled surface capable of presenting translucent items. A motion desktop module may render content for at least a portion of a background of the motion desktop to a respective shared memory, shared with a composer. The composer may periodically copy the rendered content from the shared memory to the composing surface, where the composer may compose and blend a scene from background and foreground content. The composed scene may then be presented as the motion desktop. | 07-08-2010 |
| 20100214304 | TWO DIMENSIONAL MEMORY ACCESS CONTROLLER - A data processing system may include a display, the display having a display surface, and logic to modify the address signals of a graphics processing unit (GPU) if the address signals do not fall within a two-dimensional range of authorized pixel locations corresponding to a subset of the display surface, and to propagate the address signals unmodified to a display memory otherwise. | 08-26-2010 |
| 20100309211 | ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO A SHARED MEMORY - An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image. | 12-09-2010 |
| 20110157199 | Method and Device for Processing Digital Images - Disclosed is a method of processing a digital representation comprising a plurality of cells having respective cell values and being arranged in a regular grid. The method comprises performing at least one cell data reordering operation and performing at least one arithmetic operation for computing at least a first cell value of a first cell from one or more cell values of respective cells of the digital representation, each arithmetic operation including at least one multiplication. The method comprises performing the at least one reordering operation and the at least one arithmetic operation as at least two concurrent processes, each of the concurrent processes reading respective parts of the digital representation from respective memory buffers of a shared memory. | 06-30-2011 |
| 20110285731 | Mechanism for Granting Controlled Access to a Shared Resource - Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource. | 11-24-2011 |
| 20120069035 | INTER-PROCESSOR COMMUNICATION TECHNIQUES IN A MULTIPLE-PROCESSOR COMPUTING PLATFORM - This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU. | 03-22-2012 |
| 20120081380 | CROSS-ENVIRONMENT USER INTERFACE MIRRORING - A mobile computing device with a mobile operating system and desktop operating system running concurrently and independently on a shared kernel without virtualization. The mobile operating system provides a user experience for the mobile computing device that suits the mobile environment. The desktop operating system provides a full desktop user experience when the mobile computing device is docked to a second user environment. Cross-environment rendering and user interaction support provide a seamless computing experience in a multi-operating system computing environment. The seamless computing experience includes mirroring the active user interaction space of the mobile operating system to a display of a user environment associated with the desktop operating system. The mobile computing device may be a smartphone running the Android mobile operating system and a full desktop Linux distribution on a modified Android kernel. | 04-05-2012 |
| 20120092356 | Systems and Methods for Performing Shared Memory Accesses - Various systems and methods are described for accessing a shared memory in a graphics processing unit (GPU). One embodiment comprises determining whether data to be read from a shared memory aligns to a boundary of the shared memory, wherein the data comprises a plurality of data blocks, and wherein the shared memory comprises a plurality of banks and a plurality of offsets. A swizzle pattern in which the data blocks are to be arranged for processing is determined. Based on whether the data aligns with a boundary of the shared memory and based on the determined swizzle pattern, an order for performing one or more wrapping functions is determined. The shared memory is accessed by performing the one or more wrapping functions and reading the data blocks to construct the data according to the swizzle pattern. | 04-19-2012 |
| 20120133660 | DATA PROCESSING METHOD AND APPARATUS IN HETEROGENEOUS MULTI-CORE ENVIRONMENT - A method and apparatus for processing data in a heterogeneous multi-core environment, capable of reducing data processing time by storing frames not having redundant data only among input frames in a shared memory. The apparatus compares a second frame with a first frame having a time difference with respect to a first frame, thereby determining identity between the first frame and the second frame. The apparatus stores address information related to the first frame or stores the second frame according to the determination result, thereby reducing quantity of data to be updated. | 05-31-2012 |
| 20130127885 | Handheld Electronic Device Supporting Multiple Display Mechanisms - A handheld electronic device includes a display manager configured to provide a plurality of objects for display at a plurality of display mechanisms, where at least two of the plurality of display mechanisms display at least one common object, and a control filter having preconfigured filter criteria configured to automatically determine, based on a type of an object, to which of the plurality of display mechanisms the display manager provides the object. | 05-23-2013 |
| 20140015842 | IMPLEMENTING PREVIOUSLY RENDERED FRAME BUFFER INFORMATION IN A CUSTOMIZED GUI DISPLAY - Embodiments are directed to providing direct access to graphical user interface (GUI) frame buffers and to associating input hardware with a login session. In one scenario, a computer system registers a plug-in software module with a remote desktop client. The registering includes requesting one or more frame buffers rendered for display on a computer system display. The computer system determines that a session has been established between a computer system user and the remote desktop client. The computer system then receives the requested frame buffers and displays the frame buffers on the computer system display and/or sends the received frame buffers to various registered third parties. | 01-16-2014 |
| 20140071144 | METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM - A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified. | 03-13-2014 |
| 20140132615 | DISPLAY APPARATUS AND METHOD FOR CONTROLLING THEREOF - A display apparatus is provided. The display apparatus includes a display, a memory which stores screen setting data on the display, an internal interface which performs data communication in the display apparatus, and a switch which switches between communication between the memory and a host apparatus or communication between the memory and the internal interface. The switch is driven by hot plug power or main power according to a predetermined condition, and, if the main power is turned off, the switch is driven by the hot plug power and performs communication with the host apparatus. Accordingly, the display apparatus satisfies a communication standard for recognizing apparatuses using a single memory. | 05-15-2014 |
| 20140160138 | MEMORY BASED SEMAPHORES - Memory-based semaphore are described that are useful for synchronizing operations between different processing engines. In one example, operations include executing a context at a producer engine, the executing including updating a memory register, and sending a signal from the producer engine to a consumer engine that the memory register has been updated, the signal including a Context ID to identify a context to be executed by the consumer engine to update the register. | 06-12-2014 |
| 20140176588 | TECHNIQUE FOR STORING SHARED VERTICES - A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written. | 06-26-2014 |
| 20140176589 | TECHNIQUE FOR STORING SHARED VERTICES - A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written. | 06-26-2014 |
| 20150097849 | INTER-PROCESSOR COMMUNICATION TECHNIQUES IN A MULTIPLE-PROCESSOR COMPUTING PLATFORM - This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU. | 04-09-2015 |
| 20150332429 | Exploiting Frame to Frame Coherency in a Sort-Middle Architecture - Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame. | 11-19-2015 |
| 345542000 | Unified memory architecture (e.g., UMA) | 5 |
| 20100118041 | Shared virtual memory - Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings. | 05-13-2010 |
| 20110037772 | Scalable Unified Memory Architecture - A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller. | 02-17-2011 |
| 20120182304 | Scalable Unified Memory Architecture - A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller. | 07-19-2012 |
| 20140049550 | Shared Virtual Memory - Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings. | 02-20-2014 |
| 20140375662 | SHARED VIRTUAL MEMORY - Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings. | 12-25-2014 |
