| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 345534000 | Memory access timing signals | 24 |
| 20080266304 | Display unit and method for displaying multiple images - A display unit includes: a display panel for displaying a plurality of information images; a memory for storing a plurality of image data elements corresponding to the information images; an image memory for storing the image data elements transferred from the memory; and a controller for controlling the display panel to display the information images based on the image data elements in the image memory. The controller transfers a part of the image data elements to the image memory on ahead when the display unit starts to operate, and the controller controls the display panel to display a part of information images on ahead based on the part of the image data elements. | 10-30-2008 |
| 20080297525 | Method And Apparatus For Reducing Accesses To A Frame Buffer - An apparatus comprises a first unit to receive a first frame. The first unit replaces each datum of the first frame with a datum having a particular value if the datum of the first frame is within a region of the first frame. A second frame is thereby created. The first unit also writes the second frame. | 12-04-2008 |
| 20090141036 | Video image display apparatus and buffer management method for video image display apparatus - A buffer management method implemented in a video image display apparatus for displaying images, including: controlling a write address in a buffer for writing input data thereto; controlling a read address in the buffer for reading display data therefrom; comparing the write address and read address; and managing a transmission of the display data to a spatial light modulator (SLM) based on a comparison result of comparing the write address to the read address. | 06-04-2009 |
| 20100085368 | TIMING CONTROLLER CAPABLE OF REMOVING SURGE SIGNAL AND DISPLAY APPARATUS INCLUDING THE SAME - A timing controller includes a first stage removing a first surge signal generated during a first logic level period of a data enable signal, and a second stage receiving the data enable signal generated by the first stage and removing a second surge signal generated during a second logic level period of the received data enable signal. | 04-08-2010 |
| 20110115804 | Methods and Apparatus for Image Processing at Pixel Rate - Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth. | 05-19-2011 |
| 20120154414 | INTEGRATED CIRCUIT FOR USE IN PLASMA DISPLAY PANEL, ACCESS CONTROL METHOD, AND PLASMA DISPLAY SYSTEM - Provided is a plasma display system capable of restricting peak data traffic when a shared memory is used. In the plasma display system, a control unit | 06-21-2012 |
| 20120176389 | METHODS AND APPARATUS FOR IMAGE PROCESSING AT PIXEL RATE - Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth. | 07-12-2012 |
| 20120188262 | DETECTING STATIC IMAGES AND REDUCING RESOURCE USAGE ON AN ELECTRONIC DEVICE - An electronic device for detecting static images and reducing resource usage is described. The electronic device includes a processor and instructions stored in memory. The electronic device determines image memory. The electronic device also sets a timer. The electronic device further monitors the image memory. The electronic device also determines whether there is a write access request for the image memory. Furthermore, the electronic device determines whether a time threshold has been reached based on the timer if there is not a write access request for the image memory. The electronic device also reduces display resource usage if the time threshold has been reached. | 07-26-2012 |
| 20120206465 | DISPLAY CONTROLLER DRIVER AND TESTING METHOD THEREOF - A display controller driver and a testing method thereof are provided. The display controller driver includes an image data memory, a timing control circuit, and a data line driving circuit. The image data memory stores display data. The timing control circuit obtains the display data from the image data memory. The data line driving circuit is coupled to the timing control circuit. The data line driving circuit receives the display data and outputs a grayscale voltage signal corresponding to the display data through at least one data-line output terminal of the display controller driver. In a test operation mode, the timing control circuit further transmits the display data from the image data memory to at least one test output port of the display controller driver. | 08-16-2012 |
| 20120229484 | NETWORK HARDWARE GRAPHICS ADAPTER COMPRESSION - Systems and methods of compressing and displaying the contents of multiple display devices on a single display device are presented. The display content from each of a plurality of devices is contemporaneously displayed by placing each respective desktop display raster data into video memory in a sequential order for each of the plurality of monitors and setting the scan engine to scan a single, very wide, image having a horizontal value equal to the sum of the widths of the individual displays and a vertical value equal to the original height of the individual display. | 09-13-2012 |
| 20130120420 | METHOD AND SYSTEM FOR EFFICIENTLY ORGANIZING DATA IN MEMORY - A method and system for efficiently organizing data in memory is provided. Exemplary aspects of the invention may include storing linear data and block data in more than one DRAM device and accessing the data with one read/write access cycle. Common control signals may be used to control the DRAM devices and the address lines used to address each DRAM device may be independent from one another. The data read from the DRAM devices may be reordered to make the data more suitable for processing by applications. | 05-16-2013 |
| 20130169656 | OPPORTUNISTIC FRAME BUFFER COPY FOR EFFICIENT MEMORY PARTIAL POWER DOWN - Embodiments of the present invention may be directed to a graphics system of a computer system. The system may include a frame buffer having a number of partitions respectively mapped to a number of discrete memory devices and a dedicated copy buffer operable to store new image frames, mapped to a first memory device. The first memory device corresponds to a first partition of the number of partitions. The system may also include a loader circuit coupled between the frame buffer and the dedicated copy buffer, operable to copy new image frames from the frame buffer to the dedicated copy buffer. The system may also include a clocked output coupled to receive an image frame from the dedicated copy buffer and operable to drive a display device therewith. The system may enter a low power state wherein a number of the discrete memory devices are powered off. | 07-04-2013 |
| 20130249923 | METHODS AND APPARATUS FOR IMAGE PROCESSING AT PIXEL RATE - Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth. | 09-26-2013 |
| 20130342551 | METHODS AND APPARATUS FOR IMAGE PROCESSING AT PIXEL RATE - Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth. | 12-26-2013 |
| 20140009480 | DISPLAY SYSTEM WITH DISPLAY PANEL AND DISPLAY CONTROLLER AND DRIVER HAVING MOVING PICTURE INTERFACE - No flicker is displayed on the display screen during display of moving pictures and power consumption can be reduced by adding a high quality moving picture display function. Moreover, the number of times of transfer of moving pictures by comprising a still-picture • text • system • I/O bus • interface and a moving picture interface (external display interface), providing a display operation change register (DM) and a RAM access change register (RM) which are changed selectively depending on display content (display mode) displayed on a display device and displaying the display data on the display device via a picture memory even in the moving picture display mode. | 01-09-2014 |
| 20140333642 | DISPLAY SYSTEM AND DATA TRANSMISSION METHOD THEREOF - A display system and a data transmission method thereof are provided. When a first frame stored in a frame buffer is identical to a second frame to be output from an audio and video (AV) source, the AV source is set an AV control signal corresponding to a self-refresh mode, and a timing controller reads the first frame to output a display data controlled by the AV control signal. When the first frame is differed from the second frame, the AV source is set the AV control signal corresponding to a data update mode and a AV data signal corresponding to the second frame, and the timing controller stores the second frame in the frame buffer controlled by the AV control signal and outputs the display data corresponding to the first frame or the second frame according the timing sequences of the AV data signal and the display data. | 11-13-2014 |
| 20150009224 | DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - An object of the present invention is to provide a display device and a method of driving it, capable of displaying images properly even upon asynchronous input of image data while taking advantages of decreased power consumption implemented by intermission driving. | 01-08-2015 |
| 20150042668 | TERMINAL AND CONTROL METHOD THEREOF - A terminal includes a controller, a driver, and a display. The controller transmits image data based on a first signal. The driver includes an internal memory and performs a memory write operation for the transmitted image data in the internal memory. The display output the image data, for which the memory write operation in the internal memory has been performed, based on a memory scan operation. The performs the memory scan operation at a first frequency and generates a second signal based on when the memory scan operation and memory write operation for the internal memory are to alternate. The controller transmits the image data based on the second signal. | 02-12-2015 |
| 20150049103 | CONTROL CIRCUIT FOR FRAME MEMORY, DISPLAY DEVICE INCLUDING THE SAME AND METHOD OF CONTROLLING THE SAME - A control circuit for a frame memory includes a divider, a frame memory, a read control circuit, and a write control circuit. The divider divides image data into subfield data according to a plurality of subfields, where the image data is provided in synchronization with a first synchronization signal and in a unit of a frame. The frame memory has a plurality of blocks to store the subfield data. The read control circuit sequentially reads the subfield data from the blocks in synchronization with a second synchronization signal. The write control circuit writes new data to a first block before data written in a second block is read, and after data written in the first block is read by the read control circuit. The second synchronization signal may have a same cycle as the first synchronization signal and may be delayed by a preset delay time. | 02-19-2015 |
| 20150062138 | TIMING CONTROLLER FOR IMAGE DISPLAY AND ASSOCIATED CONTROL METHOD - A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase. | 03-05-2015 |
| 20150084973 | DEVICES AND METHODS FOR INDICATING ACTIVE FRAME STARTS - Devices and methods for providing an indication of an active frame start, while reducing a number of line buffers utilized by conventional systems are provided herein. By way of example, an electronic display panel may include a host device (e.g., a processor) that provides an indication of a pending active frame start. The indication may be provided at a predetermined and fixed time/line interval before the active frame start. Next, a timing controller of the display circuitry may generate a vertical start pulse during vertical blanking based upon the indication and the fixed time/line interval. The vertical start pulse may be used to drive multi-clock integrated row driver circuits. | 03-26-2015 |
| 20150130824 | TIMING CONTROLLER TO PERFORM PANEL SELF-REFRESH USING COMPRESSED DATA, METHOD OF OPERATING THE SAME, AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A method of operating a timing controller, which communicates with a host through a mobile industry processor interface (MIPI) and communicates with a display panel module through a display interface, is provided. The method includes storing image data compressed by one of the host and the timing controller in a frame memory, decompressing the image data stored in the frame memory, and performing panel self-refresh on the display panel module using the decompressed image data. | 05-14-2015 |
| 20160078957 | MEMORY, DISPLAY DEVICE INCLUDING THE SAME, AND WRITING METHOD OF THE SAME - A memory is provided, which comprises an electrically erasable and programmable read only memory (EEPROM) configured to store an operation system and to be rewritable in response to a write operation signal, an address comparator configured to be connected to Inter Integrated Circuit (I2C) lines and output the write operation signal to the EEPROM in response to an external signal, a digital-to-analog converter (DAC) unit configured to determine whether to connect a DAC resistor and the I2C lines in response to the external signal and a pull-up resistor unit configured to be connected to the I2C lines. | 03-17-2016 |
| 20160203802 | TIMING CONTROLLER AND DISPLAY DEVICE INCLUDING THE SAME | 07-14-2016 |
