Class / Patent application number | Description | Number of patent applications / Date published |
345519000 | Integrated circuit (e.g., single chip semiconductor device) | 36 |
20080211818 | GRAPHICS PROCESSOR WITH INTEGRATED WIRELESS CIRCUIT - Circuits, methods, and apparatus that are capable of processing graphics information and wirelessly transmitting processed graphics information to a monitor. In order to achieve a high bandwidth, one embodiment of the present invention provides a graphics processor chip that includes multiple RF transmitters such that processed graphics information can be transmitted using the cumulative bandwidth of multiple wireless channels. These transmitters can use one or more RF standards or proprietary signaling schemes. | 09-04-2008 |
20080266302 | Mechanism for granting controlled access to a shared resource - Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource. | 10-30-2008 |
20080278508 | Architecture and Method for Remote Platform Control Management - An integrated circuit is a baseboard management controller that is a fully integrated system-on-a-chip microprocessor incorporating function blocks and interfaces that provide remote management solution. The integrated circuit uses a microprocessor, and a video compression accelerator in combination with a unified memory architecture to accelerate video processing, and a set of system and peripheral functions that are useful in a variety of remote management applications. The video compression accelerator generates hash map values for received image data, compares the hash map values to generate a difference map and encodes the image data corresponding to the difference map prior to the microprocessor sending the encoded video data to a client. | 11-13-2008 |
20080309672 | SYSTEM AND METHOD FOR DIGITAL VIDEO SCAN USING 3-D GEOMETRY - A system and method for providing digital video scan using 3-D geometry. The digital video scan system includes a 3-D scan scene maker for generating a plurality of video display units for displaying digital video data; a plurality of video producing devices producing a plurality of video feeds; a video scan sequencer receiving and organizing the plurality of video feeds into a predetermined order; a video rendering device rendering the digital video data from the plurality of video feeds for display within a separate one of the video display units; and video display apparatus displaying the digital video data from each video feed in the video display units. The plurality of video display units are positioned in a 3-D scene so that a plurality of video display units are at least partially viewable at the same time. Moreover, at intervals, the digital video data is incremented from one video display unit to another thus allowing an observer to view each digital video data in a foreground position. Furthermore, the observer is provided with a video data selector allowing the operator to select digital video data in one video display unit and move the selected digital video data to another video display unit. | 12-18-2008 |
20090128571 | Data Processing Hardware - This invention generally relates to data processing hardware, and more particularly to hardware accelerators and related methods for matrix factorisation especially non-negative matrix factorisation (NMF). Embodiments of the invention are particularly useful for driving electroluminescent displays such as OLED displays. A matrix factorisation hardware accelerator for determining a pair of factor matrices (R;C) which when multiplied together approximate a target matrix, the hardware accelerator comprising: an input to receive an input data matrix representing said target matrix; a first factor matrix memory for storing row and column data for a first factor matrix (R), said first factor matrix memory having a plurality of first data buses each associated with a respective block of said first factor matrix memory for accessing first factor matrix column data stored in the block; a second factor matrix memory for storing row and column data for a second factor matrix (C), said second factor matrix memory having a plurality of second data buses each associated with a respective block of said second factor matrix memory for accessing second factor matrix row data stored in the block; a matrix of processor blocks, each processor block having: a first processor block data bus coupled to one of said first data buses, a second processor block data bus coupled to one of said second data buses, and a result data output; a processor memory block for storing a portion of a matrix (Q) representing a difference between a product of said pair of factor matrices and said target matrix; and a data processor comprising at least one multiply-add unit, said data processor having a first input coupled to said processor memory block and a second input coupled to one or both of said first and second processor block data buses and having an output coupled to said result data output; and control circuitry to control writing of data from said input into said processor memory blocks of said matrix of processor blocks, to control reading of data from said first and second factor matrix memories for provision to said matrix of processor blocks, and to control writing of data derived from said result data outputs back to said first and second factor matrix memories to perform said matrix factorisation. | 05-21-2009 |
20090128572 | VIDEO AND GRAPHICS SYSTEM WITH AN INTEGRATED SYSTEM BRIDGE CONTROLLER - A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system as well as external peripheral devices. The system bridge controller is capable of performing format conversion between big-endian data and little-endian data. The system bridge controller includes a PCI bridge to interface with PCI devices, an I/O bus bridge to interface with I/O devices such as RAM, ROM, flash memory and 68000-compatible peripheral devices, and a CPU interface block to interface the CPU to video processing devices on the integrated circuit chip such as an MPEG video decoder. | 05-21-2009 |
20090251473 | RESOLVING IMAGE / DATA MISMATCH VIA ON-OFF PATTERN - A two-dimensional panel, particularly a liquid crystal display device, has a maximum display area with a width of (T×M) addressable channels. The addressable channels are addressed through a plurality of T source channel integrated circuits (ICs), with each source channel IC having M source channels. The number of addressable channels exceeds the number of channels of data in an image display data array having a width of W pixels, each pixel comprising P subpixels in the width dimension. The excess addressable channels are distributed symmetrically across the width dimension of the displayed image. In other embodiments the number of addressable channels is less than the number of channels of data and excess channels of data are excluded symmetrically across the width dimension of the displayed image. Further embodiments distribute excess addressable channels symmetrically across the height dimension or exclude excess channels of data symmetrically across the height dimension. | 10-08-2009 |
20090309885 | Performance allocation method and apparatus - In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for the graphics process in order to allocate performance resources to the graphics process and in some cases, between the graphics process and a central processing unit. | 12-17-2009 |
20100079470 | SEMICONDUCTOR DEVICE, GRAPHICS CONTROLLER, AND INFORMATION PROCESSING METHOD - A semiconductor device includes a data acquisition unit which acquires first graphic data including a first drawing position in a drawing region, and acquires second graphic data including a second drawing position different from the first drawing position in the drawing region located later than the first graphic data, a detector which detects positions in a first direction in the drawing region of the first drawing position and the second drawing position, and a controller which causes drawing information at the first drawing position and drawing information at the second drawing position to be continuously stored in a memory when the positions of the first drawing position and the second drawing position in the first direction are similar. | 04-01-2010 |
20100079471 | Display System Having Floating Point Rasterization and Floating Point Framebuffering - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data. | 04-01-2010 |
20100110085 | MICROCONTROLLER WITH INTEGRATED GRAPHICAL PROCESSING UNIT - A microcontroller with an integrated special instruction processing unit and a programmable cycle state machine. The special instruction processing unit allows offloading of intensive processing of output data and the programmable cycle state machine minimizes the amount of customized, off chip circuitry necessary to connect the microcontroller to an external display. | 05-06-2010 |
20100182330 | Small, Adaptable, Real-Time, Scalable Image Processing Chip - An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed. | 07-22-2010 |
20100259548 | SEMICONDUCTOR DEVICE - The present invention intends to realize a narrow frame of a system on panel. In addition to this, a system mounted on a panel is intended to make higher and more versatile in the functionality. In the invention, on a panel on which a pixel portion (including a liquid crystal element, a light-emitting element) and a driving circuit are formed, integrated circuits that have so far constituted an external circuit are laminated and formed. Specifically, of the pixel portion and the driving circuit on the panel, on a position that overlaps with the driving circuit, any one kind or a plurality of kinds of the integrated circuits is formed by laminating according to a transcription technique. | 10-14-2010 |
20110074792 | ULTRASONIC IMAGE PROCESSING SYSTEM AND ULTRASONIC IMAGE PROCESSING METHOD THEREOF - An exemplary ultrasonic image processing system includes an ultrasonic transmitting apparatus, an ultrasonic receiving apparatus, a front-end processing circuit and a computer. The front-end processing circuit is electrically coupled to an ultrasonic probe through the ultrasonic transmitting apparatus and the ultrasonic receiving apparatus respectively. The computer is electrically coupled to the front-end processing circuit. The computer includes a central processing unit (CPU) and a graphics processing unit (GPU). The system employs the CPU to control the operations of the ultrasonic transmitting apparatus and the ultrasonic receiving apparatus through the front-end processing circuit, so as to acquire ultrasound scanning data. The system further employs the GPU to perform an image reconstruction process on the acquired ultrasound scanning data by way of multi-thread process, so as to generate an image display data. Moreover, a corresponding ultrasonic image processing method is also disclosed. | 03-31-2011 |
20110074793 | ELECTRICAL DEVICE SUPPORTING SWITCHABLE GRAPHICS FUNCTION AND METHOD FOR CONTROLLING THEREOF - An electrical device supporting switchable graphics function, electrically connected with a display unit, includes a first graphic chip, a second graphic chip, a peripheral, an Embedded Controller (EC) and a processing unit. Information of a present graphic chip is stored in an EC RAM of the EC, wherein the present graphic chip is one of the first graphic chip and the second graphic chip. A control unit of the EC obtains the information of the present graphic chip from the EC RAM and controls operation status of the peripheral according to the obtained information of the present graphic chip. The processing unit obtains the information of the present graphic chip from the EC RAM. The processing unit drives the present graphic chip to process an image signal and transmit the processed image signal to the display unit for display according to the obtained information of the present graphic chip. | 03-31-2011 |
20110169842 | DISPLAY SYSTEM HAVING FLOATING POINT RASTERIZATION AND FLOATING POINT FRAMEBUFFERING - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data. | 07-14-2011 |
20110169843 | TRANSISTOR ARRAY, MANUFACTURING METHOD THEREOF AND IMAGE PROCESSOR - An image processor by way of a transistor array in which a plurality of transistors are formed on a substrate comprising a plurality of polysilicon thin-film transistors using a first semiconductor layer composed of polysilicon formed on the substrate and functional devices having a plurality of amorphous silicon thin-film transistors using a second semiconductor layer composed of amorphous silicon which are formed in an upper layer more superior than the first semiconductor layer. The polysilicon thin-film transistors and functional devices include a plurality of electrode layers composed of a conductor layer, for instance, the functional devices at least of any one of the electrode layers are formed in the same layer as any one the electrode layers of the polysilicon thin-film transistors. | 07-14-2011 |
20120007871 | ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO A SHARED MEMORY - An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image. | 01-12-2012 |
20120032966 | SEMICONDUCTOR DEVICE - The present invention intends to realize a narrow frame of a system on panel. In addition to this, a system mounted on a panel is intended to make higher and more versatile in the functionality. In the invention, on a panel on which a pixel portion (including a liquid crystal element, a light-emitting element) and a driving circuit are formed, integrated circuits that have so far constituted an external circuit are laminated and formed. Specifically, of the pixel portion and the driving circuit on the panel, on a position that overlaps with the driving circuit, any one kind or a plurality of kinds of the integrated circuits is formed by laminating according to a transcription technique. | 02-09-2012 |
20120169744 | Power Supplying Unit and Liquid Crystal Display Device Including the Same - A power supplying unit for a liquid crystal display device includes: a power integrated circuit for generating a source voltage and a compensation voltage, the compensation voltage linearly varying according to an ambient temperature; and a charge pumping part for generating a gate high voltage using the source voltage and the compensation voltage, the gate high voltage linearly varying when the ambient temperature is lower than a reference temperature. | 07-05-2012 |
20120188260 | GRAPHICS CONTROLLER INTEGRATED CIRCUIT WITHOUT MEMORY INTERFACE - A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection. | 07-26-2012 |
20120249561 | FLOATING POINT COMPUTER SYSTEM WITH S_E_M FORMATTING - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data. | 10-04-2012 |
20120249562 | FLOATING POINT COMPUTER SYSTEM WITH FOG - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data. | 10-04-2012 |
20130021351 | METHOD AND SYSTEM FOR CONTROLLING MULTIMEDIA MONITOR - A method and a system for controlling a multimedia monitor are provided. The multimedia monitor has a central processing unit (CPU) and communicates with a computer system through a communication interface. The multimedia monitor displays images from the computer system when the multimedia monitor is in an external signal mode, and displays images generated by the CPU when the multimedia monitor is in a multimedia application mode. In the method, an input event is received by the computer system and an input command corresponding to the input event is transmitted to the multimedia monitor through the communication interface. After that, whether the input command belongs to a multimedia command set is determined by the multimedia monitor. If the input command belongs to the multimedia command set, an action corresponding to the input command under the multimedia application mode is executed by the multimedia monitor. | 01-24-2013 |
20130057559 | DISPLAY DEVICES - A display device includes a panel including pixels defined by data lines and gate lines, a housing chassis covering a sidewall and an edge of the panel, a printed circuit board under the panel, the printed circuit board including circuit elements configured to generate at least one of a data signal, a gate signal, and a control signal, a chip on film connecting the printed circuit board to the panel, the chip on film between the housing chassis and the sidewall of the panel, a driver integrated circuit mounted on the chip on film and configured to respond to the control signal and drive at least one of the data signal and the gate signal applied to the data lines and the gate lines, and a connection unit attaching the chip on film to the housing chassis and dissipating heat generated by the driver integrated circuit to the housing chassis. | 03-07-2013 |
20130106872 | INTEGRATED CIRCUIT FOR DISPLAY APPARATUS AND METHOD THEREOF | 05-02-2013 |
20130222401 | SEMICONDUCTOR PACKAGE, AND INFORMATION PROCESSING APPARATUS AND STORAGE DEVICE INCLUDING THE SEMICONDUCTOR PACKAGES - According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer. | 08-29-2013 |
20140063026 | SOC PERFORMING DYNAMIC VOLTAGE AND FREQUENCY SCALING POLICIES USING 3D WORKLOAD, AND METHOD USING THE SAME - A semiconductor device includes a graphics processor unit (GPU) configured to receive three-dimensional (3D) input data and a central processing unit (CPU) configured to receive the 3D input data and adjust a frequency and operating voltage of the GPU based on the 3D input data. The GPU performs image processing on the 3D input data based on the adjusted frequency and the operating voltage. | 03-06-2014 |
20140184619 | SYSTEM-ON-CHIP PERFORMING DYNAMIC VOLTAGE AND FREQUENCY SCALING - A system-on-chip (SoC), measures the workload of a graphics processing unit (GPU), compares the frame process speed of the GPU with the frame rate of a display device, and adjusts the operating frequency of the GPU based on the comparison result and the workload of the GPU. | 07-03-2014 |
20140218378 | SYSTEM ON CHIP FOR UPDATING PARTIAL FRAME OF IMAGE AND METHOD OF OPERATING THE SAME - A system on chip (SoC) and a method of operating the same are provided. The SoC includes a central processing unit (CPU) controlling a memory operation and a display operation on a current frame of an image based on generation of the image and an interrupt signal; an image generator requesting data of the current frame from a memory according to control of the CPU; a UD unit determining whether the current frame is updated, detecting whether an update region is a partial frame based on virtual addresses included in a request of the image generator, and outputting the interrupt signal corresponding to the update region to the CPU; a memory controller storing the update region in the memory according to the control of the CPU; and a display controller accessing the memory and outputting the update region to a display device according to the control of the CPU. | 08-07-2014 |
20140306968 | Method of Reading Data, Method of Transmitting Data and Mobile Device thereof - A method of reading data for a display drive IC of a panel is provided. The method includes receiving a write format and at least one image packet, generating a synchronization signal according to the write format, and reading data of the at least one image packet according to the synchronization signal such that the panel uses a video mode to display the data of the at least one image packet. | 10-16-2014 |
20150015591 | HOST FOR CONTROLLING FREQUENCY OF OPERATING CLOCK SIGNAL OF DISPLAY DRIVER IC AND SYSTEM INCLUDING THE SAME - A display driver integrated circuit (DDI) for driving a display of image data on a display panel, an application processor (AP), a system including the DDI and the AP, and methods of operating the same are provided. The application processor includes: a controller configured to obtain a frequency of a data transmission timing control received from a display driver integrated circuit (DDI), and to generate, based on the obtained frequency, a frequency control signal for adjusting a frequency related to an operating clock signal for the DDI; a transmitter configured to transmit the generated frequency control signal to the DDI; and a frequency calculation circuit including: a detector configured to receive the data transmission timing control signal from the DDI, and a frequency calculator configured to calculate a frequency of the received data transmission timing control signal. | 01-15-2015 |
20150339796 | APPARATUS AND METHOD FOR CONTROLLING VIDEO OUTPUT OF AUDIO VIDEO NAVIGATION SYSTEM - The present invention provides an apparatus for controlling a video output of an audio video navigation (AVN) system, including: a display unit which displays a video in the AVN system; a signal dividing unit which divides an input first signal, transmits the video to the display unit using a second signal obtained by dividing the first signal and senses a user input on the display unit using a third signal obtained by dividing the first signal; and a video output control unit which controls an output of a video which conforms with a predetermined standard, using the first signal and controls an output of a video corresponding to the user input. | 11-26-2015 |
20160086564 | MULTI-PROTOCOL SUPPORT FOR DISPLAY DEVICES - Systems and methods of the present disclosure include transmitter devices. The transmitter devices include a high-speed driver domain having a low-dropout regulator. The low-dropout regulator reduces a voltage level from an input voltage source to the high-speed driver domain. In addition, the transmitter devices include a low-speed driver domain. The low-speed driver domain includes a pre-driver which reduces a voltage level from an input voltage source to the low-speed driver domain. | 03-24-2016 |
20160104451 | METHOD, SYSTEM, AND APPARATUS FOR BATTERY LIFE EXTENSION AND PERIPHERAL EXPANSION OF A WEARABLE DATA COLLECTION DEVICE - An apparatus for providing an external power supply, memory device, camera, and/or other peripheral capabilities to a head-mounted data collection device may include a first portion releasably connecting to the data collection device. The first portion may have a first data port interface configured for connection to a corresponding data port interface of the data collection device. The apparatus may have a second portion releasably connectable to the first portion, the second portion including an internal data port interface configured for connection to a corresponding internal data port interface of the first portion, a power cell module, and a power supply interface configured for connection to a corresponding power supply input of the head-mounted wearable data collection device. The first portion and/or the second portion may include interface logic for receiving data via the first data port and command logic for issuing commands to the data collection device. | 04-14-2016 |
20160133225 | PROCESSING SYSTEM DISPLAY CONTROLLER INTERFACE TO PROGRAMMABLE LOGIC - In an example, a programmable integrated circuit (IC) includes programmable logic and a display controller. The display controller includes a first interface coupled to receive coded data, a renderer to generate display-agnostic data from the coded data, a transmitter to generate display data from the display-agnostic data in accordance with a first protocol, a second interface coupled to provide the display data as output, and a third interface coupled to provide the display-agnostic data to the programmable logic. | 05-12-2016 |