Class / Patent application number | Description | Number of patent applications / Date published |
341172000 | Using charge transfer devices (e.g., charge coupled devices, charge transfer by switched capacitances) | 85 |
20080211706 | Capacitive digital to analog and analog to digital converters - A pipelined analog-to-digital converter (ADC) comprises a first stage that receives an input voltage signal and that comprises an analog-to-digital converter (ADC). The ADC includes an amplifier having an input and an output. N capacitances are connected in parallel and include first ends that selectively communicate with the input and second ends. N switches selectively connect the second ends of the N capacitances to the voltage input during a first phase, one of the second ends of the N capacitances to the output of the amplifier during a second phase, and others of the second ends of the N capacitances to one of a voltage reference and a reference potential during the second phase. A second stage communicates with the output the amplifier. | 09-04-2008 |
20080246646 | Charge-domain pipelined analog-to-digital converter - An ADC implementation of a bucket brigade type charge transfer pipeline using Metal Oxide Semiconductor (MOS) Bucket Brigade Devices (BBDs) that can be used in Analog-to-Digital (A/D) converters and other applications. In one embodiment a control circuit provides independent control of charge storage and charge transfer timing. Other arrangements provide high-speed and high-accuracy (A/D) conversion by employing a “boosted” charge-transfer circuit. The implementation can also achieve lower power consumption and improved resolution compared to other charge-domain methods by the use of a tapered pipeline, in which the amount of charge being processed is reduced in later pipeline stages compared to earlier ones. Still other embodiments enable implementing more than one decision threshold per stage, to support multi-bit resolution per stage and RSD-type A/D conversion algorithms. | 10-09-2008 |
20080297393 | Low power 10 gigabit ethernet interface - A low-power communication interface, such as used with 10 Gigabit Ethernet, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline. | 12-04-2008 |
20080303705 | A/D conversion circuit, control method thereof, solid-state imaging device, and imaging apparatus - An A/D conversion circuit includes: an input capacitance to which an input signal and a reference signal are sequentially applied; an operational amplifier; a first switch connected between the other end of the input capacitance and a first input end of the operational amplifier; a feedback capacitance connected to the first input end of the operational amplifier; a second switch connected between the other end of the feedback capacitance and an output end of the operational amplifier; a third switch selectively applying a predetermined voltage to the other end of the feedback capacitance; a fourth switch selectively causing a short circuit between the first input end and the output end of the operational amplifier; a fifth switch applying the predetermined voltage to a second input end of the operational amplifier; and a sixth switch applying a ramp reference voltage to the second input end of the operational amplifier. | 12-11-2008 |
20090002216 | Method and device for processing an incident signal, in particular for filtering and analogue/digital conversion - The method and device include the filtering and the analog/digital conversion of an intermediate signal. The intermediate signal is processed by a filtering and analog/digital conversion circuit that is configurable using switched passive capacitor technology. The various configurations successively adopted by the circuit provide filtering and analog/digital conversion to be successively carried out. | 01-01-2009 |
20090009376 | Device for measuring an electric charge in digitized form - The present invention relates to a device for measuring an electric charge in digitized form. The digitized value is coded on N bits. The device has at least a battery of N capacitors ( | 01-08-2009 |
20090015455 | Analog-to-digital converter, method of controlling the same, and wireless transceiver circuit - In an analog-to-digital converter, when a capacitive element with a small capacitance is used in order to reduce power consumption, the characteristics of the analog-to-digital converter deteriorate due to the variation in the specific accuracy. Further, the method of reducing the variation with the specific accuracy causes an increase in the size of the circuit and power consumption. An analog-to-digital converter includes an analog core unit having at least one capacitive element. The capacitive element includes a capacitive bank having plural capacitive element units having substantially the same capacitance value, and the capacitive bank is configured to select one capacitive element unit from the plural capacitive element units with substantially equal probability. | 01-15-2009 |
20090066556 | Method and Device for Controlling a Successive Approximation Register Analog to Digital Converter - A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator. | 03-12-2009 |
20090102695 | A/D Converter with Noise Cancel Function - An A/D converter comprises capacitors C | 04-23-2009 |
20090121912 | Circuits and methods to reduce or eliminate signal-dependent modulation of a reference bias - Circuits and methods that improve the performance of voltage reference driver circuits and associated analog to digital converters are provided. A voltage reference driver circuit that maintains a substantially constant output voltage when a load current is modulated by an input signal is provided. The voltage reference driver circuit synchronously decouples a voltage regulation circuit from the load circuit when modulating events such as pulses caused by the load circuit during a switching interval are generated, preventing disturbance of the regulation circuitry and keeping its output voltage substantially constant. | 05-14-2009 |
20090128391 | SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period. | 05-21-2009 |
20090135041 | Analog-to-digital converter for accumulating reference voltages successively divided by two - An analog-to-digital converter includes a ½ powered signal generator configured to generate divided signals by successively dividing a full scale signal by 2 and output one of the divided signals, an accumulator configured to update a reference signal according to a current divided signal and a current output bit, and a comparator configured to compare the updated reference signal with an input signal and generate a next output bit. | 05-28-2009 |
20090167587 | ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) and a battery operated electronic device comprising the ADC. The ADC comprising an input switch; an array of binary-weighted capacitors, the array of capacitors receiving the input voltage signal via the input switch in an on state of the input switch; a plurality of switches, each switch connected in series with a respective one of the capacitors at an opposite side compared to the input switch, wherein a VDD signal is applied to each switch in one switching state and ground in another switching state; a comparator having as one input a voltage from the input switch side of the array of capacitors and as another input a voltage of VDD/2; and a switch control unit coupled to an output of the comparator for controlling the switches based on the output from the comparator. | 07-02-2009 |
20090251350 | CURRENT SAMPLING MIXER WITH HARMONIC REJECTION - Provided is a current sampling mixer that can be applied to a broadband broadcasting system. The current sampling mixer can change a structure of a current sampler including a plurality of capacitors to select and sum capacitors having a weight value given in the output, thereby performing a finite impulse response filter function and a harmonic rejection function. | 10-08-2009 |
20090322580 | ANALOG FILTER WITH PASSIVE COMPONENTS FOR DISCRETE TIME SIGNALS - A filter intended to receive a discrete time signal at a sampling dock frequency, comprising a determined number, greater than 2, of filtering units, each filtering unit comprising head capacitors in a number equal to the determined number, assembled in parallel between an input terminal and the terminal of an integration capacitor; and means for connecting, in successive clock cycles in a number equal to the determined number, successively each head capacitor to the input terminal, and for then simultaneously connecting the head capacitors to the integration capacitor, and in which the successive dock cycles during which the head capacitors of a filtering unit are connected to the input terminal are offset by one dock cycle from one filtering unit to the next one. | 12-31-2009 |
20100001892 | SUCCESSIVE APPROXIMATION A/D CONVERTER - A successive approximation A/D converter includes a capacitive D/A converter including capacitors, and generates a voltage based on the input voltage and a first digital signal including J bits; a resistive D/A converter that generates a voltage based on a second digital signal; a capacitor that capacity-couples the voltage to an output node; a comparator that generates a result based on the voltage; a control circuit that supplies the first digital signal to the capacitive D/A converter according to the result and outputs a third digital signal indicating a correction and a fourth digital signal including K bits; and a digital calculating circuit that generates the second digital signal including K bits based on the third digital signal and the fourth digital signal, and supplies the second digital signal to the resistive D/A converter, a (J+K) bit digital data is generated based on the input signal. | 01-07-2010 |
20100026546 | SAR ADC - An electronic device is provided for analog to digital conversion using successive approximation. The device comprises a first ADC stage. The first ADC stage includes a first plurality of capacitors adapted to sample an input voltage, and adapted to be coupled to either a first reference signal level or a second reference signal level. At least one capacitor of the first plurality of capacitors is adapted to be left floating. A control stage is adapted to switch the at least one floating capacitor to the first reference signal level or the second reference signal level in response to an analog to digital conversion decision made by a second ADC stage. | 02-04-2010 |
20100117883 | Cable Gateway Using A Charge-Domain Pipeline Analog to Digital Converter - A cable gateway, such as compatible with version 3.0 of the Data Over Cable Service Interface Specifications and other audiovisual standards, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline of at least two stages. | 05-13-2010 |
20100141499 | APPARATUS AND METHOD FOR SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION - A successive approximation analog-to-digital converter (ADC) includes a binary-weighted capacitor array, quantizer, and control block. One end of each capacitor is connected to the input of the quantizer, and a second end of each capacitor is controlled by the control block through a driver. A voltage is sampled, quantized, and stored as the most significant bit of the ADC's output. Depending on the result of the quantization, the control block toggles the driver of one of the capacitors corresponding to the most significant bit. The voltage at the common node is sampled again to obtain a second bit of the ADC's output. The operations are repeated as needed to obtain and store additional bits of the ADC's output. Similar configuration and process are described for a differential ADC. The operation is asynchronous, allowing extra time for metastable states only when such states occur. | 06-10-2010 |
20100141500 | SOLID STATE IMAGE PICKUP ELEMENT AND CAMERA SYSTEM - A solid state image pickup element includes a pixel unit having a plurality of pixels for photoelectric conversion disposed in a matrix shape and a pixel signal read circuit for reading pixel signals in the unit of a plurality of pixels from the pixel unit. The pixel signal read circuit includes a plurality of comparators disposed in correspondence with a pixel column layout for performing comparison judgment between a read signal potential and a reference voltage and outputting a judgment signal and a plurality of counters each for counting a comparison time of a corresponding one of the comparators, an operation being controlled by an output from a corresponding one of the comparators. The comparators include a first amplifier for performing a comparison operation between the reference voltage and the read signal potential and inverting an output at a predetermined comparison point, a second amplifier for forming a current path when an output of the first amplifier is inverted, to output an output of the first amplifier by gain up, and a current control circuit for shutting the current path of the second amplifier when an output level of the second amplifier exceeds a predetermined threshold level. | 06-10-2010 |
20100188278 | CHARGE REDISTRIBUTION SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND RELATED OPERATING METHOD - The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balacing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage. | 07-29-2010 |
20100194621 | AD CONVERTER CIRCUIT AND OPTICAL SENSOR - The A/D converting circuit | 08-05-2010 |
20100225519 | EDC ARCHITECTURE - A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply. | 09-09-2010 |
20100328131 | Capacitive Integrate and Fold Charge-to-Digital Converter - A circuit for converting a charge signal into a binary format of output bits comprises: an integration circuit including an operational transconductance amplifier having an inverting input terminal and an output terminal, an integrating capacitor connected between the inverting input terminal and the output terminal, the integrating capacitor for storing a charge input selectively provided by a sensor diode; and a folding circuit having a fold capacitor, the fold capacitor switchably coupled either to a fold voltage source via a fold buffer for charging the fold capacitor to a predetermined fold charge value, or to the integrating capacitor for selectively removing at least a portion of the stored charge input. | 12-30-2010 |
20110095930 | SWITCHED-CAPACITOR PIPELINE ADC STAGE - A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (ISI) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device. | 04-28-2011 |
20110133974 | SWITCHED-CAPACITOR INPUT CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER INCLUDING THE SAME - A switched-capacitor input circuit which receives an analog input signal, and samples and holds the analog input signal, comprising a differential amplifier, a first capacitor, one terminal of the first capacitor being connected to a non-inverting input terminal of the differential amplifier, a second capacitor, one terminal of the second capacitor being connected to an inverting input terminal of the differential amplifier, a first switch configured to connect the other terminal of the first capacitor to one of a first reference voltage and a second reference voltage, a second switch configured to connect the other terminal of the second capacitor to one of the first reference voltage and the second reference voltage, and a third switch configured to connect the other terminal of the first capacitor to the other terminal of the second capacitor. | 06-09-2011 |
20110193736 | SWITCHED-CAPACITOR PIPELINE STAGE - A circuit for an N-bit stage ( | 08-11-2011 |
20110227774 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-DIGITAL CONVERTER AND METHOD FOR OPERATING THE SAME - A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2 | 09-22-2011 |
20110234441 | CYCLIC A/D CONVERTER - A control circuit connects a capacitor to an input terminal and an output terminal of an operational amplifier and applies a signal charge to charge the capacitor with a switch being turned off. Thus, a conversion voltage corresponding to the signal charge is outputted from the operational amplifier. The control circuit then sets charges, which correspond to the conversion voltage, in capacitors and reallocates the charges among the capacitors by connecting non-common electrodes of the capacitors to either one of a plurality of reference voltage lines in accordance with a conversion result of an A/D conversion circuit with the capacitor being connected to the input terminal and the output terminal of the operational amplifier. The control circuit thereafter performs, a number of times, charge setting, initialization and subsequent charge reallocation in accordance with a residual voltage outputted from the operational amplifier. | 09-29-2011 |
20120056770 | SUCCESSIVE APPROXIMATION REGISTER-ANALOG DIGITAL CONVERTER AND RECEIVER - An SAR-ADC includes input and reference terminals, first and second capacitor sets, a dummy capacitor, a comparator, a switch, and a logic. The first and second capacitor sets include first and second capacitors, respectively. The first capacitor has a first capacitance. The second capacitor has a second capacitance. The dummy capacitor has a third capacitance. The comparator compares an output voltage with a ground voltage and outputs a digital output code in accordance with a difference between the output and ground voltages. The switch is connected among the first capacitors of the first and second capacitor sets, and the reference terminal. The logic turns the switch based on the digital output code. The input terminal is located between the first and second capacitors of the first capacitor set. The second capacitor of the first capacitor set is located between the first and second capacitors of the second capacitor set. | 03-08-2012 |
20120105265 | Low power bit switches and method for high-voltage input SAR ADC - A switched capacitor circuit, which may be an SAR ADC, includes a plurality of bit switching circuits ( | 05-03-2012 |
20120112947 | WIDE RANGE CHARGE BALANCING CAPACITIVE-TO-DIGITAL CONVERTER - A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor. | 05-10-2012 |
20120112948 | COMPACT SAR ADC - A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage. | 05-10-2012 |
20120133541 | ANALOG-DIGITAL CONVERTER - An analog-digital converter includes converter units and a control unit. The converter units each including a comparator for performing a comparison using an input voltage, one or more capacitor ladders each having a signal line connected with first terminals of capacitors and with one input of the comparator, and switches each of which is associated with one of the capacitors, connected to a second terminal of the respective capacitor with a first or a second reference potential, the input voltage being shifted when switching one or more of the switches. The control unit controls the number of converter units, and to set the switching states of the plurality of switches in conversion cycles and to obtain comparison results from each of the comparators in a comparison subsequent to each setting of the switching states. | 05-31-2012 |
20120146830 | ANALOG DIGITAL CONVERTER - Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array. | 06-14-2012 |
20120162000 | SWITCHED CAPACITOR CIRCUIT AND STAGE CIRCUIT FOR AD CONVERTER - A switched capacitor circuit, which is operable in two or more kinds of operation modes including a first and second operation modes, includes an amplifier and two or more internal capacitors with switches for controlling connection/disconnection of the capacitor. In the first operation mode that precedes the second operation mode, the switched capacitor circuit generates the first analog output voltage by using the first internal capacitor connected between an input terminal and output terminal of the amplifier by using its switches, the other internal capacitances connected between an input terminal of the amplifier and each analog input voltage supply by using its switches. In the second operation mode, the switched capacitor circuit generates the second analog output voltage with larger feedback factor of the amplifier than it in the first operation mode, by removing some of the internal capacitors, except the first internal capacitor, from the first operation mode. | 06-28-2012 |
20120218137 | LOW-POWER AREA-EFFICIENT SAR ADC USING DUAL CAPACITOR ARRAYS - An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array. | 08-30-2012 |
20120268304 | SWITCHED-CAPACITOR CIRCUIT AND PIPELINED ANALOG-TO-DIGITAL CONVERTER - A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor. | 10-25-2012 |
20120280846 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased. | 11-08-2012 |
20120326909 | SIMULTANEOUSLY-SAMPLING SINGLE-ENDED AND DIFFERENTIAL TWO-INPUT ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) system configured to receive a first and a second analog quantity and to provide a plurality of numerical parameters representative of the first and second analog quantities. The ADC system includes a first, a second, and a third ADC circuit, and a digital interface circuit. The first ADC circuit is configured to provide a first code representative of the first analog quantity and to provide a first analog residue quantity representative of the first analog quantity with respect to the first code. The second ADC circuit is configured to provide a second code representative of the second analog quantity and to provide a second analog residue quantity representative of the second analog quantity with respect to the second code. The third ADC circuit is configured to receive the first and second analog residue quantities, and to provide a third digital code representative of a difference of the first and second analog residue quantities. The digital interface circuit is configured to receive the first, second, and third codes, and to provide the plurality of numerical parameters representative of the first and second analog quantities. | 12-27-2012 |
20130002467 | TWO-STAGE ANALOG-TO-DIGITAL CONVERTER USING SAR AND TDC - Various embodiments of this disclosure may describe a two-stage ADC circuit, and a time-interleaved system based on the two-stage ADC circuit. The two-stage ADC circuit may include a SAR converter for the first stage and a charge based TDC for the second stage. The two-stage ADC circuit may be used in high performance serial I/O applications. Other embodiments may be disclosed and claimed. | 01-03-2013 |
20130002468 | ANALOG-DIGITAL CONVERTER - An analog-digital converter includes a decision unit configured to evaluate a comparison potential in a decision step to obtain a comparison result; a number of charging units each comprising a switchable capacitor and an associated reference potential source, wherein each charging unit is configured to change the comparison potential by connecting the reference potential source to the switchable capacitor; and a control unit configure to successively switching one of the charging units following a previous decision step wherein, depending on the obtained comparison result the comparison potential is applied with a predetermined charge by the one respective charging unit, and wherein at least two of the charging units have an associated reference potential source providing different reference potentials. | 01-03-2013 |
20130002469 | CONFIGURING AN ANALOG-DIGITAL CONVERTER - A method for operating an analog-digital converter including a number of charging units, each comprising a switchable capacitor and an associated reference potential source, includes evaluating a comparison potential in successive decision steps to obtain a comparison result; and successively switching one of the charging units following a previous one of the decision steps, wherein, depending on the obtained comparison result, the comparison potential is changed by the one respective charging unit by connecting the associated reference potential source to the switchable capacitor, wherein in two of the successive switching steps different reference potentials are applied to the switchable capacitor. | 01-03-2013 |
20130015996 | AD CONVERTER AND INFORMATION PROCESSING APPARATUSAANM FURUTA; MasanoriAACI Odawara-shiAACO JPAAGP FURUTA; Masanori Odawara-shi JP - An analog-to-digital converter includes: weighted capacitors connected to each other at one ends thereof, having a capacitance value weighted at a predetermined ratio, and including a variable capacitance capacitor capable of reducing the capacitance value; a comparator including an input to which the one ends of the weighted capacitors are coupled; switches that connect the other ends different from the one ends to any of an input terminal into which an input signal is input, a reference voltage source used for successive approximation of the input signal, a ground, and an open terminal; a successive approximation controller that controls the switches to sample the input signal onto the weighted capacitors, and use the reference voltage source to generate a comparative voltage for the successive approximation, to thereby execute a successive approximation; and a capacitance controller that controls the switches to reduce a capacitance value of the variable capacitance capacitor. | 01-17-2013 |
20130021190 | SYSTEMS AND METHODS FOR DATA CONVERSION - Systems and methods are provided for converting analog data to digital data that can include performing N successive analog subtractions from an initial data charge Qin. The analog subtractions are performed using an amplifier coupled to a discharge capacitor and a divider circuit coupled to an input of the amplifier. The divider circuit includes a first capacitor, a second capacitor, and a switch to alternately divide a remaining charge Q by 2 | 01-24-2013 |
20130021191 | SYSTEMS AND METHODS FOR DATA CONVERSION - Systems and methods are provided for converting analog data to digital data that can include a discharge capacitor coupled to a voltage source. The voltage source supplies an initial data charge to the discharge capacitor; an amplifier coupled to the discharge capacitor; a divider circuit coupled to the amplifier; and a comparator coupled to the amplifier and the divider circuit. The divider circuit includes a first capacitor, a second capacitor, and a switch that is operated to alternately divide a remaining charge Q by 2 | 01-24-2013 |
20130076553 | SAR ADC CAPABLE OF REDUCING ENERGY CONSUMPTION - An SAR ADC capable of reducing energy consumption, including a voltage selecting circuit for configuring a capacitor circuit to form a first equivalent capacitor having a capacitance of (2m−1)C, a second equivalent capacitor having a capacitance of (2 | 03-28-2013 |
20130076554 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER - A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators. | 03-28-2013 |
20130082855 | ANALOG-DIGITAL CONVERTER - A method and apparatus for operating an analog-digital converter for converting an input signal into a multibit output in one conversion cycle. The method includes loading a capacitor array by applying a given input signal potential, evaluating a sampling potential provided by the capacitor array in a number of consecutive decision steps performed by at least two decision latches and changing the sampling potential by switching the capacitor array for each decision step based on a result of the step of evaluating the sampling potential, where the step of evaluating at least one of the decision latches performs the evaluating for two decision steps. | 04-04-2013 |
20130088377 | Microcontroller ADC with a Variable Sample & Hold Capacitor - An ADC module includes an analog to digital converter coupled with an analog bus, wherein the an analog to digital converter comprises a main sample and hold capacitor; and a plurality of additional sample and hold capacitances which can be programmably coupled in parallel with said main sample and hold capacitance. | 04-11-2013 |
20130120180 | A/D CONVERTER - An A/D converter | 05-16-2013 |
20130147649 | Analogue to Digital Converter, An Integrated Circuit and Medical Device - An analogue to digital converter comprises a first input connection to receive a first part of the analogue input signal; a second input connection to receive a second part of the analogue input signal; a first and second plurality of capacitors, each capacitor of the first plurality of capacitors forms a capacitor pair with a corresponding capacitor in the second plurality of capacitors; wherein, during a sampling period, the first input connection couples the first part of the analogue input signal to a first contact of each capacitor of the first plurality of capacitors, the second input connection couples the second part of the analogue input signal to a first contact of each capacitor of the second plurality of capacitors, and a switching array couples a second contact of each capacitor of the first and second plurality of capacitors to a common mode voltage to determine a first bit of the digital output signal. | 06-13-2013 |
20130169464 | METHOD AND APPARATUS FOR CONVERSION OF PORTION OF ELECTRIC CHARGE TO DIGITAL WORD - The solution according to the invention consisting in conversion of a portion of electric charge to a digital word of a number of bits equal to n by the use of successive redistribution of charge in the array (A) of binary-scaled capacitors (C | 07-04-2013 |
20130169465 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF - A successive approximation analog to digital converter and a conversion method thereof are provided. The successive approximation analog to digital converter includes a sample circuit, a conversion circuit, and a filtering control circuit. The sample circuit is configured to sample an analog voltage from an analog signal. The conversion circuit is configured to convert the analog voltage into a digital voltage. The filtering control circuit is configured to transmit a filtering control signal to the sample circuit according to the digital voltage. The sample circuit further samples a next analog voltage from the analog signal and adjusts the next analog voltage into an adjusted analog voltage according to the filtering control signal. The conversion circuit further converts the adjusted analog voltage into a next digital voltage, wherein the next digital voltage is a filtered digital voltage. | 07-04-2013 |
20130194121 | Performing Digital Windowing In An Analog-to-Digital Converter (ADC) - In one embodiment, a data acquisition circuit includes an analog multiplexer to receive analog signals and select an analog signal for output, an ADC coupled to the multiplexer to receive the analog signal and perform a conversion of the analog signal to a N-bit digital value in at least N clock cycles, and a controller coupled to the ADC to enable the ADC to compare the analog signal to a second analog signal in a single clock cycle. | 08-01-2013 |
20130194122 | ANALOG TO DIGITAL CONVERTER WITH LEAKAGE CURRENT CORRECTION CIRCUIT - An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch with a shape factor substantially similar to that of the reset switch. An operational amplifier replicates the voltage of the comparator sense input node to the drain of the dummy transistor to create the same operating point as the reset switch. The resulting leakage current is then repeated and fed back to the node to cancel the offending leakage current. | 08-01-2013 |
20130194123 | Method and Apparatus for Clockless Conversion of Voltage Value to Digital Word - Method and apparatus for mapping the converted voltage value by electric charge value proportional to the converted voltage value and in accumulation of charge in the sampling capacitor until the voltage on this capacitor is equal to the converted voltage. Furthermore, realization of the process of that electric charge redistribution in the array of redistribution by changes of states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. As soon as accumulation of electric charge in the sampling capacitor is terminated, electric charge is accumulated in the additional sampling capacitor then the process of that electric charge redistribution is realized and relevant values are assigned to bits of the digital word. When a trigger signal is detected, next cycle begins and electric charge is accumulated in the sampling capacitor. | 08-01-2013 |
20130194124 | METHOD AND APPARATUS FOR CLOCKLESS CONVERSION OF INSTANTANEOUS VOLTAGE VALUE TO DIGITAL WORD - Method consists in accumulation of electric charge in the sampling capacitor (C | 08-01-2013 |
20130207826 | METHOD AND APPARATUS FOR CLOCKLESS CONVERSION OF TIME INTERVAL TO DIGITAL WORD - Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is aaccumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again. | 08-15-2013 |
20130207827 | CHARGE SHARING ANALOG COMPUTATION CIRCUITRY AND APPLICATIONS - In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters. | 08-15-2013 |
20130214960 | METHOD AND APPARATUS FOR CLOCKLESS CONVERSION OF PORTION OF ELECTRIC CHARGE TO DIGITAL WORD - Method and apparatus for accumulation of electric charge delivered to the charge input (InQ) in the sampling capacitor (C | 08-22-2013 |
20130328709 | AD CONVERTER APPARATUS, AD CONVERTER CIRCUIT, AND AD CONVERSION METHOD - An analogue-digital converter apparatus includes a plurality of AD converters connected in series, each AD converter to convert an analog signal received by a first AD converter, at least one of the AD converters including: a residual signal generator that generates a first residual signal, the first residual signal being a difference between the analog signal or one of two residual signals amplified and output by a preceding AD converter and a first reference signal, and a second residual signal, the second residual signal being a difference between the analog signal or one of the two residual signals and a second reference signal; and an amplifier that amplifies and outputs the first residual signal to a subsequent AD converter at a first timing and amplifies and outputs the second residual signal to the subsequent AD converter at a second timing. | 12-12-2013 |
20140002291 | ANALOG TO DIGITAL CONVERSION ARCHITECTURE AND METHOD WITH INPUT AND REFERENCE VOLTAGE SCALING | 01-02-2014 |
20140035771 | PREDICTIVE SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERSION DEVICE AND METHOD - A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to 1/2 of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits. | 02-06-2014 |
20140035772 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER USING CAPACITOR ARRAY WITH SUB-CAPACITORS CONFIGURED BY CAPACITOR DISASSEMBLING AND RELATED METHOD THEREOF - A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2 | 02-06-2014 |
20140062752 | ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD USING THE SAME - An analog-to-digital converter includes a comparison unit that outputs a result obtained by comparing a voltage of an input node with a comparison voltage; 1 | 03-06-2014 |
20140070976 | ANALOG TO DIGITAL CONVERTER INCLUDING A PRE-CHARGE CIRCUIT - An analog to digital converter comprising at least one sampling capacitor connected to a sample node, and a pre-charge circuit arranged to cause the voltage on the sample node to substantially match the input voltage prior to the analog to digital converter entering an acquire mode in which the sample node is connected to the input node by a sample switch. | 03-13-2014 |
20140077986 | Segmented Column-Parallel Analog-to-Digital Converter - A successive approximation A/D converter which includes a sub ranging classifier that receives an input signal and classifies said input signal according to plural different highest resolution bits, to determine a range of the input signal, and creating a set of most significant bits based on said range, said subranging classifier also setting and determining an offset based on said range, and a successive approximation A/D converted that converting lowest resolution parts of the input signal as adjusted by the offset. | 03-20-2014 |
20140091960 | METHODS AND ARRANGEMENTS FOR HIGH-SPEED ANALOG-TO-DIGITAL CONVERSION - Logic such as hardware and/or code for high-speed analog-to-digital conversion of a signal. Logic may receive an analog signal as an input to a sampling receiver. The sampling receiver may implement a successive approximation register (SAR), analog-to-digital converter (ADC) to produce the digital output. Logic may re-task a comparator of the SAR ADC during a sampling mode to generate a digital comparator output that represents a comparison of a voltage of the charge on a capacitance of the DAC against a threshold reference voltage. The digital comparator output may be applied to the input of automatic gain control (AGC) logic. The AGC logic may receive the digital comparator signal which is representative of one sample of a multiple sample, sample cycle, allowing the AGC logic to generate a gain control signal that is responsive to both total composite average and peak amplitudes. | 04-03-2014 |
20140132438 | Circuits and Methods for Implementing a Residue Amplifier - Circuits and methods for implementing a residue amplifier are provided. In some embodiments, circuits for implementing a residue amplifier are provided, the circuits comprising: a first capacitor configured to be charged to an input voltage level and that discharges from the input voltage level to a reference voltage level; a comparator having a first input coupled to the first capacitor, a second input coupled to a reference voltage source, and an output that indicates when the charge on the first capacitor is above the reference voltage level; and a second capacitor configured to be charged to an output voltage based on the output of the comparator. | 05-15-2014 |
20140168000 | ANTI-ALIASING SAMPLING CIRCUITS AND ANALOG-TO-DIGITAL CONVERTER - A sampling circuit, such as the sampling circuit of a successive approximation analog-to-digital converter (ADC), provides anti-aliasing filtering of a sampled input signal. The circuit samples the input signal using multiple capacitors, wherein each capacitor samples the input signal at a distinct time during a sampling time interval. The circuit combines the samples stored on different capacitors during a conversion time interval, and generates a digital output signal using the combined samples. In one example, a first bit of the output signal is generated using a sample stored on a first capacitor, and second bit of the output signal is generated using a sample stored on a second capacitor. In another example, the circuitry performs finite or infinite impulse response (FIR or IIR) filtering of the input signal, where a filter characteristic is determined by the relative sizes of the capacitors used for sampling. | 06-19-2014 |
20140176359 | REFERENCE CHARGE CANCELLATION FOR ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter (ADC) includes reference charge cancellation features to at least partially offset a voltage distortion on a bypass capacitor of a reference buffer due to a voltage reference hit taken by a switched capacitor bank with which the bypass capacitor is connected. The charge cancellation may be configured in logic to be input signal dependent because different resolved bits or transitions between resolved bits may cause different amounts of voltage reference hits. By adjusting the bypass capacitor in response to each of at least some of the reference hits while resolving a word of bits, the reference voltage signal provided by the bypass capacitor undergoes far less settling, remaining more stable and linear for a more accurate reference voltage. Furthermore, a smaller capacitor may be used for the bypass capacitor, reducing power consumption and area on chip. | 06-26-2014 |
20140203958 | PASSIVE AMPLIFICATION CIRCUIT AND ANALOG-DIGITAL CONVERTOR - A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit. | 07-24-2014 |
20140253359 | BALANCED SIGNAL PROCESSING CIRCUIT AND ANALOG-DIGITAL CONVERSION CIRCUIT - A balanced signal processing circuit includes: a comparator; a first capacitor having a first end connected to a non-inverting input terminal of the comparator; a second capacitor having a first end connected to an inverting input terminal of the comparator; a first switch configured to apply a voltage signal to the first end of the first capacitor; a second switch configured to apply a voltage signal to the first end of the second capacitor; an operation state detection section configured to detect an operation state of the comparator; and an offset voltage correction section configured to apply a predetermined offset voltage to a second end of the first capacitor and a second end of the second capacitor when the operation state detection section detects an abnormal operation state of the comparator. | 09-11-2014 |
20140285370 | SUCCESSIVE APPROXIMATION AD CONVERTER AND NOISE GENERATOR - In a successive approximation AD converter, a noise generator outputs the output of a ΔΣ modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed. | 09-25-2014 |
20140320330 | SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER FOR PROGRAMMABLY AMPLIFYING AMPLITUDE OF INPUT SIGNAL AND METHOD THEREOF - Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation. | 10-30-2014 |
20140333465 | Clocked Reference Buffer in a Successive Approximation Analog-to-Digital Converter - A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor. | 11-13-2014 |
20150054668 | Switched Capacitance Converter - A system includes a first capacitor group to facilitate determination of a first bit, and a second capacitor group to facilitate determination of a second bit in combination with the first capacitor group. The system further includes a delayed clock switch to engage the second capacitor group after determination of the first bit. | 02-26-2015 |
20150061913 | Dual-Path Comparator and Method - A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value. | 03-05-2015 |
20150109161 | ISOLATED BOOTSTRAPPED SWITCH - A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump. | 04-23-2015 |
20160056831 | ENHANCED RESOLUTION SUCCESSIVE-APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD - An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M. | 02-25-2016 |
20160065229 | HIGH-SPEED COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER - A comparator for an analog-to-digital converter is provided. The comparator includes a differential amplifier unit that receives a sampling signal and provides an output signal, based on a voltage provided by the sampling signal. The differential amplifier unit includes an input stage that receives the sampling signal and integrates a current on the integration nodes based on potentials of the sampling signal. The comparator includes a sense amplifier coupled with the integration nodes that detects a potential difference and amplifies the potential difference to generate the output signal. The comparator includes a charge injection circuit ( | 03-03-2016 |
20160099721 | Analog-Digital Conversion System and Method for Controlling the Same - An analog-digital conversion system includes an analog-digital converter; and a preamplifier circuit which is provided in the previous stage of the analog-digital converter and differentially amplifies an input analog signal. In the preamplifier circuit, an offset voltage and/or a noise occurs and/or is mixed. The preamplifier circuit outputs two types of analog amplified differential signals where a phase is inverted only with respect to the offset voltage and/or the noise. The analog-digital converter has an averaging circuit which averages the two types of analog amplified differential signals for each clock cycle of sampling preceding an analog-digital conversion and outputs a digital signal based on the differential signal averaged by the averaging circuit. | 04-07-2016 |
20160112057 | SENSOR DEVICE INCLUDING HIGH-RESOLUTION ANALOG TO DIGITAL CONVERTER - Provided is a sensor device including: a sensor unit converting a voltage of a periodically switched capacitor into a pulse signal by referring to a clock signal to provide the pulse signal as a first sensing signal; and a high-resolution analog to digital converter (ADC) amplifying a period of the first sensing signal 2 | 04-21-2016 |
20160134300 | SAR ADC AND METHOD THEREOF - A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase. | 05-12-2016 |