| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341145000 | Coarse and fine conversions | 47 |
| 20080198054 | SYSTEM FOR DISPLAYING IMAGE AND DIGITAL-TO-ANALOG CONVERTING METHOD - A digital to analog converter is provided comprising a charge sharing circuit, a discharging circuit and a voltage boosting circuit. The charge sharing circuit sequentially receives first to (N-1)th bits of serial digital signals. The charge sharing circuit shares and stores charges between a first capacitor and a second capacitor according to a charging voltage, a ground voltage, a first clock signal and serial data signals. The discharging circuit discharges the charge sharing circuit according to a reset signal. After the voltage boosting circuit receive the (N-1)th digital signal, the charge boosting circuit whether to boost a first terminal and a second terminal of the second capacitor or not based on an Nth digital signal. After the voltage boosting circuit receives the Nth serial digital signal, the charge sharing circuit outputs an analog signal from the second terminal of the second capacitor. | 08-21-2008 |
| 20080218394 | LOGICAL CURRENT DIVISION MULTIPLEXING FOR ENCODING MULTIPLE DIGITAL SIGNALS - A method and a system are disclosed for transmitting an N-bit digital signal at a source. The N-bit digital signal representing a binary value is used to modulate an electrical current by using N discrete voltages representing each bit. The N discrete voltages are coupled to N corresponding switches to control the switches. The switches conduct a corresponding electrical current if the value of the corresponding discrete voltage is the binary value of 1. The currents from each of the closed switches are summed to form a current-encoded data signal in a single physical conductor representing the original N-bit digital signal. The current-encoded data signal is transmitted through the single physical conductor to a current decoder for decoding the current-encoded data signal and extracting the original N-bit digital signal at a destination. | 09-11-2008 |
| 20080303704 | Low-Power Inverted Ladder Digital-to-Analog Converter - An inverted ladder circuit for a Digital to Analog Converter (DAC) having an input binary word representing an input value and an output current corresponding to a converted analog value. The inverted ladder circuit includes at least two fine resistor ladders, including at least an upper fine resistor ladder and a lower fine resistor ladder. The inverted ladder circuit also includes a coarse resistor ladder having a corresponding plurality of coarse ladder resistors, wherein the coarse resistor ladder slides upon the at least two fine resistor ladders. The inverted ladder circuit also includes a plurality of upper fine switches and a plurality of lower fine switches, wherein the switches operate in parallel according to the lower five bits of the input binary word. The plurality of fine ladder resistors are matched with the plurality of coarse ladder resistors to obtain current proportional to the input binary word. The output resistance and parasitic capacitance are reduced. | 12-11-2008 |
| 20080309538 | DIGITAL/ANALOG CONVERTING DRIVER AND METHOD - A digital/analog converting driver and a digital/analog converting method, in which the digital/analog converting driver converts digital data having M+N (M and N are integers) bits into an analog voltage and includes a first converting unit, a second converting unit, and an analog voltage outputting unit. The first converting unit converts successive M bits of the digital data into a first voltage. The second converting unit converts successive N bits of the digital data into a second voltage. The analog voltage outputting unit adds the first voltage and the second voltage and outputs the added voltage as the analog voltage. The output range of the first voltage is different from that of the second voltage. | 12-18-2008 |
| 20080316078 | D/A CONVERTER CIRCUIT - A multi-bit D/A converter circuit that prevents a bit inversion and requires a reduced layout area is offered. A first switching circuit is provided in order to select a pair of analog voltages generated across one of resistors in a first resistor string. The selected pair of analog voltages is provided as reference voltages to a second resistor string. A second switching circuit is provided in order to select a pair of analog voltages generated across one of the resistors in the second resistor string. The selected pair of analog voltages is provided as reference voltages to a third resistor string. A third switching circuit is provided in order to select one of analog voltages generated in the third resistor string. | 12-25-2008 |
| 20090002212 | Digital-to-Analogue Converter System with Increased Performance - The invention relates to an N-bit digital-to-analogue converter (DAC) system, comprising—a DAC unit comprising an N-bit master DAC and a slave DAC, yielding a master DAC unit output signal and a slave DAC unit output signal, respectively, said N-bit master DAC having an output step size,—an adder unit combining the master DAC unit output signal and the slave DAC unit output signal, and—a means for storing correction values for at least the master DAC, said correction values being used by the slave DAC, whereby the DAC system is arranged for master DAC output corrections with a size in absolute value higher than half of the output step size. | 01-01-2009 |
| 20090073015 | System for displaying images - A system for displaying images is provided. A capacitor type digital-to-analog converter is coupled between a first node and a second node and generates a first analog signal according to a digital signal with N bit data. An analogue buffer is coupled between the second node and a third node and generates a second analog signal according to the first analog signal and a bias voltage. A first switch is coupled between a predetermined voltage and the second node. A second switch is coupled between the first node and the third node. A third switch is coupled between the third node and an analog output signal. The second switch is turned on and the third switch is turned off when the first switch is turned on, and the first and second switches are turned off when the third switch is turned on. | 03-19-2009 |
| 20090085787 | VOLTAGE RANDOM ACCESS MEMORY (VRAM) - An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells. | 04-02-2009 |
| 20090140901 | RISA CONTROLLER FOR AN RF INTEGRATED CIRCUIT (RFIC) HAVING IMPROVED EXECUTION SPEED - An RFIC controller configured for executing multiple tasks. A serial interface is included having a serial bus for receiving a data stream having control bits and data bits. One or more registers are coupled to the serial bus for storing the control bits and data bits as they are received. Control circuitry is also included. The data stream is formatted such that the control bits are received before the data bits, the control bits specifying an operation. The control circuitry is configured to examine the control bits as they are received to determine the operation specified by the control bits before the data bits are received. A task corresponding to the operation specified by the control bits is then initiated before the data bits are received. | 06-04-2009 |
| 20090140902 | Digital-Analog Converter and Camera Module Having the Same - Disclosed are a digital-analog converter and a camera module having the same. The digital-analog converter includes a plurality of decoders for receiving bits of a digital input signal by dividing the bits in a predetermined bit unit except for lower bits of the digital input signal, and decoding the bits into thermometer code signals, a delay unit for delaying output of the lower bits of the digital input signal, a latch unit for synchronizing output signals of the decoders with an output signal of the delay unit, and a current source for converting a digital signal output from the latch unit into an analog signal. | 06-04-2009 |
| 20090167583 | INTERPOLATION DIGITAL-TO-ANALOG CONVERTER - A digital-to-analog converter (DAC) includes coarse interpolation DACs configured to produce a current range based on an input digital signal, and fine interpolation DACs configured to produce an output current that is based on an input digital signal and that is within the current range produced by the coarse interpolation DACs. | 07-02-2009 |
| 20090179785 | Read and Write Interface Communications Protocol for Digital-to-Analog Signal Converter with Non-Volatile Memory - A mixed signal integrated circuit device, e.g., digital-to-analog converter (DAC), has a serial interface communication protocol that accesses volatile and/or non-volatile memory and allows a preprogrammed output voltage whenever the mixed signal device is powered-up. However, unlike conventional DACs, DACs with non-volatile memory may need special interface communication protocols for effective operation of the DAC and communications between a system master controller unit (MCU). Interface communications protocols that do not violate standard serial bus communications protocols are provided for communicating between the volatile and non-volatile memories of the DAC so that the MCU may access the DAC's memories (non-volatile and/or volatile memories). The mixed signal integrated circuit device has a user programmable address. | 07-16-2009 |
| 20090201187 | DIGITAL-TO-ANALOG CONVERTER, ANALOG-TO-DIGITAL CONVERTER, AND SEMICONDUCTOR DEVICE - A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained. | 08-13-2009 |
| 20090309776 | D/A converter and reference voltage circuit including same - A variable resistor is connected to each terminal of (2̂n)−1 resistors R connected in series. The variable resistors have resistances RH and RL determined according to a digital signal containing m lower bits LoB. | 12-17-2009 |
| 20100045502 | CURRENT OUTPUT TYPE DIGITAL-ANALOG CONVERSION CIRCUIT, AND GRAPHIC DISPLAY DEVICE - A current output type digital-analog conversion circuit which outputs a current signal includes a decoder for decoding higher-order bits of input digital data, a plurality of binary current generators, and a current adder. Each of the binary current generators includes a device for outputting a binary current which increases linearly as binary values according to lower-order bits of the input digital data, and a device for outputting a predetermined all-ON current. Either the device for outputting the binary current or the element for outputting the all-ON current of the binary current generator is selected according to a decode signal output by the decoder. The current adder adds up and outputs the binary currents and the all-ON currents output by the plurality of binary current generators. | 02-25-2010 |
| 20100079325 | DATA CONVERSION CIRCUITRY AND METHOD THEREFOR - A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided. | 04-01-2010 |
| 20100141497 | Decoder Architecture with Sub-Thermometer Codes for DACs - A digital-to-analog converter (DAC) for converting a digital signal to an analog signal includes a first thermometer decoder and a second thermometer decoder. The first thermometer decoder is configured to decode most-significant bits (MSBs) of the digital signal to generate a first thermometer code. The second thermometer decoder is configured to decode middle bits of the digital signal to generate a second thermometer code. The DAC further includes a plurality of macro cells with each controlled by one bit of the first thermometer code. The plurality of macro cells is configured to provide a first analog signal according to the first thermometer code. The DAC further includes a macro cell configured to provide a second analog signal according to the second thermometer code. The macro cell is further configured to provide a third analog signal according to least-significant bits (LSBs) of the digital signal. | 06-10-2010 |
| 20100164777 | DIGITAL-TO-ANALOG CONVERTER - A digital-to-analog converter is disclosed. The digital-to-analog converter includes a decoder that receives a plurality of digital input signals to output a plurality of thermometer decode signals, a current supply part including a plurality of current sources, each of which operates in one of a sleeping mode and an operating mode under the control of the thermometer decode signals, and a switching part including a plurality of switching units, each of which operates in one of a sleeping mode and an operating mode under the control of the thermometer decode signals. The current supply part selectively outputs a plurality of switching power signals. The switching part outputs an analog signal under the control of the thermometer decode signals. | 07-01-2010 |
| 20100182181 | A-TO-D CONVERTER - A successive approximation type A-to-D converter includes a cyclic D-to-A converter ( | 07-22-2010 |
| 20100302085 | Field Device Having an Analog Output - A field device having an analog output, i.e., a measuring transducer, for process instrumentation having a 4-20 mA interface as the analog output. For digital-to-analog conversion, a digital value is split into a digital coarse portion and a digital fine portion. Depending on the digital coarse portion, a first analog signal is generated using a pulse width modulator having a downstream mounted low path filter and a signal above the analog output signal, and a second output signal using a pulse width modulator also having a downstream mounted low path filter with a signal below the analog output signal. The analog signals are supplied to a third pulse width modulator controlled with the digital fine portion, where a low-pass filter (TP | 12-02-2010 |
| 20110006939 | D/A converter - A resistor string type D/A converter in accordance with an exemplary aspect of the present invention includes a resistor string, switches, a higher-order decoder, a lower-order decoder, and a conversion unit. The resistor string generates a plurality of analog voltages by dividing a voltage between a first reference voltage and a second reference voltage. Each of the switches is provided for a respective one of a plurality of voltage drawing points. The higher-order decoder generates a higher-order control signal according to the value of higher bits of an input digital signal. The lower-order decoder generates a lower-order control signal corresponding to the value of lower bits of the input digital signal. The conversion unit outputs a voltage between a pair of the analog voltage values obtained through a pair of switches based on the lower-order control signal. | 01-13-2011 |
| 20110090106 | DIGITAL-TO-ANALOG CONVERTER WITH MULTI-SEGMENTED CONVERSION - A 12-bit DAC includes a resistor string, three 16-to-1 selectors and an adder. The 12-bit DAC receives a 12-bit digital input data and provides a corresponding analog output voltage with 3-segmented conversion. The resistor string includes a plurality of voltage-dividing units for providing a plurality of reference voltages corresponding to each segment of conversion. After receiving the plurality of reference voltages generated by the resistor string, the three 16-to-1 selectors output 3 reference voltages corresponding to the three segments of conversion according to the 4 most significant bits, 4 least significant bits and the other 4 bits in the 12-bit digital input data, respectively. The adder can then generate the corresponding output analog voltage by summing the 3 reference voltages. | 04-21-2011 |
| 20110102226 | DIGITAL-TO-ANALOGUE CONVERTER - An N-bit DAC ( | 05-05-2011 |
| 20110140943 | Digital-analog converter - In order to reduce a current mismatch by laying-out the bias circuit of current cells adjacent to each other in a common current centroid manner or connecting the output lines of the current cells in a tournament manner, there is provided a digital-analog converter in which a plurality of current cells are two dimensionally and symmetrically disposed according to a previously determined order, the digital-analog converter including: a first current cell group including a portion of the plurality of current cells; and a second current cell group including the rest of the plurality of current cells, not included in the first current cell group, the outputs of each current cell of the first current cell group being connected to the outputs of each current cell of the second current cell group in a tournament manner, wherein each of the plurality of current cells includes: a switch circuit switching the output and block of a unit current according to an input signal; and a bias circuit mirroring current supplied according to the switching of the switch circuit and converting the current into the unit current, the bias circuit of two current cells adjacent to each other among the plurality of current cells being laid-out in a common current centroid manner. | 06-16-2011 |
| 20110140944 | DIGITAL-TO-ANALOG CONVERTER - A resistor string digital-to-analog converter includes a high-order resistor string, first high-order switches, a high-order decoder, a low-order decoder, and a conversion unit. The high-order resistor string includes a plurality of voltage acquisition points that are coupled through unit resistors. The high-order decoder generates a first high-order control signal in accordance with a high-order bit value, and operates in accordance with the first high-order control signal to bring into conduction a first high-order switch coupled to a pair of voltage acquisition points adjacent to each other through one or more voltage acquisition points. The low-order decoder generates a low-order control signal for controlling the conversion unit. The conversion unit divides a pair of high-order analog voltages output from a pair of voltage acquisition points. | 06-16-2011 |
| 20110156942 | REDUCED AREA DIGITAL-TO-ANALOG CONVERTER - One embodiment of the invention includes a digital-to-analog converter (DAC) system. A resistive ladder comprises a plurality of resistors having an approximately equal resistance and is arranged in a respective plurality of resistive rungs between first and second ends of the resistive ladder. The first end of the resistive ladder can be coupled to an output and at least a portion of the plurality of resistors between the first end and the second end of the resistive ladder can have a physical size that is descending size-scaled in a direction from the first end of the resistive ladder to the second end of the resistive ladder. A switching circuit is configured to connect each of the plurality of resistive rungs to one of a first voltage and a second voltage based on a binary value of a digital input signal to generate a corresponding analog output voltage at the output. | 06-30-2011 |
| 20110205097 | DIGITAL-TO-ANALOG CONVERTER, ANALOG-TO-DIGITAL CONVERTER, AND SEMICONDUCTOR DEVICE - A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained. | 08-25-2011 |
| 20120026025 | POTENTIOMETER AND METHOD - A potentiometer and a method for adjusting an impedance. In accordance with an embodiment, the potentiometer may be a programmable multistage digital potentiometer that has a first stage comprising a non-shunted impedance, a second stage coupled between a reference terminal and the first stage, and a third stage coupled between the first stage and another reference terminal. In accordance with another embodiment, the potentiometer receives a wiper address and parses it into sections such that one section controls the first stage, a second portion controls portions of the second and third stages, and a third portion controls the other portions of the second and third stages to produce a desired impedance between a common wiper terminal and the reference terminals. | 02-02-2012 |
| 20120139769 | D/A CONVERTER - A resistor string type D/A converter includes a higher-order decoder to which a digital signal is input, a higher-order resistor string in which a plurality of resistors and a plurality of voltage drawing points are alternately connected between a first reference voltage and a second reference voltage, the higher-order resistor string being configured to output a plurality of first voltages, each from a respective one of the plurality of voltage drawing points, a plurality of first higher-order switches connected to the plurality of voltage drawing points in a one-to-one configuration, conductive states of the first higher-order switches being controlled based on the digital signal, and a conversion unit that outputs a second voltage based on the plurality of the first voltages supplied through the plurality of first higher-order switches. The higher-order decoder brings two first higher-order switches into conduction based on the digital signal. | 06-07-2012 |
| 20120146825 | CYCLIC DIGITAL-TO-ANALOG CONVERTER (DAC) WITH CAPACITOR SWAPPING - A cyclic digital-to-analog converter includes a first capacitor and a second capacitor. Switching circuitry is selectively configurable to connect the first and second capacitors is at least two modes of operation, wherein a first mode uses the first capacitor during conversion of a bit as a sampling capacitor and uses the second capacitor during conversion of that bit as a holding capacitor, and wherein a second mode uses the second capacitor during conversion of a bit as a sampling capacitor and uses the first capacitor during conversion of that bit as a holding capacitor. A controller swaps converter operation between the first and second modes based on the bit values of a digital word to be converted. If adjacent bits of the digital word to be converted have different logical values, the converter swaps from the first mode to the second mode (or from the second mode to the first mode). Otherwise, the converted remains in the current first or second mode. | 06-14-2012 |
| 20120146826 | DEVICE AND METHOD FOR CONTROLLING REFERENCE VOLTAGE OF DIGITAL-TO-ANALOG CONVERTER - The present invention relates to device and method for controlling a reference voltage of a digital-to-analog converter for minimizing variation of output voltages among LED driving chips which drive an LED (Light Emitting Diode) backlight. | 06-14-2012 |
| 20120256776 | DIGITAL-TO-ANALOG CONVERTER - A resistor string digital-to-analog converter includes a high-order resistor string, first high-order switches, a high-order decoder, a low-order decoder, and a conversion unit. The high-order resistor string includes a plurality of voltage acquisition points that are coupled through unit resistors. The high-order decoder generates a first high-order control signal in accordance with a high-order bit value, and operates in accordance with the first high-order control signal to bring into conduction a first high-order switch coupled to a pair of voltage acquisition points adjacent to each other through one or more voltage acquisition points. The low-order decoder generates a low-order control signal for controlling the conversion unit. The conversion unit divides a pair of high-order analog voltages output from a pair of voltage acquisition points. | 10-11-2012 |
| 20120262321 | ANALOG TO DIGITAL CONVERTER AND DIGITAL TO ANALOG CONVERTER - To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished. | 10-18-2012 |
| 20140002289 | MULTI-STAGE STRING DAC | 01-02-2014 |
| 20140002290 | ANALOG TO DIGITAL CONVERTER | 01-02-2014 |
| 20140197974 | DIGITAL TO ANALOG CONVERTER AND METHOD FOR CONTROLLING CURRENT SOURCE ARRAY IN DIGITAL TO ANALOG CONVERTER - A digital to analog converter and a method for controlling a current source array in a digital to analog converter relate to the field of electronics technologies, and are used to reduce a system error. The digital to analog converter includes: a decoding module, a switch array, and a current source array, where the decoding module is configured to generate a 2 | 07-17-2014 |
| 20140266834 | DIGITAL-TO-ANALOG CONVERTER COMPRISING SLOW CONVERTER SECTION AND FAST CONVERTER SECTION - A digital-to-analog converter for converting digital values to an analog output signal includes a first converter section and a second converter section operating at different conversion rates. A first analog signal provided by the first converter section and a second analog signal provided by the second converter section are combined to obtain the analog output signal. The concept may be used in fields of DAC applications where the sample rate is much higher than the signal bandwidth. The limited signal bandwidth means that the maximum change between two neighboring samples is a small fraction of the whole DAC range. The first converter section may cover a large range of values, whereas for the second converter section a relatively small range of values may be sufficient. | 09-18-2014 |
| 20140266835 | DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACS), AND RELATED CIRCUITS, SYSTEMS, AND METHODS - Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time. | 09-18-2014 |
| 20140266836 | POLARITY COMPENSATING DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACs), AND RELATED CIRCUITS, SYSTEMS, AND METHODS - Polarity compensating dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a secondary voltage divider of a dual-string DAC includes a switch logic unit. The switch logic unit is configured to compensate for polarity changes in the dual-string DAC to maintain monotonicity. Monotonicity means an output voltage of a DAC either increases or stays constant for monotonically increasing functions or either decreases or stays constant for monotonically decreasing functions given an incremental change in a DAC input code. The switch logic unit is configured to compensate for polarity changes in the input voltage from the primary voltage divider to the secondary resistor string. The switch logic unit is configured to select a secondary switch among the plurality of secondary switches in a secondary voltage divider, to divide an input voltage based on a polarity indicator and a DAC input code, to maintain monotonicity. | 09-18-2014 |
| 20140266837 | REDUNDANT DELAY DIGITAL-TO-TIME CONVERTER - Representative implementations of devices and techniques provide a time delay based on an input value. A digital delay may be generated based on a coarse delay and a fine delay. The coarse delay may be selected based on the input value. The fine delay may be selected from an overlapping set of fine delay intervals, based on the selected coarse delay. In some implementations, a control component may be used to select the fine delay when more than one fine delay interval is indicated. | 09-18-2014 |
| 20140266838 | DIGITAL TO ANALOG CONVERTER WITH AN INTRA-STRING SWITCHING NETWORK - A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the multi-string DAC is configured to use the voltage change at terminals of a first string separately to the voltage drop across a first switching network that couples the first and second strings to provide an analog output in response to a digital input to the DAC. | 09-18-2014 |
| 20140313066 | MULTIPLE STRING DIGITAL TO ANALOG CONVERTER - A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the DAC comprises a first and second switching network, the second switching network providing multiple switched paths which compensate for impedance effects of the second string and provides multiple state changes at the output node of the DAC. | 10-23-2014 |
| 20140347202 | DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACs), AND RELATED CIRCUITS, SYSTEMS, AND METHODS - Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time. | 11-27-2014 |
| 20150048961 | HIGH OUTPUT POWER DIGITAL-TO-ANALOG CONVERTER SYSTEM - The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more). | 02-19-2015 |
| 20160065234 | MONOTONIC SEGMENTED DIGITAL TO ANALOG CONVERTER - In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word. | 03-03-2016 |
| 20160182079 | DAC WITH SUB-DACS AND RELATED METHODS | 06-23-2016 |
| 20160182080 | HIGH-SPEED, LOW-POWER RECONFIGURABLE VOLTAGE-MODE DAC-DRIVER | 06-23-2016 |
