| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341141000 | Multiplex | 52 |
| 20080204289 | Signal interface circuit - Interface unit for voltage input signals comprising two or more input channels. The input signals of these two or more input channels are connected alternately by an analog multiplexer to an analog-to-digital converter. The A/D converter comprises an integrated sigma-delta modulator circuit which generates a digitized 1-bit signal representing the input signal voltage level for a control unit irrespective of whether the input channel signal is digital or analog. By means of the invention all input voltage channels are made similar such that the input channels of the interface unit can receive an analog or digital signal irrespective of each other. | 08-28-2008 |
| 20080224907 | CIRCUIT FOR PROGRAMMING SAMPLING TIME IN A MULTICHANNEL ANALOG-TO-DIGITAL CONVERTER - The sampling time in a multichannel analog-to-digital converter is programmed with a circuit comprising a memory register with memory locations, which can be respectively coupled to the channels of the converter. The memory locations of the register are able to store a signal identifying a sampling-time value selected for each individual channel of the converter. The circuit likewise comprises a converter module coupled to the memory register for converting the signal identifying the sampling-time value into a corresponding signal for driving the respective channel of the converter for a sampling time corresponding to the sampling time selected. The circuit can be actuated in a synchronized way with the converter so as to vary selectively the sampling time applied to the channels of the converter in the course of operation. | 09-18-2008 |
| 20080238745 | METHODS AND APPARATUS FOR MULTIPLEXED SIGNAL SOURCES USING AN ANALOG-TO-DIGITAL CONVERTER - A multiplexing circuit uses parallel-configured pairs of resistors and signal sources in a voltage divider network in such a way that a single analog-to-digital input can be used to specify the state of more than one signal source. One circuit includes a microprocessor having an analog-to-digital (ADC) input; a memory communicatively coupled to the microprocessor; and a voltage divider network having an output coupled to the ADC input, wherein the network includes a plurality of resistors paired with a plurality of respective signal sources, and wherein the output is unique for each combination of states of the signal sources in accordance with a known relation that is stored in the memory. The signal sources are selected from two categories of sources: continuous sources and discrete sources, where discrete sources may be binary discrete or random discrete. In one embodiment, the first signal source is either a continuous source or a random discrete source, and the second signal is a binary discrete source. | 10-02-2008 |
| 20080278359 | Analog-to-Digital Converter Offset and Gain Calibration Using Internal Voltage References - A mixed signal device having an analog-to-digital converter (ADC) with offset and gain calibration using internal voltage references whereby the digital processor calibrates out offset and gain errors in the analog-to-digital converter by adjusting the analog input amplifier gain and offset or with software compensating the digital representations of the voltages measured. Two different known voltage values are used in determining the offset and gain adjustments needed to calibrate the ADC against the two know voltage values. The mixed signal device may further comprise a Bandgap voltage reference having an accurate known voltage value. Wherein the Bandgap voltage reference may be used for further offset and gain calibration of the ADC to produce substantially absolute voltage values. | 11-13-2008 |
| 20080297384 | Analog to Digital Converter Unit - The present invention is a programmable Analog to Digital Converter (ADC) unit ( | 12-04-2008 |
| 20080303702 | A/D converter - An A/D converter capable of generating an interrupt for requesting a control circuit to read the results of A/D conversion, in desired timing. Analog signals input from channels selected by a channel-selecting section are input to an A/D conversion section, and are sequentially A/D-converted. The results of A/D conversion are sequentially stored in different stages of a FIFO. A stage number-counting section counts the number of the stages of the FIFO where the results of A/D conversion are stored. An interrupt signal-delivering section outputs an interrupt signal for requesting a CPU to read the results of A/D conversion when the number of stages counted by the stage number-counting section is equal to an interrupt-generating stage number set by an interrupt-generating stage number-setting section. | 12-11-2008 |
| 20090015452 | Method and Device for Analong Digital Conversion of a Complex Signal - In order to convert a complex analog signal into a complex digital signal in an analog-digital conversion device having two channels, I and Q respectively, in quadrature, each comprising an input and an associated output, each output being fed back onto said associated input so as to form a first and a second feedback loops each comprising a digital-analog converter, the device comprising a complex filter with a first stage and a last stage, after sampling ( | 01-15-2009 |
| 20090058702 | A/D CONVERSION APPARATUS - An A/D conversion apparatus performs motor current detection in an A/D conversion period corresponding to two phases out of three phases of a sinusoidal drive motor, using reduced register resources while minimizing the number of A/D converters. The A/D conversion apparatus includes: a selection unit selecting one of a plurality of input channels; an A/D converter converting an analog signal from the selected input channel to a digital signal; a start register holding a start channel number of sequential conversion; an end register holding an end channel number of the sequential conversion; a prohibition information holding unit holding prohibition information indicating an input channel to be excluded from the sequential conversion; and a control unit causing the selection unit to select, in channel number order, input channels corresponding to channel numbers from the start channel number to the end channel number except the input channel indicated by the prohibition information. | 03-05-2009 |
| 20090085784 | Integrated Circuit Comprising a Plurality of Digital-to-Analog Converters, Sigma-Delta Modulator Circuit, and Method of Calibrating a Plurality of Multibit Digital-to-Analog Converters - In an integrated circuit including a first multibit digital-to-analog converter and a second multibit digital-to-analog converter, a calibration circuit is provided which is shared between the first and second digital-to-analog converters. | 04-02-2009 |
| 20090091483 | FLASH ANALOG TO DIGITAL CONVERTER (ADC) - A flash ADC in which different thresholds are provided to different comparators in different time instances. Such a feature may be advantageously used in digital converters type components since the flash ADC would provide more time for amplifiers to generate amplified residue signals. | 04-09-2009 |
| 20090115650 | SYSTEM AND METHOD FOR WIDEBAND DIRECT SAMPLING AND BEAMFORMING USING COMPLEX ANALOG TO DIGITAL CONVERTER - A system comprising an radio frequency (RF) signal input; a plurality of time-skewed, undersampled analog to digital converters (ADCs); a plurality of complex finite input response (FIR) filters in parallel, wherein each complex FIR filter receives the output beam and/or band provided by the plurality of ADCs and generates a corresponding output beam of a given frequency. | 05-07-2009 |
| 20090115651 | System and method providing channel multiplexing for analog-to-digital conversion - There is provided a demodulator system comprising a first input to receive a first analog signal at a first rate; a second input to receive a second analog signal at the first rate; a MUX coupled to the first input and the second input to receive the first analog signal and the second analog signal, and to multiplex the first analog signal and the second analog signal to generate a multiplexed analog output; an ADC to receive the multiplexed analog output and generate a multiplexed digital output, the ADC operating at a second rate, the second rate substantially equal to the first rate multiplied by a total number of input analog signals; a DEMUX to receive the multiplexed digital output and generate a first digital output having a first bitstream and a second digital output having a second bitstream corresponding to the first analog signal and the second analog signal. | 05-07-2009 |
| 20090135034 | SYSTEM AND METHOD FOR RECEIVING ANALOG AND DIGITAL INPUT - A system and a method are provided for receiving analog and digital audio input via a single audio input connector. The method includes receiving an input signal from a single audio input connector, splitting the received input signal into a first input signal and a second input signal, filtering the first input signal to pass a digital signal, filtering the second input signal to pass an analog signal, digitizing the filtered analog signal, and multiplexing the filtered digital signal and the filtered digitized analog signal. | 05-28-2009 |
| 20090273498 | INTERRUPT BASED MULTIPLEXED CURRENT LIMIT CIRCUIT - A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value. | 11-05-2009 |
| 20090278717 | ANALOGUE/DIGITAL CONVERTER - There are provided in a scanning mode: a conversion sequence setting register ( | 11-12-2009 |
| 20090284401 | CONFIGURATIONS FOR DATA PORTS AT DIGITAL INTERFACE FOR MULTIPLE DATA CONVERTERS - A data converter includes multiple analog to digital converters (ADCs) and uses a reduced number of data ports at the digital interface for transferring signal samples. The bits of the signal samples generated in parallel by the ADCs are multiplexed into fewer data streams than the number of ADCs. The data ports transfer the data streams at a higher data transfer rate than the bit rate of the samples output from the ADCs. Unused data ports are powered down, decreasing power consumption and system complexity. A host device receives the data streams using fewer input data ports and demultiplexes the received data streams to reproduce the signal samples. Efficient data transfer to a data converter including multiple digital to analog converters (DACs), from a source device generating multiple digital signals can also use fewer data ports having higher data transfer rates. | 11-19-2009 |
| 20090303093 | SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods. | 12-10-2009 |
| 20100013687 | METHOD AND APPARATUS FOR CONVERTING SIGNALS - A method of converting a plurality of input signals on first and second converters, such that the first and second converters are both used when the plurality of signals comprises two signals, characterised in that said method comprises:
| 01-21-2010 |
| 20100073211 | HIGH VOLTAGE ISOLATION BY CAPACITIVE COUPLING - The present invention comprises a circuit for transferring N inputs, wherein N is greater than or equal to 2, across a capacitive coupling media comprising a line circuit, a coupling capacitor, and a neutral potential circuit. The line circuit comprises: (1) a data converter for each input, for sampling and converting the N inputs; (2) a multiplexer for combining the outputs of the N data converters and a synchronization signal to generate an unencoded composite bit stream; (3) a data encoder for encoding the composite bit stream. The capacitor couples the encoded composite bit stream to a data decoder. The neutral potential circuit comprises: (1) the data decoder for decoding the coupled composite bit stream, and generating a recovered data stream and a recovered clock; (2) a synchronization recovery, control logic, and de-multiplex function for providing a set of digital outputs that correspond to the inputs to the data converters. | 03-25-2010 |
| 20100103010 | TWO-STEP SUB-RANGING ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR PERFORMING TWO-STEP SUB-RANGING IN AN ANALOG-TO-DIGITAL CONVERTER - A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC. | 04-29-2010 |
| 20100103011 | CONFIGURATIONS FOR DATA PORTS AT DIGITAL INTERFACE FOR MULTIPLE DATA CONVERTERS - A data converter includes multiple analog to digital converters (ADCs) and uses a reduced number of data ports at the digital interface for transferring signal samples. The bits of the signal samples generated in parallel by the ADCs are multiplexed into fewer data streams than the number of ADCs. The data ports transfer the data streams at a higher data transfer rate than the bit rate of the samples output from the ADCs. Unused data ports are powered down, decreasing power consumption and system complexity. A host device receives the data streams using fewer input data ports and demultiplexes the received data streams to reproduce the signal samples. Efficient data transfer to a data converter including multiple digital to analog converters (DACs), from a source device generating multiple digital signals can also use fewer data ports having higher data transfer rates. | 04-29-2010 |
| 20100127907 | READBACK REGISTERS - A method reading bank register values is provided. Register values are stored in a readback bank. The register values are output sequentially from the serial bank. An indicator is received by the serial bank. A determination is then made as to whether the indicator was received by the serial bank prior to completion of the outputting of the register values. If the indicator was received prior to completion of the outputting of the register values, the register values are loaded into the serial bank from the readback bank. | 05-27-2010 |
| 20100164772 | ANALOG INPUT DEVICE - An amplifier for amplifying a pulse-like signal output from a secondary side of an isolating transformer, a capacitor connected to a negative feedback loop across the input and output of the amplifier, and a timing control circuit for controlling an FET into a closed state, then controlling a switch into a closed state, and after that controlling the switch into an open state at timing simultaneously with the FET or earlier than the FET are provided, and when the switch is controlled into the open state, an AD converter converts the output signal of the amplifier to a digital signal. | 07-01-2010 |
| 20100188276 | SYSTEM AND METHOD FOR PROCESSING SIGNALS FROM MULTIPLE INPUT DEVICES - Systems and methods for processing a plurality of input signals are provided. A plurality of selection signals are received. Each of the plurality of selection signals is representative of one of a plurality of input signal characteristics. Each of the input signal characteristics is associated with one of the plurality of input signals. The plurality of input signals are converted into at least one digital waveform. A plurality of signal values may be extracted from the at least one digital waveform based on the plurality of input signal characteristics. An output signal may be generated based on each of the plurality of signal values. | 07-29-2010 |
| 20100238058 | MULTIPLE INPUT ANALOG TO DIGITAL CONVERTER - A multi-input analog to digital converter (“ADC”) to accept and process multiple inputs. The analog multiplexer is integrated with an amplifier chopper circuit to form a high precision, temperature stable, ADC circuit with multiple inputs. | 09-23-2010 |
| 20100245143 | ANALOG-TO-DIGITAL CONVERSION MODULE ADAPTED FOR IRREGULAR SAMPLING SEQUENCES - Apparatus and methods are provided for performing a sampling sequence for a plurality of samples. An analog-to-digital conversion module comprises a sampling module, a register, and a sampling control module coupled to the sampling module and the register. The sampling module is configured to convert analog signals into corresponding digital values in response to sampling trigger signals and the register is configured to maintain scan mode criteria for a plurality of samples. The sampling control module is configured to identify a scan mode criterion for a respective sample of the plurality of samples, automatically generate a sampling trigger signal when the scan mode criterion for the respective sample is equal to a first value, and generate the sampling trigger signal in response to a timing trigger signal when the scan mode criterion for the respective sample is equal to a second value. | 09-30-2010 |
| 20100271244 | A/D Converter - An analog to digital converter includes: a reference circuit adapted to generate reference voltages; differential amplifiers; normal phase circuits each of which samples a normal phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a first input terminal of one of the differential amplifiers when the input is differential and single-ended; and reversed phase circuits each of which samples a reversed phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a second input terminal of one of the differential amplifiers when the input is differential and which samples a ground level as a reference voltage of the reference circuit and supplies the reference voltage and comparison voltage to the second input terminal of the differential amplifier when the input is single-ended. | 10-28-2010 |
| 20100309035 | METHOD AND APPARATUS TO IMPROVE REFERENCE VOLTAGE ACCURACY - A method and apparatus for converting an analog input voltage signal to a discrete signal, the method including generating at least one reference voltage and at least one secondary voltage. The method further including selecting at least one voltage between the at least one reference voltage and the at least one secondary voltage and generating at least one intermediate voltage based on the at least one voltage and at least one digital code. The at least one intermediate voltage and the analog input voltage further being used to generate at least one comparison signal and the discrete signal being generated based on the at least one comparison signal and the at least one digital code. | 12-09-2010 |
| 20100328123 | ANALOG-TO-DIGITAL CONVERTER - According to an embodiment, an analog-to-digital converter (ADC) including an ADC unit, a clock-phase control unit, a multiplexer, and a digital-output processing unit is provided. The digital-output processing unit inputs digital outputs of the ADC unit to either an averaging circuit or the multiplexer depending on the specified conversion speed and the specified conversion accuracy, or inputs the digital outputs of the ADC unit to the averaging circuit and the multiplexer in this order, and outputs ADC digital signals with the specified conversion speed and the specified conversion accuracy. | 12-30-2010 |
| 20110043397 | SYSTEM AND METHOD FOR REDUCING PATTERN NOISE IN ANALOG SYSTEM PROCESSING - An analog-to-digital conversion system includes an analog-to-digital converter (ADC), a plurality of receivers, each for capturing input analog signals, a multiplexer having inputs coupled to each of the receivers and an output coupled to the ADC, the multiplexer establishing a signal path between a selected one of the inputs and the output in response to an index signal, and a mux controller to supply a random sequence of index signals to the multiplexer. | 02-24-2011 |
| 20110084863 | PIPELINE TIME-TO-DIGITAL CONVERTER - A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell. | 04-14-2011 |
| 20110102221 | Transparent Multiplexing of Analog-To-Digital Converters - A method and apparatus for sampling and converting analog input values. In response to an event, a value is transmitted from an input of a multiplexer to the output of the multiplexer. The output of the multiplexer is coupled to an input of an analog-to-digital converter (ADC). In response to a second event, a value is transmitted from the input of the multiplexer to a second ADC. | 05-05-2011 |
| 20110169673 | TIME-TO-DIGITAL CONVERTER WITH BUILT-IN SELF TEST - Apparatuses and methods related to time-to-digital converters (TDCs) are herein described. Generally, a time-to-digital converter is a device which measures a time period or time interval and outputs a digital value representing the measured time period. In an implementation, an apparatus is provided comprising a time-to-digital converter circuit, which further comprises a built-in self test (BIST). The built-in self test may be implemented using one or more oscillators coupled to the time-to-digital converter via one or more multiplexer devices. | 07-14-2011 |
| 20110210880 | ANALOG-TO-DIGITAL CONVERTER - Various implementations relating to analog-to-digital converters are provided. A comparator of such a circuit is used for converting different analog input signals, while analog-to-digital conversion circuitry for these conversions is implemented at least partially separately. In other implementations, a comparator is used both for analog-to-digital conversion and for comparing an input signal to a constant or non-constant value. | 09-01-2011 |
| 20120062404 | Novel Noise Injection Technique - A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality. | 03-15-2012 |
| 20120105261 | ADC CHANNEL SELECTION AND CONVERSION - A microcontroller includes a microcontroller core and an analog-to-digital converter (“ADC”) coupled to said microcontroller core. The ADC has multiple input channel multiplexers that are configured to receive multiple analog input channels. The microcontroller further includes a selection register and a data structure. The data structure comprises a plurality of associated field sets. Each bit position in the selection register indexes to one of the associated field sets in the data structure, and the value contained in each such bit position indicates whether or not to select the corresponding associated field set for selection of an analog input channel. Each associated field set comprises one or more values collectively specifying an analog input channel to select for conversion to digital form. | 05-03-2012 |
| 20120112940 | ANALOG TO DIGITAL CONVERTER - An analog to digital converter (ADC) includes a clock control unit supplying a predetermined clock signal corresponding to luminance among a plurality of clock signals having different frequencies; and a signal conversion unit comparing a ramp signal with an inputted pixel signal to generate a comparison result signal. The ADC performs counting corresponding to the predetermined clock signal supplied by the clock control unit and stores a count value counted at a time of the generating of the comparison result signal. | 05-10-2012 |
| 20120218133 | HIGH SPEED, HIGH VOLTAGE MULTIPLEXER - A method for digitizing at least a portion of a selected analog input signal of a plurality of analog input signals by using a multiplexer having a plurality of channels is provided. Each channel for the multiplexer is associated with at least one of the analog input signals and is associated with a pair of select signals, and wherein each channel includes a cell having an input terminal, an output terminal, and a boosted NMOS switch. According to the method, a first select signal from each pair of select signals is asserted to decouple the input and output terminals for each cell. A boost capacitor is also charged during the non-sampling or conversion phase while the first select signal from each pair of select signals is asserted. A second select signal that is associated with the selected analog input signal is then asserted so as to couple together the input and output terminals for the cell associated with the selected analog input signal and to provide a voltage stored on the boost capacitor to the associated boosted NMOS switch. The portion of the selected analog input signal is then digitized. | 08-30-2012 |
| 20120299759 | ANALOG TO DIGITAL CONVERSION APPARATUS - An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed. | 11-29-2012 |
| 20120299760 | SEQUENCE ARBITER FOR ANALOG-TO-DIGITAL CONVERSIONS - An analog-to-digital converter device may include an input multiplexer circuit having analog input terminals configured to receive a respective plurality of analog input signals. The input multiplexer circuit may be responsive to a first select input. The device may also include a trigger multiplexer circuit having input terminals configured to receive respective triggering signals. The trigger multiplexer circuit may be responsive to a second select input. Analog-to-digital converter circuitry may be configured to convert the selected analog signal into a digital signal. A sequence arbiter may be coupled to the first and second select inputs and may have input terminals configured to receive a respective plurality of conversion sequence configuration signals. The sequence arbiter may be configured to manage each conversion sequence of the analog-to-digital converter circuitry based upon the relative conversion sequence configuration signal received, and control the conversion sequences. | 11-29-2012 |
| 20130181855 | ANALOG-TO-DIGITAL CONVERTING CIRCUIT AND ANALOG-TO-DIGITAL CONVERTING METHOD - An analog-to-digital converting circuit includes a reference circuit and an analog-to-digital converter (ADC). The reference circuit provides a base voltage, which has one end grounded. The ADC receives an analog input signal and a base voltage signal. The ADC includes a first DC buffer and an ADC core unit. The first DC buffer internally receives an offset voltage signal and a data voltage signal to be digitized, and outputs two converting control signals. The ADC core unit receives the two converting control signals from the first DC buffer and an ADC input range voltage signal, and outputs a digital code. All of the offset voltage signal and the data voltage signal and the ADC input range voltage signal have been added with the base voltage signal. | 07-18-2013 |
| 20130201044 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSING SYSTEM - The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer. | 08-08-2013 |
| 20140055292 | SHARING EMBEDDED ADC RESOURCES ACROSS HARDWARE AND SOFTWARE SAMPLE-CONVERSION QUEUES WITH IMPROVED AVAILABILITY OF THE RESOURCES - An apparatus for sharing embedded analog-to-digital conversion resources across multiple hardware and software sample conversation queues includes an analog front end, a least one FIFO buffer, a plurality of configuration registers and a sequencer. The sequencer admits a higher priority hardware stepping sequence until the higher priority stepping sequence is completed. After completion, the apparatus reverts to completing pending conversions. | 02-27-2014 |
| 20140292551 | SAMPLING DEVICE WITH BUFFER CIRCUIT FOR HIGH-SPEED ADCS - A sampling and interleaving stage device for use in an analog-digital-converter and for providing a sampling output signal and an analog-to-digital-converter. The sampling and interleaving stage device for use in an analog-digital-converter, including: a receiving unit having a clock unit with a plurality of clock-driven switches for receiving an input signal; for each of the plurality of clock-driven switches, a first demultiplexer, for receiving the input signal via a clock-driven switch and for providing a number of first demultiplexer outputs; for a first demultiplexer output, at least one storage element for a stored input potential depending on the input signal; and an output demultiplexer for receiving an indication about the stored input potential and for outputting a corresponding sampling output signal to a respective sampling output. | 10-02-2014 |
| 20140300500 | ANALOG/DIGITAL CONVERTER AND METHOD FOR CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS - The objective of the invention is to provide an A/D converter that exhibits fewer malfunctions due to variations in manufacturing. An A/D converter ( | 10-09-2014 |
| 20150109156 | ANALOG DIGITAL DATA CONVERSION METHOD, ANALOG DIGITAL DATA CONVERTER, AND ANALOG DIGITAL CONVERSION CHIP - The present invention is applicable to the field of communication, and provides an analog digital data conversion method, an analog digital data convertor and an analog digital conversion chip. The method includes: converting multiple groups of analog data to multiple groups of digital data; performing frequency shift on the multiple groups of digital data, wherein the multiple groups of frequency shifted digital data are independently distributed within a first preset bandwidth; filtering the multiple groups of frequency shifted digital data to remove outband information; and distributing without overlap the filtered multiple groups of digital data within a second preset bandwidth. The method substantially reduces pressure of data transmission between the converter and an FPGA or ASIC, and effectively simplifying the design of a multiband receiver. | 04-23-2015 |
| 20150326237 | SPECTRALLY WEIGHTED ANALOG TO DIGITAL CONVERSION - Systems and methods presented herein provide for analog to digital conversion with variable bit resolution. In one embodiment, a system includes a processor and a multiplexer. The processor is operable to receive an analog signal, to detect power spectral densities in the analog signal, to segment the analog signal into at least two frequency bands, to sample each of the frequency bands, and to quantize each of the sampled frequency bands with bit resolutions according to detected power spectral densities of the frequency bands. The multiplexer is operable to multiplex the quantized frequency bands into a data stream. | 11-12-2015 |
| 20150365099 | MULTIPLEXED SIGNAL SAMPLER AND CONDITIONER - A signal convertor includes a first sensor configured to generate a first signal and a second signal and first and second multiplexers configured receive the first and second signals, respectively, and generate samples. The signal convertor also includes an analog-to-digital (A/D) convertor configured to convert the samples and a processor configured to multiply the samples by a sine vector and by a cosine vector and determine a magnitude of the first and second signals based upon the product of the samples and the sine vector and the product of the samples and the cosine vector. A method for converting a signal is also disclosed. | 12-17-2015 |
| 20160020777 | CONFIGURABLE TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A time-interleaved analog-to-digital converter for conversion of L analog input signals to L corresponding digital output signals comprises an array of N (N>L) constituent analog-to-digital converters each having an analog input and a digital output and each adapted to digitize an analog input sample, and a controller adapted to (for each of the L analog input signals indexed by i=1, 2, . . . , L) select a number N | 01-21-2016 |
| 20160036457 | METHOD AND APPARATUS FOR PERFOMRING ANALOG-TO-DIGITAL CONVERSION ON MULITPLE INPUT SIGNALS - A method, computer-readable storage medium, and signal processing apparatus for processing a plurality of input signals. The method includes receiving or generating a first intermediate signal and a second intermediate signal. The first and second intermediate signals are summed and the summed signals are output to a signal analog-to-digital converter having a predetermined sampling frequency. | 02-04-2016 |
| 20160134296 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSING SYSTEM - The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer. | 05-12-2016 |
| 20220140834 | MULTIPLEXING DEVICE FOR DIGITAL-TO-ANALOG CONVERSION CIRCUIT AND ANALOG-TO-DIGITAL CONVERSION CIRCUIT IN STORAGE AND CALCULATION INTEGRATED CHIP - A multiplexing device for a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a storage and calculation integrated chip, comprising a digital-to-analog conversion circuit (DAC) module, an analog vector-matrix multiplication operation circuit(AMAC) module, an analog-to-digital conversion circuit(ADC) module, a first many-to-one multiplexer (M1-MUX) module, a second M1-MUX module, a first one-to-many multiplexer (1M-MUX) module, a second 1M-MUX module, and a switching transistor module. At an AMAC input end, each DAC corresponds to a plurality of input ends and is shared with the first 1M-MUX module in a time multiplexing mode by means of the first M1-MUX module; at an AMAC output end, each ADC corresponds to a plurality of output ends, and is shared with the second 1M-MUX module in a time multiplexing mode by means of the second M1-MUX module; the number of DACs and ADCs is reduced, and the chip area is reduced. | 05-05-2022 |
