Class / Patent application number | Description | Number of patent applications / Date published |
341133000 | With particular solid state devices (e.g., Gunn effect device, Josephson device, drift transistor, using solid state active devices as impedances) with other at longer intervals) | 47 |
20080238744 | DIGITAL-TO-ANALOG CONVERTER CELL - A DAC cell comprising: two or more PMOS core devices coupled in series between a power supply and a steering node; a first core transistor coupled between the steering node and a complementary power supply line and controlled by a control signal; and a second core transistor coupled between the steering node and an output of the DAC cell and controlled by a logical inverse of the control signal, wherein the control signal and its logical inverse direct a current from the steering node to either the complementary power supply line or to the output of the DAC cell based on the control signal. | 10-02-2008 |
20080284626 | Analog-digital converter, solid-state image capturing apparatus, and electronic information device - An analog-digital converter is provided. The analog-digital converter includes: a comparing section for comparing an input signal voltage and an analog ramp voltage in which a voltage level gradually increases; and a latch section for storing a digital value of a digital ramp signal, in which a digital value of a voltage level gradually increases in synchronization with the analog ramp voltage when the analog ramp voltage or a voltage corresponding to the analog ramp voltage and the input signal voltage are equal. A voltage in which part or all of a plurality of analog ramp signals are added is used as the analog ramp voltage so that a gain is selectable. | 11-20-2008 |
20090033531 | CURRENT STEERING DIGITAL-ANALOG CONVERTER PARTICULARLY INSENSITIVE TO PACKAGING STRESSES - A current steering digital-analog converter for converting a digital code into an analog signal, the converter including a substrate of semiconductor material, an array of current generators integrated in the substrate, a common summation node and switches controllable on the basis of the digital code for connecting and disconnecting the current generators to and from the common summation node. The current generators are adapted to provide the common summation node with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator of the array of generators. The current generator is divided into a base number of modular current generation elements in parallel to one another at least equal to two. | 02-05-2009 |
20100001890 | HIGH SPEED VOLTAGE FOLLOWING DEVICE FOR ANALOG-TO-DIGITAL CONVERSION SYSTEM - A voltage following device is described, for the driving of a sampling network coupleable to an analog/digital converter, comprising at least one first transistor provided with a first terminal to receive an input signal, and a second terminal to provide an output signal to the sampling network which is representative of the input signal translation of an amount equal to a gate and source voltage of said at least one first transistor. The voltage following device having a driving network of said at least one first transistor to keep said gate and source voltage equal to a shift reference voltage. | 01-07-2010 |
20100026537 | Superconductor Analog-to-Digital Converter - A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an N | 02-04-2010 |
20100066576 | Superconductor Multi-Level Quantizer - A superconductor multi-level quantizer is disclosed, which quantizer includes a number N of Josephson junction (JJ) comparators connected in parallel to a common input node. The quantizer further includes at least one flux bias device. Each flux bias device is capable to adjust the flux threshold for at least one of the JJ comparators. The quantizer is so configured a feedback current from the output is capable to shift the flux threshold for each of the JJ comparators. | 03-18-2010 |
20100117880 | Variable sized aperture window of an analog-to-digital converter - An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a multitude of inverter pairs interconnected in series, a specific permittivity material device, and a sequencer or multiplier. A second enhanced sampling system includes a variable sized aperture window, wherein a width of a sample pulse is narrowed through a variable clock mechanism to produce a faster sampling rate. This variable sized aperture window system can be used by itself, or in combination with any of the presently described multiple ADC distributed sampling systems. | 05-13-2010 |
20100149011 | SUPERCONDUCTING ANALOG-TO-DIGITAL CONVERTER - A superconducting bandpass sigma-delta Analog-to-Digital Converter (ADC) is disclosed. The ADC is characterized as being an N | 06-17-2010 |
20100164770 | MULTI-STAGE COMPARATOR WITH OFFSET CANCELING CAPACITOR ACROSS SECONDARY DIFFERENTIAL INPUTS FOR HIGH-SPEED LOW-GAIN COMPARE AND HIGH-GAIN AUTO-ZEROING - An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period. | 07-01-2010 |
20100245142 | TRI-LEVEL DYNAMIC ELEMENT MATCHER ALLOWING REDUCED REFERENCE LOADING AND DAC ELEMENT REDUCTION - Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements. | 09-30-2010 |
20110057823 | Asynchronous SAR ADC - An asynchronous analog to digital convertor for converting an analog input signal into a digital output is presented. According to an embodiment, the analog to digital convertor comprises a clock input operable to receive an external clock signal having a clock period, a comparator operable to compare the analog input signal to a reference signal, a digital to analog converter operable to generate the reference signal corresponding to a state of a successive approximation register, and a control block connected to the comparator and to the digital to analog converter. The control block is operable to generate and receive a sequence of control signals according to a successive approximation algorithm, to perform a plurality of comparisons, and to update the state of the successive approximation register thereby generating the digital output. | 03-10-2011 |
20120274494 | SUPERCONDUCTING ANALOG-TO-DIGITAL CONVERTER WITH CURRENT AMPLIFIED FEEDBACK - A superconducting bandpass sigma-delta modulator and a method for analog-to-digital signal conversion is disclosed. The superconducting bandpass sigma-delta modulator includes coupled resonators having a desired impedance ratio. A first resonator connects to a comparator, which comparator generates single-flux-quantum pulses. A feedback loop links from the comparator to a second resonator and includes a current amplifier. A digital RF receiver system is also disclosed. This system includes a second order bandpass sigma-delta modulator, which has a desired impedance ratio between resonators and a feedback loop with current amplification. The system further has an antenna configured to receive a GHz frequency radio transmission and to yield an analog signal which is accepted by the sigma-delta modulator. | 11-01-2012 |
341135000 | Current mirror | 9 |
20080291068 | CURRENT OUTPUT CIRCUIT WITH BIAS CONTROL AND METHOD THEREOF - A current output circuit with bias control and a method thereof are provided. The current output circuit includes a current mirror circuit comprising a first transistor and a second transistor having respectively two drains, and a control circuit coupled to the current mirror circuit. The control circuit receives drain voltages of the first transistor and the second transistor, and adjusts a respective gate bias of the first transistor and the second transistor according to a respective drain voltage thereof. | 11-27-2008 |
20090167579 | D/A CONVERSION CIRCUIT - In an mode of this invention, a digital/analog conversion circuit, includes: a digital/analog conversion portion which outputs a first current according to an input digital signal; and a first current mirror circuit which generates a mirror current according to the first current and outputs the mirror current as an analog signal, the digital/analog conversion circuit converting the digital signal into the analog signal, and further including: a second current mirror circuit, which generates a first mirror current according to the first current; and a third current mirror circuit, which is connected to a reference voltage, and to which the first mirror current is input, and which generates a second mirror current equal to the first current, according to the first mirror current, between the digital/analog conversion portion and the second current mirror circuit. | 07-02-2009 |
20090179783 | D/A CONVERSION CIRCUIT, ORGANIC EL DRIVE CIRCUIT AND ORGANIC EL DISPLAY DEVICE - A D/A converter of the current switching type has a first current mirror circuit that D/A converts the upper (n−m) digits in n bit data to be converted and a weighting current circuit block or a second current mirror circuit that D/A converts the lower m digits in the data, by cascade connecting the weighting current circuit block or the second current mirror circuit at the upstream or at the downstream side of an output side transistor other than the output side transistors of the first current mirror circuit. In this manner, current flowing through the output side transistor flows as diverting currents to the weighting current circuit block or the second current mirror circuit corresponding to the digit weights of the lower m digits, and the diverting currents are taken out at the outputs of the D/A conversion circuit as analog converted currents of the lower m digits. | 07-16-2009 |
20100007536 | RAPID RECOVERY CIRCUIT - When a semiconductor circuit, in which a stabilizing capacitor | 01-14-2010 |
20100097253 | LOW POWER LINEAR INTERPOLATION DIGITAL-TO-ANALOG CONVERSION - A resistor network digital-to-analog converter (DAC) subdivides each sampling clock cycle of the DAC into a number of phases. For at least one bit input of the DAC associated with a desired input resistor weight, the input bit value is sampled at each phase. Each of those sampled values is then applied to a respective resistor branch, the parallel set of resistor branches forming the parallel equivalent of the desired input resistor weight for that bit input. Such application may be, for example, via a slew-rate controlled driver, to smooth transient edges in the generated analog output signal. The resulting analog signal experiences reduced reconstruction errors at a higher frequency while consuming less power than a comparable oversampling DAC. Shifting reconstruction errors to higher frequencies relaxes downstream filtering requirements, which simplifies analog signal filtering and allows, for example, the use of current-mode low pass filters. | 04-22-2010 |
20100156685 | SAR ANALOG-TO-DIGITAL CONVERTER HAVING VARIABLE CURRENTS FOR LOW POWER MODE OF OPERATION - A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SARADC. | 06-24-2010 |
20100164771 | EXPONENTIAL DIGITAL TO ANALOG CONVERTER - A system for generating a programmable exponential analog output signal, comprising a digital to analog conversion circuit for converting said digital signal into an analog output signal, the digital to analog conversion circuit having a substantially exponential transfer function defined by a programmable ratio of values of components. Preferably, the conversion circuit is implemented as a current mirror ( | 07-01-2010 |
20100283647 | PROGRAMMABLE DIGITAL-TO-ANALOG CONVERTER - A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes. | 11-11-2010 |
20110210878 | APPARATUSES AND METHODS FOR MULTIPLE-OUTPUT COMPARATORS AND ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter with comparators with multiple, inter-coupled, outputs is provided, which may be also called a Benorion Analog-to-Digital Converter (ADC) or a Benorion Converter. The analog-to-digital converter includes a plurality of comparators operably coupled for receiving an analog input signal and configured for comparing the analog input signal with a plurality of voltage reference signals. Each comparator of the plurality is configured for generating a plurality of comparator outputs comprising a primary comparator output, and at least one additional comparator output selected from the group consisting of positive comparator outputs and negative comparator. The analog-to-digital converter further includes a plurality of composite outputs, each composite output of the plurality comprising a combination of the primary comparator output from a corresponding comparator of the plurality and at least one additional comparator output from at least one additional comparator of the plurality of comparators. Other comparators and methods are provided. | 09-01-2011 |
341136000 | Field effect transistor | 26 |
20080198050 | DELTA-SIGMA MODULATOR AND DA CONVERTER APPARATUS INCLUDING DELTA-SIGMA MODULATOR CHANGING ORDER OF FILTER - In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits. | 08-21-2008 |
20080309530 | Quantizing circuits with variable parameters - Systems, methods, and devices are disclosed, such as a device including a floating-gate transistor, a quantizing circuit coupled to the floating-gate transistor, and a controller configured to vary a voltage of a gate of the floating-gate transistor when reading data from the floating-gate transistor. | 12-18-2008 |
20080309531 | Data Driver and Driving Method of Organic Light Emitting Display Device Using the Same - A data driver capable of generating data signals with desired voltage values. The data driver includes a first digital-analog converter including a plurality of first switches, the first digital-analog converter selecting two reference voltages from among a plurality of reference voltages by turning on two of the first switches corresponding to high level bits of data; and a second digital-analog converter for dividing the two reference voltages into a plurality of voltages and for supplying any one of the two reference voltages and the divided voltages corresponding to low level bits of the data as a data signal to an output terminal, wherein the second digital-analog converter includes a transistor turned on by a bias voltage to compensate for a turn-on resistance of the two of the first switches. | 12-18-2008 |
20090045993 | CURRENT STEERING DAC - A multi-channel current steering DAC (Digital-to-Analog Converter), for example, a 2-channel current steering DAC, includes a plurality of current sources I | 02-19-2009 |
20090051575 | DRIVING APPARATUS FOR DISPLAY - A driving apparatus for a display is provided. The driving apparatus for a display comprises a reference voltage generator, a digital-to-analog converter, and an output unit. The reference voltage generator generates a plurality of reference voltages, and receives a difference value between two adjacent reference voltages and generates a plurality of sub reference voltages. The digital-to-analog converter selects one of the reference voltages and outputs the selected reference voltage as a first analog signal. The digital-to-analog converter selects one of the sub reference voltages and outputs the selected reference voltage as a second analog signal. The output unit processes, by addition or subtraction, the first and second analog signals for output. | 02-26-2009 |
20090051576 | SWITCHING CIRCUITRY - A digital-to-analog converter, comprising: a first field-effect transistor; a second field-effect transistor; and adjusting means for adjusting a bulk voltage applied to at least one of the first and second field-effect transistors so as to tend to equalise respective switching delays of the transistors. | 02-26-2009 |
20090079604 | Dual Gate Oxide Analog Circuit Architecture With Dual Voltage Supplies and Associated Method - An analog circuit architecture is fabricated with dual gate oxides and dual voltage supplies. In the analog circuit architecture, different kinds of devices/transistors with different gate oxide thicknesses are biased by different voltages, such that advantages of each device technology are mixed to enhance total performance of the analog circuit. For example, thin oxide 0.18 um transistors are biased at 1.8V for higher speed and lower power consumption, whereas thick oxide 0.35 um transistors are biased at 3.3V for a wider signal swing range. | 03-26-2009 |
20090128383 | Compensation of nonlinearity of single ended Digital to analog converters - This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit. | 05-21-2009 |
20090207059 | FLEXIBLE ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter ( | 08-20-2009 |
20090256733 | Current control circuit - Provided is a current control circuit. A current control circuit may include a clock sensing unit configured to generate a control signal according to one or more frequencies based on a plurality of clock signals, and a current scaling unit configured to scale a bias current according to the control signal. The current control circuit according to example embodiments may dynamically control a bias current according to one or more frequencies based on a plurality of clock signals so that power consumption of an analog-to-digital converter (ADC) and the semiconductor device including the ADC, which require various operating frequencies, may be improved. | 10-15-2009 |
20090303092 | ANALOG-TO-DIGITAL CONVERSION DEVICES AND ANALOG-TO-DIGITAL CONVERSION STAGES THEREOF - An analog-to-digital (A/D) conversion device is provided and includes a first A/D conversion stage. The A/D conversion stage includes a first pre-amp unit, first and second latch units, and a first conversion unit. The first pre-amp unit amplifies the analog input data and outputs a first amplified data. The first and second latch units are enabled by first and second latch clock signals to latch the first and second amplified data and generate first and second latched data, respectively. The first pre-amp unit is reset between a time point when the first latch unit is enabled and a time point when the second latch unit is enabled. The first conversion unit receives the analog input data, and the first and second latched data and accordingly generates a first analog output data. | 12-10-2009 |
20100007537 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH SHORTENED SOURCE AND DRAIN - A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate and between the doped regions. Accordingly, the layout area could be substantially reduced. | 01-14-2010 |
20110050470 | DIGITAL-TO-ANALOG CONVERTER - A DAC unit, connected to a current supply transistor, includes first control transistors connected in parallel to each other, with each being connected in series to the current supply transistor. The first control transistors drive currents at different current values in response to a bias voltage. The DAC unit also includes second control transistors connected in parallel to each other, with each being connected in series to the current supply transistor. Each second control transistor drives the current having the same current value as one of the first control transistors in response to the single bias voltage. The first and second control transistors driving the currents having the same current value operate in a complementary manner based on part of a digital code. The DAC unit generates an output current by selectively combining at least one of the currents driven by the first control transistors. | 03-03-2011 |
20110210879 | APPARATUSES AND METHODS FOR PHYSICAL LAYOUTS OF ANALOG-TO-DIGITAL CONVERTERS - Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple, inter-coupled, outputs. Such an ADC may be called a Benorion Analog-to-Digital Converter. A method for fabricating an integrated circuit is also provided. The method comprises arranging transistors of a first comparator in a one-dimensional row in a first direction, arranging transistors of at least one additional comparator in the one-dimensional row in the first direction, and arranging transistors of the first comparator and the at least one additional comparator relative to each other in a second direction orthogonal to the first direction. | 09-01-2011 |
20120154189 | CURRENT SWITCH DRIVING CIRCUIT AND DIGITAL TO ANALOG CONVERTER - Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state. | 06-21-2012 |
20120176262 | Exponential-Logarithmic Analog-to-Digital Converter - The present invention provides an analog to digital converter by using an exponential-logarithmic model. The exponential-logarithmic analog-to-digital converter includes an exponential circuit which acquires an analog input voltage and generates an analog output voltage that is an exponential function of the input voltage. A positive feedback circuit that succeeds the exponential circuit exhibits a natural logarithmic characteristic. A comparator is connected to the positive feedback circuit to compare an output voltage of the positive feedback circuit with a reference voltage. Via the exponential-logarithmic conversion technique, the time interval or pulse produced by the positive feedback circuit is a linear function of the magnitude of the input voltage. Based on the comparator output, a counter is employed to translate the analog input signal to its digital representation. | 07-12-2012 |
20120229315 | N-BIT DIGITAL-TO-ANALOG CONVERTING DEVICE - An N-bit digital-to-analog converting device includes: a decoder for converting an N-bit binary digital signal into a multi-bit thermometer code during each cycle of a clock signal alternating between first and second states, N being an integer not less than two; a random number generator for generating a reset signal having at least one high logic level bit and at least one low logic level bit that are equal in number and that have a random, time-varying arrangement; and a converting module coupled electrically to the decoder and the random number generator, and configured to convert the thermometer code into an analog voltage corresponding to the digital signal when the clock signal is in the first state, and to reset the analog voltage to a reset value according to the reset signal when the clock signal is in the second state. | 09-13-2012 |
20120326905 | SIGMA-DELTA MODULATOR - Disclosed herein is a sigma-delta modulator, including an integration circuit, a first DAC unit, and a second DAC unit. The integration circuit includes first and second terminals, and integrates a voltage supplied via the first terminal. The first DAC unit alternately supplies a first voltage obtained at one end of a first resistor to the first terminal and the second terminal. The second DAC unit alternately supplies a second voltage at the other end of a second resistor to the second terminal or the first terminal. The second DAC unit supplies the second voltage to the second terminal when the first DAC unit supplies the first voltage to the first terminal. The second DAC unit supplies the second voltage to the first terminal when the first DAC unit supplies the first voltage to the second terminal. | 12-27-2012 |
20130044017 | PIPELINE A/D CONVERTER AND A/D CONVERTING METHOD - An A-type converter circuit compares an input voltage with multiple threshold voltages, judges which segment it belongs to, and generates first and second voltages with the input voltage segment between them. The A-type converter circuit generates third and fourth voltages by amplifying the differences between the first and the input voltages and between the second and the input voltages. A B-type converter circuit divides the range between the third and fourth voltages into multiple segments, and judges which segment includes the common voltage. Subsequently, the B-type converter circuit generates fifth and sixth voltages with the common voltage segment between them. The B-type converter circuit generates a seventh (the next stage's third voltage) and an eighth voltage by amplifying the differences between the fifth and the common voltages and between the sixth and the common voltages. | 02-21-2013 |
20130057420 | DIGITAL-TO-ANALOG CONVERTER - There is provided a digital-to-analog converter including: a mirror circuit including a first transistor to copy a reference current at a predetermined mirror ratio, and a second transistor cascade coupled with the first transistor; and an analog switch coupled with a gate of the second transistor, the analog switch being configured to be controlled, by a digital signal input from outside, so as to be turned on or off. | 03-07-2013 |
20130063291 | EXCESS LOOP DELAY COMPENSATION FOR A CONTINUOUS TIME SIGMA DELTA MODULATOR - A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined. | 03-14-2013 |
20130063292 | NMOS Buffer for High-Speed Low-Resolution Current Steering Digital-to-Analog Converters - The present disclosure provides techniques for using an NMOS field effect transistor-based buffer to buffer a pair of complementary digital signals and output a pair of equivalently fast rising and fast falling complementary signals to simultaneously drive a differential pair of PMOS transistors of a unit cell that output an analog signal for a current steering DAC. Accordingly, a DAC comprises a latch circuit and a unit cell circuit. The latch circuit includes an NMOS field effect transistor-based buffer and is capable of receiving a first digital signal and a clock signal and outputting a second digital signal through the NMOS field effect transistor-based buffer according to the clock signal. The second digital signal is associated with the first digital signal. The unit cell circuit, coupled to the latch circuit, receives the second digital signal and outputs an analog signal representative of the first digital signal. | 03-14-2013 |
20130113640 | DIGITAL-TO-ANALOG CONVERTING DEVICE - A digital-to-analog converting device converts an N-bit digital input signal into an analog signal using M reference voltages, where N>3 and M=2 | 05-09-2013 |
20130169458 | ISOLATION CIRCUIT FOR A DIGITAL-TO-ANALOG CONVERTER - An electronic circuit comprises a digital-to-analog converter (DAC) core circuit having a current source device and a digital input bit. An isolation circuit is also provided and is connected to the DAC core circuit. The isolation circuit is configured to selectively provide a source bias signal to the current source device. The isolation circuit also is configured to isolate the source bias signal from the current source device based on a state of the digital input bit. | 07-04-2013 |
20150318864 | CURRENT IMPULSE (CI) DIGITAL-TO-ANALOG CONVERTER (DAC) - A current impulse (CI) method is provided for converting digital data signals to analog values. First, digital data hits are converted into current impulses. Then, the current impulses are converted into analog currents representing the digital data hits. More typically, the method accepts a k-bit digital word, and converts the k-bit digital word into (k) corresponding current impulses. In one aspect, the method accepts (n) consecutive k-bit digital words. Then, for each bit position in the k-bit digital word, (n) consecutive bits are sampled using (n) consecutive phases of an n-phase clock, creating (n) interleaved current impulses. The (n) interleaved current impulses are converted into an analog current representing the (n) consecutive k-bit digital words. Alternatively, (n) consecutive hits are sampled using (n) consecutive phases of an n-phase clock for each bit position in the k-bit digital word, creating (n) summed current impulses. A CI digital-to-analog converter is also provided. | 11-05-2015 |
20160173113 | N-PATH CASCODE TRANSISTOR OUTPUT SWITCH FOR A DIGITAL TO ANALOG CONVERTER | 06-16-2016 |