Entries |
Document | Title | Date |
20080211702 | Comparator Chain Offset Reduction - Comparator chain total offset, static and dynamic, is reduced by injecting a compensation quantity in at least one point in the chain of comparator components. The compensation quantity is determined by providing the comparator chain with calibration signals having equal values and evaluating the output states of the comparator chain. The compensation quantity is adjusted until the probabilities of high and low output states are substantially equal and a calibrated value for the compensation is determined. | 09-04-2008 |
20080238738 | Output data correction device for analog-to-digital conversion circuit and analog-to-digital converted output data correction method - An output data correction device is provided for an A/D conversion circuit that achieves high precision over input voltage domains. An estimated maximum input ranging from 0 V to 5 V is divided into domains. A comparison circuit decides to which of the domains a voltage Vin input to a pulse phase-difference encoding circuit belongs. Control logic and a digital analog controller (DAC) select and transmit reference voltages associated with each of the domains. When each of the reference voltages is selected, a quadratic functional equation is computed and determined. A graph of the function passes coordinate points representing the reference voltages in a coordinate system with reference voltages and A/D-converted data values as dimensions. When each input voltage is selected, the A/D-converted digital data is corrected using the quadratic functional equation associated with the domain to which the input voltage Vin is decided to belong. | 10-02-2008 |
20080272942 | ANALOG TO DIGITAL CONVERTER AND RECORDING MEDIUM - An analog-to-digital conversion apparatus includes an interleaving section that aligns the digital data respectively output from a plurality of analog-to-digital conversion sections and generates a data sequence, and a correction arithmetic section that corrects a data value error caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, in which the correction arithmetic section includes: a data partitioning section that generates a plurality of partition data by partitioning the data sequence, a data inserting section that inserts data with data value zero at the head or end of each of the partition data by a predetermined insertion data number to sequentially output these data, an arithmetic section that sequentially outputs data after correction made by sequentially performing correction arithmetic on the partition data, and a data connecting section that adds sequentially connects the data after correction and the data after correction following the data after correction. | 11-06-2008 |
20080291066 | Composite analog to digital receiver with adaptive self-linearization - A distortion correcting analog to digital converter (ADC) system includes a plurality of ADCs configured to convert an analog signal to a plurality of digital ADC outputs, wherein the plurality of ADCs are configured to generate a composite signal based on the plurality of ADC outputs, there is an offset between a first one of the plurality of ADC outputs and a second one of the plurality of ADC outputs, the offset causing distortion in the composite signal. The system further includes an adaptive self-linearizer configured to receive the composite signal, and to perform self-linearization based on the composite signal to correct for the distortion in the composite signal. | 11-27-2008 |
20080291067 | Automatic range shift system and method for an Analog to Digital Converter - Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range. | 11-27-2008 |
20080297383 | Calibrating an analog component using digital feedback information - In one embodiment, the present invention includes an apparatus having an analog front end to receive a signal from a communication channel physical medium, an analog-to-digital converter (ADC) coupled to an output of the analog front end to digitize the received signal, and a digital signal processor (DSP) coupled to receive an output signal of the ADC and to process the digitized signal to generate a decision output and an error signal, and a feedback path to provide the error signal from the DSP to the ADC for use in calibration. Other embodiments are described and claimed. | 12-04-2008 |
20080316073 | Digital-to-analog converter and distortion correction circuit - Disclosed is a D/A converter including: a delta-sigma modulator for subjecting a digital signal to delta-sigma modulation; a pulse-width modulator for outputting a pulse-width-modulated signal having a pulse width conforming to a digital value that is output from the delta-sigma modulator; and a distortion detector for detecting a distortion component produced in the pulse-width modulator. The distortion detector includes a delay controller for receiving the digital signal and correcting the phase thereof; a second delta-sigma modulator; a second pulse-width modulator; a subtractor for subtracting the output of the second delta-sigma modulator from the output of the second pulse-width modulator; and a second subtractor for subtracting the output signal of the first subtractor from the output signal of the delay controller. | 12-25-2008 |
20090002210 | Analog correction of a phase-mismatch in high-sample rate time-interleaved analog-to-digital converters - A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered. | 01-01-2009 |
20090021406 | Sub-channel distortion mitigation in parallel digital systems - A method and apparatus for compensating for gain offset, bias offset, and skew in a parallel processing environment is disclosed. The method and apparatus may be configured to compensate for mismatches between the sub-channel signals in a parallel ADC. This allows for accurate combination of the signals on the sub-channels. The method and apparatus may be utilized in a high speed data communication system having two or more channels, each of which are interleaved into two or more sub-channels. In one embodiment a DC loop processes signals on two or more sub-channels to account for and remove unwanted bias offset. In one embodiment a sub-channel gain mismatch compensation system (SCGMC) processes signals on two or more sub-channels to account for and remove unwanted gain offset. In one embodiment a skew compensation system, such as a parallel interpolator, processes signals on two or more sub-channels to remove unwanted skew across sub-channels. | 01-22-2009 |
20090058697 | METHOD AND SYSTEM FOR MINIMIZING THE ACCUMULATED OFFSET ERROR FOR AN ANALOG TO DIGITAL CONVERTER - A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then combined to substantially remove the offset error. A system and method in accordance with the present invention compensates for the accumulated offset error over many samples, thereby achieving much higher accuracy in the offset error compensation. | 03-05-2009 |
20090073011 | CIRCUIT AND METHOD FOR GAIN ERROR CORRECTION IN ADC - Gain errors are corrected in an ADC chip including an integrator ( | 03-19-2009 |
20090102689 | MULTIPLE MODE SIGMA-DELTA MODULATOR - Modulation circuits for operating in at least a first and second mode are described herein. | 04-23-2009 |
20090135033 | APPARATUS AND METHOD FOR EFFICIENT ANALOG-TO-DIGITAL CONVERSION - For digitizing analog measurement signals, an analog-to-digital converter is used, wherein the offset to be subtracted from an analog measurement value is taken to account within a locked loop by means of which an analog-to-digital converter operating according to the modulation principle is fed back. | 05-28-2009 |
20090153380 | CURRENT COMPENSATION FOR DIGITAL-TO-ANALOG CONVERTER - A current compensation circuit and an optimized current compensation circuit are disclosed for a Parallel Resistors Architecture (PRA) digital-to-analog converter (DAC). The circuits are used to balance code dependent current consumption of the PRA-DAC. | 06-18-2009 |
20090167575 | Analog-To-Digital Converting Apparatus And Vehicle Power Supply Apparatus Using The Same - The A/D conversion apparatus and the vehicle power-supply device using the apparatus calculate errors at a plurality of reference voltages and reference errors prior to error correction. Each reference error is applied to a digital-output range that is divided by digital output corresponding to the reference voltages. In the calculation, when the errors obtained at adjacent reference voltages have same signs, the reference error is determined as an average of the errors obtained at adjacent reference voltages; on the other hand, when the errors obtained at adjacent reference voltages have different signs, the reference error is determined to be zero. The apparatus provides a corrected digital output by subtracting the reference error—which is applied to the digital-output range including the digital output—from the digital output corresponding to analog input voltage. | 07-02-2009 |
20090167576 | METHOD OF STEPWISE ELIMINATING VOLTAGE OFFSET AND VOLTAGE OFFSET ELIMINATION DEVICE IN ANALOG TO DIGITAL PIPELINE CONVERTER - Disclosed is a device of stepwise eliminating an offset voltage in an analog-to-digital pipeline converter. The device includes a sub analog-to-digital converter to convert an input signal inputted from a preceding stage into a first digital signal, a sub digital-to-analog converter to convert the first digital signal into a first analog signal, and an offset removing unit to remove a part of the offset voltage according to an offset code relative to the offset voltage based on a remaining signal to thereby generate a corrected remaining signal. | 07-02-2009 |
20090184853 | ANALOG TO DIGITAL CONVERTER WITH IMPROVED INPUT OVERLOAD RECOVERY - An aspect of the present invention avoids an amplifier of an analog to digital converter (ADC) from entering a saturation region. In an embodiment, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized. | 07-23-2009 |
20090189795 | QUANTIZATION ERROR REDUCTION IN PWM FULL-MASH CONVERTERS - Techniques for reducing quantization error in electronic components are described herein. | 07-30-2009 |
20090201184 | ANALOG ERROR CORRECTION FOR A PIPELINED CHARGE-DOMAIN A/D CONVERTER - A technique for correcting errors in Bucket Brigade Device (BBD)-based pipelined devices, such as Analog-to Digital Converters (ADCs). The gain between pipeline stages is desired to be a specific amount, such as unity: that is, all net charge present in each stage ideally is transferred to the next stage. In practical BBD-based circuits, however, the charge-transfer gain is less than ideal, resulting in errors. The approach described herein provides analog correction of such errors due to both capacitor mismatch and to sub-unity charge-transfer gain. In certain embodiments the adjustment circuit may use an adjustable current source and Field Effect Transistor to introduce the correction. In still other embodiments, the adjustment circuit may determine a voltage-feedback coefficient. | 08-13-2009 |
20090207058 | SAMPLING ERROR REDUCTION IN PWM-MASH CONVERTERS - Techniques for reducing sampling error in electronic components are described herein. | 08-20-2009 |
20090219185 | Adjusting an Input Signal Level of a Sigma-Delta Converter - The invention relates to adjusting an input signal level of a Sigma-Delta converter. A control signal indicative of an input signal level to said Sigma-Delta converter is generated, and the input signal level to said Sigma-Delta converter is adjusted in dependence of said control signal. The control signal is generated as a signal indicating an operating condition of said Sigma-Delta converter. In this way, internal signals from the Sigma-Delta converter can be used to determine the state of the Sigma-Delta converter, i.e. whether it is operating within its operational input range or not, and whether it is close to the limits of the operational input range. This provides a simple, but accurate guidance of an automatic gain control upstream of the Sigma-Delta converter. | 09-03-2009 |
20090243900 | ANALOG DIGITAL CONVERTER, A/D CONVERSION STAGE, METHOD FOR GENERATING DIGITAL SIGNAL CORRESPONDING TO ANALOG SIGNAL, AND METHOD FOR GENERATING SIGNAL INDICATING CONVERSION ERROR IN THE A/D CONVERSION STAGE - A conversion operation B is performed with respect to a sample value R in an A/D conversion stage | 10-01-2009 |
20090243901 | PIPELINE-TYPE ANALOG-TO-DIGITAL CONVERTER - A pipeline-type AID converter includes: N number of stages cascade-connected; and a digital correction circuit that receives digital signals outputted from the N number of stages and outputs a final digital signal. In the converter, an Mth stage in the N number of stages includes: a sub A/D converter A/D-converting an input analog signal; a sub D/A converter D/A converting a digital signal outputted from the sub A/D converter; a differential amplifier circuit that includes a sample hold circuit and an operational amplifier, performs an sampling operation and a holding operation to obtain a difference between the input analog signal and an output signal of the sub D/A converter, and amplifies the difference; and a compensation circuit compensating a gain error of the operational amplifier in an operation of the differential amplifier circuit, the gain error being caused by parasitic capacitance between an input terminal and an output terminal of the operational amplifier, and 1≦M10-01-2009 | |
20090261998 | APPARATUS AND METHOD FOR SIGMA-DELTA ANALOG TO DIGITAL CONVERSION - A method and apparatus are provided for sigma-delta (ΣΔ) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least One low-order bit. | 10-22-2009 |
20090273495 | ANALOG DIGITAL CONVERTING APPARATUS, ANALOG DIGITAL CONVERTING METHOD, TEST APPARATUS, PROGRAM AND RECORDING MEDIUM - Provided is an AD converting apparatus that converts an analog input signal into a digital output signal, comprising a plurality of AD converters that are supplied with sampling clocks differing from each other by a prescribed phase, and that each output an individual signal obtained by digitizing the input signal according to the sampling clock supplied thereto; a common compensating section that commonly compensates for prescribed common non-linear distortion in the individual signals; a plurality of individual compensating sections that each individually compensate for individual non-linear distortion in a corresponding one of the individual signals, the individual non-linear distortion obtained as a ratio between the non-linear distortion and the common non-linear distortion in each individual signal; and a combining section that combines the individual signals to generate the output signal. | 11-05-2009 |
20090315745 | Auto Ranging System and Method for Analog Signal - Disclosed herein are embodiments of an auto ranging system and method for an analog signal. A microprocessor is configured to digitally control the programmable gains of an operational amplifier based on the digital output of an A/D converter which may reside on or packaged along with the microprocessor. The amplifier receives a raw analog signal from a sensor and provides an amplified analog signal to the A/D converter. The gain of the amplifier generally corresponds to some range of the sensor signal. The A/D converter outputs a number of bits representative of the input signal. A microprocessor which is configured to digitally control the programmable gains of the amplifier receives and examines the output from the A/D converter and automatically adjusts the gain of the amplifier accordingly and as needed to keep or maintain the output from the A/D converter in a predetermined range. | 12-24-2009 |
20100001887 | INTEGRATED CIRCUIT WITH AUTO-ZEROING COMPARATOR STAGES THAT PROVIDE A CONTINUOUS-TIME SIGNAL - An integrated circuit includes first and second inputs configured to receive an input signal. A plurality of comparator stages is coupled in parallel to the first and second inputs. Each comparator stage is configured to perform a comparison on the input signal and provide an output signal based on the comparison. A control circuit is configured to cause the comparator stages to switch to an auto-zeroing mode in a staggered manner, thereby compensating offset voltages of the comparator stages while providing a continuous-time digital output signal. | 01-07-2010 |
20100019943 | Offset compensation scheme using a DAC - An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset. | 01-28-2010 |
20100060495 | ANALOG DIGITAL CONVERT APPARATUS, ANALOG DIGITAL CONVERT METHOD, CONTROL APPARATUS AND PROGRAM - Provided is an AD converting apparatus that converts an analog input signal into a digital output signal, comprising a plurality of AD converters supplied with sampling clocks differing from each other by prescribed phase amounts, each AD converter outputting an individual signal obtained by digitizing the input signal according to the supplied sampling clock; a plurality of amplitude-dependent characteristic correcting sections that are provided to correspond to the plurality of AD converters, each amplitude-dependent characteristic correcting section generating a corrected individual signal by correcting the individual signal output by the corresponding AD converter using a correction factor corresponding to an amplitude of the individual signal; and a combining section that generates the output signal by combining a plurality of the corrected individual signals. | 03-11-2010 |
20100060496 | MINIMIZING ADVERSE EFFECTS OF SKEW BETWEEN TWO ANALOG-TO-DIGITAL CONVERTERS - Skew between a first clock signal received by a first analog-to-digital converter (ADC) and a second clock signal received by a second ADC is adjusted to minimize error. Each ADC has an ADC element that produces a respective first or second digital output signal in response to an analog input signal and a respective first or second clock signal. A correction signal is produced in response to the first and second digital output signals. The skew between the first and second clock signals is then adjusted in response to the correction signal. | 03-11-2010 |
20100060497 | Group delay characteristic correcting device and group delay characteristic correcting method - A disclosed group delay characteristic correcting device corrects group delay characteristics of an analog low-pass filter used to remove aliasing of a digital-analog converter or an analog-digital converter. The group delay characteristic correcting device includes a digital signal processing unit configured to have an all-pass phase circuit at a stage previous to the digital-analog converter or at a stage subsequent to the analog-digital converter so as to correct the group delay characteristics of the analog low-pass filter. | 03-11-2010 |
20100066574 | Hybrid Analog to Digital Converter Circuit and Method - A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital converter circuit in communication with a voltage error signal. The high resolution analog to digital converter circuit is configured to provide a first correction signal to the digital controller when the voltage error signal is within a first error range. The hybrid analog to digital converter circuit also includes at least one flash analog to digital converter circuit in communication with the voltage error signal. The flash analog to digital converter circuit(s) is configured to provide at least a second correction signal to the digital controller when the voltage error signal is within at least a second error range. | 03-18-2010 |
20100073206 | ANALOG-TO-DIGITAL CONVERSION CIRCUITS AND METHOD FOR CALIBRATING THEREOF - An analog-to-digital conversion circuit is provided and includes an input unit, at least one analog-to-digital converter, and a processing unit. The input unit receives an analog input signal and outputs an analog output signal. A first reference signal is injected into the input unit, and the analog output signal is related to the first reference signal. The at least one analog-to-digital converter receives the analog output signal and converts the analog output signal to a digital output signal. The processing unit receives the digital output signal and performs correlation computation on the digital output signal with a second reference signal to generate a calibration parameter. | 03-25-2010 |
20100085226 | ANALOG CORRECTION OF A PHASE-MISMATCH IN HIGH-SAMPLE RATE TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered. | 04-08-2010 |
20100090873 | SYSTEMS AND METHODS FOR CHARACTERIZING COMPONENT RATIOS AND GENERATING A DIGITAL REPRESENTATION OF SAME - Circuits and methods for determining component ratios are provided. An analog to digital converter circuit may include comparison capacitors arranged in an upper group and a lower group for quantizing analog signals into the digital domain. In addition to determining the lower bits during an analog to digital conversion of an input sample, the lower group of comparison capacitors may also be used during calibration mode to quantize a ratio signal that represents the capacitor mismatches of the upper group rather than using a dedicated digital-to-analog converter to perform this function. | 04-15-2010 |
20100090874 | Digital-Analog conversion circuit and output data correction method of the same - A digital-analog conversion circuit includes a correction unit that adds a correction bit to a lower-order bit of externally input first digital input data and outputs second digital input data, and a conversion unit that receives the second digital input data and outputs an analog value, and the correction unit generates the second digital input data by manipulating data of a lower-order bit of the second digital input data around a point at which an error between the analog value and an expected value set for the first digital input data becomes larger than a preset value. | 04-15-2010 |
20100097252 | CALIBRATION DEVICE AND METHOD THEREOF FOR PIPELINED ANALOG-TO-DIGITAL CONVERTER - A calibration device comprises a comparison unit, a counting unit, a memory, and a compensation circuit. A residue of a sub analog-to-digital converter is compared with a first and a second voltage by the comparison unit for generating a comparison result. A number of times of the residue voltage, out of bounds defined by the first and the second voltage, is counted by the counting unit in an i | 04-22-2010 |
20100103003 | Method and Apparatus for Dithering in Multi-Bit Sigma-Delta Analog-to-Digital Converters - A multi-bit (M-bit, M>1) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder. | 04-29-2010 |
20100103004 | CORRELATED NOISE AND SPURIOUS SIGNAL REDUCTION - Error introduced by analog to digital conversion of a set of laser pulses can be reduced by shifting the clock reference time associated with the firing of the laser pulse. A timing offset module shifts the timing reference of each laser pulse. Digital codes generated by the ADC from the received signals are realigned and summed eliminating systematic error introduced by clock driven operations of the ADC. A comparison of the total ADC output of detected laser pulses over a select number of clock intervals enables a return signal to be distinguishable over the systematic error. | 04-29-2010 |
20100109924 | Method and apparatus for digital error correction for binary successive approximation ADC - An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code. | 05-06-2010 |
20100117876 | Apparatus and method for analog-to-digital converter calibration - An analog-to-digital converter (ADC) is provided. The ADC includes a reference voltage generator configured to generate reference voltages, an analog to digital converter core configured to receive an input signal and the reference voltages and to generate a digital signal representative of the input signal, the digital signal having a number of bits, and a controller configured to determine a quality of the input signal, and, based on a quality of the input signal, to control the number of bits of the digital signal and values of the reference voltages. | 05-13-2010 |
20100134333 | Apparatus for Monitoring Non-Linear Distortions of Radio Signals and a Method Therefor - A transmitter ( | 06-03-2010 |
20100134334 | METHOD AND DEVICE FOR DIGITALLY CORRECTING DC OFFSET - There is provided a digital Direct Current (DC) offset correction method and device. The device includes a digital-analog converter charging a load capacitor according to an input code value and generating an initial voltage value of the load capacitor; a comparator comparing an output DC offset value of a discrete-time amplifier and filter on the basis of the initial voltage value with a preset output DC offset value when the discrete-time amplifier and filter and the load capacitor are connected to each other; and a controller changing the input code value of the digital-analog converter according to comparison result of the comparator. | 06-03-2010 |
20100134335 | APPARATUS FOR COMPENSATING FOR ERROR OF TIME-TO-DIGITAL CONVERTER - An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors. | 06-03-2010 |
20100141491 | PHASE-LOCKED LOOP CIRCUITRY USING CHARGE PUMPS WITH CURRENT MIRROR CIRCUITRY - A system and method for performing phase-locked loop is disclosed. The system includes phase frequency detector circuitry, charge pump circuitry having first current mirror circuitry and second current mirror circuitry, loop filter circuitry, and voltage controlled oscillator circuitry. The phase frequency detector circuitry generates an up signal and a down signal based on the phase difference of an input signal and a feedback signal. The charge pump circuitry includes the first current mirror circuitry and the second mirror circuitry and generates a charge pump output signal based on the up and down signals. The loop filter circuitry generates a filtered control signal based on the charge pump output signal. The voltage controlled oscillator circuitry generates the feedback signal with a repeating waveform based on the filtered control signal. | 06-10-2010 |
20100149006 | ETHERNET SYSTEM - Four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair for transmission only, another for reception only and the other two (2) for transmission and reception. The signals in the wires are in packets each having timing signals defining a preamble and thereafter having digital signals representing information as by individual ones of three (3) amplitude levels. The signals received at the computer are provided with an automatic gain control (AGC) and then with digital conversions at a particular rate. A control loop operative upon the digital conversions regulates the AGC gain at a particular value. An equalizer operative only during the occurrence of the digital signals in each packet selects an individual one of the three (3) amplitude levels closest to the amplitude of each digital conversion at the time assumed to constitute the conversion peak. The amplitudes of the timing signals in each preamble at the times assumed to constitute the peaks and zero crossings of such signals are multiplied. The rate of such digital conversions is adjusted in accordance with the polarity and magnitude of the multiplication product. The relative amplitudes of the successive equalizer values following each preamble are evaluated at the times assumed to be the peaks of the digital conversions. The rate of the digital conversions is adjusted in accordance with such evaluations, thereby further regulating the digital conversions at the particular rate. The equalizer thus operates on the information signals in each packet at the signal peaks. | 06-17-2010 |
20100164762 | METHODS AND APPARATUS TO TEST AND COMPENSATE MULTI-CHANNEL DIGITAL-TO-ANALOG CONVERTERS - Methods and apparatus to test and compensate multi-channel digital-to-analog converters (DACs) are described. In some examples, a multi-channel digital-to-analog converter (DAC) and an error detector are implemented in an integrated circuit. The multi-channel DAC includes a first DAC channel configured to generate a first analog representation of a digital input signal, and a second DAC channel configured to generate a second analog representation of the digital input signal. The error detector is configured to compare the first analog representation and the second analog representation to generate a difference signal, and to output a signal indicative of whether the difference signal is greater than a predetermined threshold. | 07-01-2010 |
20100164763 | ERROR ESTIMATION AND CORRECTION IN A TWO-CHANNEL TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A two-channel time-interleaved analog-to-digital converter (TIADC) system that provides for estimation and correction of offset, gain, and sample-time errors. Error in the offsets of the two ADCs that form the TIADC produces a spurious signal at the Nyquist frequency that can be used to minimize the difference of offsets of the ADCs. The difference in gain between the two ADCs produces spurious signals reflected around the Nyquist frequency whose magnitudes can be reduced by minimizing the difference in signal power between the two ADCs. An Automatic Gain Control loop corrects the scaling of the input signal due to the average of the gains of the ADCs. Phase error produces spurious signals reflected around the Nyquist frequency that are π/2 out of phase with those due to the gain error. Minimizing the difference between the correlation of consecutive signals from the ADCs reduces the magnitude of these image tones. | 07-01-2010 |
20100164764 | Systems and Methods for Mitigating Latency in a Data Detector Feedback Loop - Various embodiments of the present invention provide systems and methods for mitigating latency in a data detector feedback loop. For example, a method for reducing latency in an error corrected data retrieval system is disclosed. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error. | 07-01-2010 |
20100171643 | Techniques for Delay Compensation of Continuous-Time Sigma-Delta Modulators - A technique for implementing compensatory feedback in a continuous-time sigma-delta modulator includes providing, based on an analog input signal, a digital output signal at an output of a quantizer circuit of the continuous-time sigma-delta modulator. A functionality of the quantizer circuit is then controlled based on the digital output signal. | 07-08-2010 |
20100176975 | RD Converter and Angle Detecting Apparatus - An RD converter is disclosed that has a first multiplier multiplying a resolver signal S | 07-15-2010 |
20100182174 | COMPENSATION OF MISMATCH ERRORS IN A TIME-INTERLEAVED ANALOG- TO- DIGITAL CONVERTER - A method for the compensation of frequency-response mismatch errors in M-channel time-interleaved ADCs. The compensation is done through an M-periodic time-varying filter h | 07-22-2010 |
20100194611 | RECEPTION CIRCUIT, METHOD OF CREATING AD CONVERTER CONVERSION TABLE OF RECEPTION CIRCUIT, AND SIGNAL TRANSFER SYSTEM - A reception circuit includes: an AD converter that outputs digital data in accordance with an input signal; a correction circuit that corrects nonlinearity of the AD converter; and an equalization circuit that equalizes the corrected digital data, wherein the correction circuit includes: a conversion table used to convert digital data output from the AD converter; and a correction amount computation circuit that creates the conversion table from the output data of the AD converter and the output of the equalization circuit. The correction amount computation circuit creates the conversion table so that there is no dependence between the ADC output value of the AD converter and the estimation result by the equalization circuit for the ADC output value. | 08-05-2010 |
20100207790 | ANALOG INPUT AND OUTPUT CIRCUIT AND VACUUM PROCESSING APPARATUS - The invention provides an analog input and output circuit and a vacuum processing apparatus capable of automatically performing the correction of all analog inputs and outputs via a single reference voltage adjustment, thereby solving the prior art problem of requiring a different correction value for each channel for accurately controlling the analog input and output due to the difference in the on resistances of switches for respective channels of an analog multiplexer. The prevent invention comprises an A/D converter | 08-19-2010 |
20100207791 | SAR ADC AND METHOD WITH INL COMPENSATION - An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for providing a digital code representing a conversion result, and an integral non-linearity (INL) compensator configured to provide an INL compensation signal for reducing INL of the analog-to-digital conversion in response to the digital code. | 08-19-2010 |
20100214140 | DIGITAL TRIMMING OF SAR ADCS - Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs. | 08-26-2010 |
20100225510 | Correction circuit for D/A converter - There is provided a correction circuit for a D/A converter, comprising: a constant current source to be connected between high- and low-potential power source lines for supplying a power source voltage to the D/A converter; and a current controller which is adapted to control a current flowing to the constant current source in accordance with an input digital signal to the D/A converter, so as to reduce a variation of a sum of currents which, when the input digital signal to the D/A converter is changed, flows to the low-potential power source line from the high-potential power source line through the D/A converter and the constant current source, respectively. | 09-09-2010 |
20100225511 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT - An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a first correction capacitor. Each of the D/A conversion circuits outputs an output signal to the input capacitor. The first correction D/A conversion circuit outputs a correction output voltage to the first correction capacitors to correct data signals output from the data line driver circuits. | 09-09-2010 |
20100225512 | A/D CONVERSION CIRCUIT FOR USE WITH LOW-POTENTIAL AND HIGH-POTENTIAL POWER SUPPLIES - A D/A conversion circuit for performing D/A conversion at high speeds. The D/A conversion circuit includes a resistor string including a plurality of resistor elements connected between a low-potential power supply and a high-potential power supply. A plurality of first switch groups are connected to the connection nodes between the resistor elements for selectively outputting voltages at the connection nodes. The outputs of the switches of the first switch groups are connected in common to a corresponding one of the nodes. The plurality of nodes are connected to an output terminal of the D/A conversion circuit via a second switch group. Predetermined switches of the first switch groups are connected in parallel to third switches to apply voltages to the nodes. | 09-09-2010 |
20100231427 | ELECTRONIC CIRCUIT FOR CORRECTING AT LEAST ONE DIGITAL MEASUREMENT SIGNAL - An electronic circuit for correcting at least one digital measurement signal (ΣΔn, ΣΔ | 09-16-2010 |
20100245136 | Methods and Apparatus for Whitening Quantization Noise in a Delta-Sigma Modulator Using Dither Signal - Methods and apparatus are provided for whitening quantization noise in a delta-sigma modulator using a dither signal. An input signal is quantized using a predictive delta-sigma modulator by quantizing the input signal using a quantizer; adding a dither signal at a first location of the predictive delta-sigma modulator; determining a quantization error associated with the quantizer; removing the dither signal at a second location of the predictive delta-sigma modulator (for example, by subtracting a substantially similar version of the dither signal at the second location); generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. The dither signal may be a white noise signal and may optionally be generated using a pseudo-random number generator. | 09-30-2010 |
20100245137 | Methods and Apparatus for Look-Ahead Block Processing in Predictive Delta-Sigma Modulators - Methods and apparatus are provided for look-ahead block processing in predictive delta-sigma modulators. An input signal is quantized using a predictive delta-sigma modulator by generating error prediction values for a current block of input values based on a linear combination of error prediction values from one or more previous blocks, input values of one or more previous blocks, quantized values of one or more previous blocks and the current block of input values; computing speculative error prediction values for at least one input value in the current block, wherein the speculative error prediction values are computed for a plurality of possible quantizer output values; selecting one of the speculative error prediction values based on a quantized value from the current block; and subtracting the error prediction values for the current block from the corresponding current block of input values. | 09-30-2010 |
20100245138 | METHODS AND APPARATUS FOR DECORRELATING QUANTIZATION NOISE IN A DELTA-SIGMA MODULATOR - Methods and apparatus are provided for decorrelating quantization noise in a delta-sigma modulator. An input signal is quantized using a predictive delta-sigma modulator, by quantizing the input signal using a quantizer; determining a quantization error associated with the quantizer by subtracting an input to the quantizer from an output of the quantizer; measuring a correlation coefficient between the quantization error and an input to the quantizer; reducing the measured correlation by subtracting a multiple of the input to the quantizer from the quantization error, wherein the multiple is based on the correlation coefficient; generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. | 09-30-2010 |
20100245139 | PULSE MODULATION A/D-CONVERTER WITH FEEDBACK - The invention relates to an A/D converter comprising an input and an output, a D/A converting feedback and a pulse width modulating forward path, the D/A converting feedback comprising at least one feed-back path, the feed-back path establishing a D/A conversion based on at least two D/A conversions subject to uncorrelated errors. | 09-30-2010 |
20100253557 | CALIBRATION OF OFFSET, GAIN AND PHASE ERRORS IN M-CHANNEL TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over N | 10-07-2010 |
20100283641 | ANALOG TO DIGITAL CONVERTER - An analog to digital converter is provided. The converter comprises a dither gain generator, a first stage, an adder, a second stage, and a digital error correction logic. The dither gain generator generates a dither gain. The first stage receives a first voltage to generate a first digital code and a second voltage. The adder is coupled to the first stage and adds the dither voltage to the second voltage to generate a third voltage. The second stage receives the third voltage to generate a second digital code. The digital error correction logic receives and corrects the first digital code and the second digital code to generate a digital code corresponding to the first voltage. | 11-11-2010 |
20100302083 | TRANSMITTER WITH DELAY MISMATCH COMPENSATION - A transmitter device is provided which comprises a digital part (DP) and an analog part (AP). The transmitter device furthermore comprises a digital modulator (DM) in the digital part (DP) for receiving bits (MB) and for digitally modulating the receiving bits (MB). A first (IDAC; RDAC) and second digital-to-analog converter (QDAC; ODAC) are provided. The transmitter device furthermore comprises at least one filter unit (H | 12-02-2010 |
20100309033 | CORRECTION OF SAMPLING MISMATCH IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals. | 12-09-2010 |
20100309034 | PIPELINE ADC - Pipeline analog-to-digital converters (ADCs) are used in many applications, but because of the configuration, components may be idled, which wastes power. Here, an ADC is provided that enables one or more stages to be switched off during a power conservation mode. By using switch networks, the ADC can produce accurate results with reduced power consumption, as desired. | 12-09-2010 |
20110001644 | METER AND FREEZE OF CALIBRATION OF TIME-INTERLEAVED ANALOG TO DIGITAL CONVERTER - A technique for improving the operation of a Time Interleaved Analog to Digital Converter (TIADC) by suppressing updates and/or correction to updates of an interleave mismatch errors estimator when one or more predetermined conditions | 01-06-2011 |
20110006933 | TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least one of the clock signals so as to sample an input signal that is generally wide-sense stationary at sampling instants, where correlation function exist between samples from a two or more of the ADCs that is a function of the time differences between associated sampling instants. The estimator is coupled to each of the adjustable delay elements and each of the ADCs so as to calculate the correlation function and adjust the adjustable delay elements to account for sampling mismatch between the ADCs based at least in part on the correlation function. | 01-13-2011 |
20110012762 | METHOD AND DEVICE FOR DIGITIZING AN ANALOG ELECTRICAL SIGNAL AND METHOD FOR DIGITIZING - A method and a device are disclosed for digitizing an analog electrical signal, in which the signal is applied to a number of subchannels connected in parallel. In at least one embodiment, the amplitude ranges of immediately adjacent subchannels with respect to amplitude are in each case displaced overlapping one another, in which the overlapping amplitude ranges include the total amplitude range, in which a subchannel serves as reference channel, in which, on the basis of the reference channel, the digital output value of the immediately adjacent subchannel with respect to amplitude is corrected when the signal is in the overlap range of the two subchannels and the digital values differ from one another, and in which a total digital value is output by way of a digital output value, taking into consideration the displacements of the amplitude ranges with respect to one another. | 01-20-2011 |
20110018749 | CHARACTERISTIC ACQUISITION DEVICE, METHOD AND PROGRAM - It is possible to reduce errors generated between multiple D/A conversion paths. A characteristic acquisition device includes [1] an arbitrary signal generator that converts a first (second) input digital pattern into a first (second) output analog pattern, [2] a digitizer that converts a first input analog pattern into a first output digital pattern, and [3] a characteristic acquisition device that includes a first transmission characteristic deriving unit that derives a first transmission characteristic which converts the first input digital pattern into the output digital pattern where the input analog pattern is the first output analog pattern, a second transmission characteristic deriving unit that derives a second transmission characteristic which converts the second input digital pattern into the output digital pattern where the input analog pattern is the second output analog pattern, and a transmission characteristic ratio deriving unit that derives a transmission characteristic ratio which is a ratio relating to the first transmission characteristic and the second transmission characteristic. | 01-27-2011 |
20110018750 | ERROR CORRECTION METHOD AND APPARATUS - A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor. | 01-27-2011 |
20110025535 | METHOD FOR GENERATING AN ANALOG SIGNAL GENERATED BY PWM SIGNAL, AND SYSTEM GENERATING SUCH SIGNAL - The present invention relates to a generation method of an analogue signal generated by a PWM signal whose cyclic ratio and period are parametrizable. It is thus possible choose the pair formed from the cyclic ratio and the period producing an analogue value that is the closest to the value corresponding to the programmed command value. But the differences between the analogue values can be very great and generate zones of imprecision of variable width. Outside of these zones, the generated analogue signal is very precise. As a result, when the command value associated with a pair is imprecise, a digital shift is applied to the command value at the same time as the application of an analogue shift means. Both shifts have the same amplitude and of opposite directions such that the cancel each other out, producing a precise analogue value. | 02-03-2011 |
20110037628 | METHOD AND SYSTEM FOR ACCELERATED ANALOG TO DIGITAL CONVERSION - Techniques for accelerated processing associated with analog to digital signal conversion are disclosed. Accelerated processing is provided for sample-and-hold and track-and-hold circuits used with analog to digital converters in various embodiments. An abbreviated sampling state, an abbreviated reset state, or both are employed in various embodiments. By accelerating processing so as to avoid the need for waiting for a signal to settle within a predetermined tolerance, errors of different types may be incurred. Such errors are determined during calibration and stored for future retrieval and error compensation. Techniques for online and offline calibration are disclosed, whereby calibration may or may not impact normal signal conversion processing. Techniques disclosed herein find broad applicability in analog to digital conversion and yield faster processing in a variety of contexts. | 02-17-2011 |
20110043392 | SAMPLER LINEARITY BY SIMULTANEOUS DERIVATIVE SAMPLING - A circuit for improved sampler linearity, in an analog to digital converter, by taking simultaneous analog samples of an input signal V(t) and its derivative, dV/dt. The correction can be implemented as a memoryless non-linear model in the analog, digital, or mixed signal domains. Delay elements placed in the clock signal path or main input signal path can provide more precise control over the correction. | 02-24-2011 |
20110063146 | MULTISTAGE CHOPPER STABILIZED DELTA-SIGMA ADC WITH REDUCED OFFSET - A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy. | 03-17-2011 |
20110063147 | SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER (ADC) AND METHOD OF ADJUSTING DELAY THEREOF - A successive approximation register analog-to-digital converter includes: a digital-to-analog converter that generates an analog voltage based on a digital code; a comparator that receives the analog voltage; a control circuit that generates a digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on a comparison result of the comparator; a delay circuit that resets the comparator based on a signal transition generated by delaying the comparison result; and an adjustment circuit that counts a value indicating a number of the signal transition being generated during a cycle of the external clock signal and adjusts a delay of the delay circuit according to a counted value. | 03-17-2011 |
20110063148 | Imbalance and distortion cancellation for composite analog to digital converter (ADC) - Imbalance and distortion cancellation for composite analog to digital converter (ADC). Such an ‘ADC’ is implemented using two or more ADCs may be employed for sampling (e.g., quantizing, digitizing, etc.) of an analog (e.g., continuous time) signal in accordance with generating a digital (e.g., discrete time) signal. Using at least two ADCs allows for the accommodation and sampling of various signals having a much broader dynamic range without suffering degradation in signal to noise ratio (SNR). Generally, the signal provided via at least one of the paths corresponding to at least one of the respective ADCs is scaled (e.g., attenuated), so that the various ADCs effectively sample signals of different magnitudes. The ADCs may respectively correspond to different magnitude and/or power levels (e.g., high power, lower power, any intermediary power level, etc.). Various implementations of compensation may be performed along the various paths corresponding to the respective ADCs. | 03-17-2011 |
20110063149 | CALIBRATION OF OFFSET, GAIN AND PHASE ERRORS IN M-CHANNEL TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over N | 03-17-2011 |
20110068961 | A/D CONVERSION DEVICE AND SERVO CONTROL DEVICE - In a feedback control device ( | 03-24-2011 |
20110074611 | Sub-channel distortion mitigation in parallel digital systems - A method and apparatus for compensating for gain offset, bias offset, and skew in a parallel processing environment is disclosed. The method and apparatus may be configured to compensate for mismatches between the sub-channel signals in a parallel ADC. This allows for accurate combination of the signals on the sub-channels. The method and apparatus may be utilized in a high speed data communication system having two or more channels, each of which are interleaved into two or more sub-channels. In one embodiment a DC loop processes signals on two or more sub-channels to account for and remove unwanted bias offset. In one embodiment a sub-channel gain mismatch compensation system (SCGMC) processes signals on two or more sub-channels to account for and remove unwanted gain offset. In one embodiment a skew compensation system, such as a parallel interpolator, processes signals on two or more sub-channels to remove unwanted skew across sub-channels. | 03-31-2011 |
20110080309 | BANDWIDTH MISMATCH ESTIMATION FOR TIME INTERLEAVED ADCS - With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a significant problem. Previously, though, no adequate solution has been found. Here, a method and apparatus are provided that can calculate and compensate for bandwidth mismatches in a TI ADC, enabling a high speed, high resolution TI ADC to be produced. | 04-07-2011 |
20110084861 | APPARATUS AND METHOD FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipeline analog-to-digital converter includes a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade. At least one of the MDAC stages includes two or more flash ADCs connected in parallel, operating alternately to generate digital signals from an analog input voltage. In one embodiment, the flash ADCs provide the digital signals in an alternating manner to a capacitor block that receives a delayed analog input voltage. In another embodiment, the at least one MDAC may include two or more capacitor blocks, each of which is associated with a respective one of the flash ADCs, forming two or more sets of a flash ADC and a capacitor block. In yet another embodiment, the at least one MDAC also include three or more capacitor blocks, each of which can be randomly selected for one of the flash ADCs. | 04-14-2011 |
20110102215 | Analog-Digital Converter - The present system is based on an analog-digital converter (ADC) having an analog input signal and at least one quantization threshold. The analog-digital converter (ADC) includes an arrangement for varying the at least one quantization threshold. | 05-05-2011 |
20110102216 | APPARATUS FOR CORRECTING SETTING ERROR IN AN MDAC AMPLIFIER - Multiplying digital-to-analog converters (MDACs), which are generally employed in pipelined analog-to-digital converters (ADCs), can have a settling error associated with the MDAC amplifier. Here, a circuit is provided that includes additional amplifiers and a capacitor network that compensates for this settling error. Thus, a more accurate pipelined ADC can now be produced. | 05-05-2011 |
20110115658 | DUAL DAC STRUCTURE FOR CHARGE REDISTRIBUTED ADC - A system for converting an analog signal to a digital codeword having N bit positions that includes a dual DAC structure having a small DAC and a large DAC. At least one comparator is coupled to the small DAC and large DAC. The small DAC performs bit trials to calculate bit positions 1 to M, and the large DAC with performs bit trial calculates bit positions M+1 to N after having been set with bit decisions from the bit trials of the small DAC. | 05-19-2011 |
20110115659 | OFFSET COMPENSATION SCHEME USING A DAC - An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset. | 05-19-2011 |
20110122005 | METHOD TO LINEARIZE THE OUTPUT FROM AN ADC - A method is disclosed of compensating the output of an ADC for non-linearity in the response of the ADC. The method comprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables. | 05-26-2011 |
20110133966 | SWITCHED-CAPACITOR INPUT CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER INCLUDING THE SAME - A switched-capacitor input circuit which receives an analog input signal, and samples and holds the analog input signal, comprising an amplifier, at least one capacitor, one terminal of the capacitor being connected to an input terminal of the amplifier, and a first switch configured to selectively connect the other terminal of the capacitor to one of a first reference voltage, a second reference voltage, and a third reference voltage, wherein the first switch connects the other terminal of the capacitor to the first reference voltage so as to perform offset correction of ternary weight | 06-09-2011 |
20110133967 | High Speed Latch Comparators - In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage. | 06-09-2011 |
20110148675 | Analog/Digital Or Digital/Analog Conversion System Having Improved Linearity - A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state). | 06-23-2011 |
20110187568 | Current-mode DAC capable of prospective correction - A current-mode DAC includes at least one to-be-corrected one current source, a referential current source, a current comparator for comparing the current of the to-be-corrected current source and the current of the referential current source, a correction controller, a successive approximation register controller controlled by the correction controller and referring to the result of the comparison for carrying out successive approximation, and at least one correction DAC electrically connected with the successive approximation register controller and the to-be-corrected current source for referring to the result acquired from the successive approximation register controller and then providing a bias for the to-be-corrected current source for carrying out current correction. Accordingly, the corrected current can have the excellent accuracy. | 08-04-2011 |
20110193731 | Analog-to-digital converter using oscillators - An apparatus is provided which has a first analog input and a second analog input. In a particular implementation, the first analog input is coupled to a first controllable oscillator and the second analog input is coupled to a second controllable oscillator. First and second digital output signals generated based on output oscillations from the first controllable oscillator and the second controllable oscillator are combined. | 08-11-2011 |
20110193732 | BANDWIDTH MISMATCH ESTIMATION IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a significant problem. Previously, though, no adequate solution has been found. Here, a method and apparatus are provided that can calculate and compensate for bandwidth mismatches in a TI ADC, enabling a high speed, high resolution TI ADC to be produced. | 08-11-2011 |
20110205092 | ELECTRONIC DEVICE - An electronic device includes a frequency variable circuit, a filter, and an output voltage decision circuit. The frequency variable circuit changes the sampling frequency of an analog-digital converter. The filter limits the pass band of the output signal of the analog-digital converter. The output voltage decision circuit determines the noise level of the output signal of the analog-digital converter after the output signal passes through the filter. The electronic device performs self-diagnosis as follows. The frequency variable circuit changes the sampling frequency of the analog-digital converter to a frequency outside of the pass band of the filter so as to change the quantization noise level of the analog-digital converter. Then, the output voltage decision circuit determines whether the integral of the quantization noise level is within a predetermined range. | 08-25-2011 |
20110227767 | COMPENSATING FOR HARMONIC DISTORTION IN AN INSTRUMENT CHANNEL - Automatic test equipment (ATE) includes circuitry configured to pass a signal in a channel of the ATE, and memory configured to store a first and second correction values. A first correction value is based on a first version of the signal, where the first correction value is for use in correcting static non-linearity associated with the channel. A second correction value is based on a second version of the signal, where the second correction value is for use in correcting dynamic non-linearity associated with the channel. Digital signal processing logic is configured to use the first correction value, the second correction value, and the signal in order to compensate for harmonic distortion from the channel. | 09-22-2011 |
20110227768 | Imbalance and distortion cancellation for composite analog to digital converter (ADC) - Imbalance and distortion cancellation for composite analog to digital converter (ADC). Such an ‘ADC’ is implemented using two or more ADCs may be employed for sampling (e.g., quantizing, digitizing, etc.) of an analog (e.g., continuous time) signal in accordance with generating a digital (e.g., discrete time) signal. Using at least two ADCs allows for the accommodation and sampling of various signals having a much broader dynamic range without suffering degradation in signal to noise ratio (SNR). Generally, the signal provided via at least one of the paths corresponding to at least one of the respective ADCs is scaled (e.g., attenuated), so that the various ADCs effectively sample signals of different magnitudes. The ADCs may respectively correspond to different magnitude and/or power levels (e.g., high power, lower power, any intermediary power level, etc.). Various implementations of compensation may be performed along the various paths corresponding to the respective ADCs. | 09-22-2011 |
20110241913 | AD CONVERSION CIRCUIT AND ERROR CORRECTING METHOD - In a microcomputer | 10-06-2011 |
20110248874 | TIME STAMP GENERATION - A circuit and method for providing a digital output indicative of the time at which an event occurred is disclosed. In one aspect, the circuit includes a fine timing circuit configured to determine in which sub-interval of a clock period the event occurred, and a correction circuit configured to correct an erroneous offset between a first and second clock signals in the fine timing circuit. The correction circuit includes a synch circuit configured to determine in which half of the clock period the event occurred so as to correct for erroneous offset in the fine timing circuit. | 10-13-2011 |
20110260899 | INL correction circuitry and method for SAR ADC - INL error in a SAR ADC ( | 10-27-2011 |
20110267211 | ANALOG-DIGITAL CONVERTER AND OPERATING METHOD THEREOF - In this invention, the accuracy between an input analog voltage and a digital output signal can be enhanced. A background digital correction type A/D converter includes a reference A/D conversion unit, a main A/D conversion unit, and a digital corrector. The main A/D conversion unit executes an A/D converting operation at a high speed, whereas the reference A/D conversion unit executes an A/D converting operation with high resolution, respectively. Each of main digital output signals of the main A/D conversion unit and a reference digital output signal of the reference A/D conversion unit are supplied to one input terminal of the digital corrector and the other input terminal thereof respectively. The digital corrector outputs a correction-processing digital output signal. The reference A/D conversion unit includes a ΣΔ A/D converter and a Nyquist filter. The Nyquist filter suppresses a high-frequency quantization error of the ΣΔ analog-digital converter. | 11-03-2011 |
20110285563 | PIPELINED ANALOG-TO-DIGITAL CONVERTER AND SUB-CONVERTER STAGE - The present invention introduces a sub-converter stage used in a pipelined analog-to-digital converter. The sub-converter stage comprises an amplifier with a gain A, a sub analog-to-digital converter with comparators and a digital unit, a first capacitor with capacitance C, a second capacitor with capacitance C−ΔC, and customized reference signal V | 11-24-2011 |
20110298641 | Bubble Correction in a Flash Analog-To-Digital Converter - Embodiments of a flash analog-to-digital converter (ADC) that can detect and suppress bubbles in a thermometer code of a flash ADC are provided herein. Bubbles can result in large sparkle errors, which degrade the bit error rates (BER) of flash ADCs. The present invention utilizes a bubble correction module that is configured to provide a bubble corrected one-of-N code by suppressing at least one of any two tops that are not separated by at least two levels within a one-of-N code. | 12-08-2011 |
20110304489 | METHODS OF AND ARRANGEMENTS FOR OFFSET COMPENSATION OF AN ANALOG-TO-DIGITAL CONVERTER - An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset. | 12-15-2011 |
20120001783 | DEVICE AND METHOD FOR DIGITIZING A SIGNAL | 01-05-2012 |
20120007756 | Digital signal processing based de-serializer - A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representation of the modulated analog serial data). The DSP communicatively couples to the ADC and receives the digitized serial data. Based upon the known characteristics of the digitized serial data and the digitized serial data itself, the DSP determines compensation operations to be performed upon the serial data to compensate for inadequacies of the receiver and/or channel response. These compensation operations may be (1) performed on the analog serial data before digitization by the ADC; (2) applied to the ADC to modify the operation of the ADC; and/or (3) performed on the digitized serial data by the DSP or another device. | 01-12-2012 |
20120013492 | PROGRAMMABLE LINEARITY CORRECTION CIRCUIT FOR DIGITAL-TO- ANALOG CONVERTER - The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal. | 01-19-2012 |
20120032825 | METHOD FOR CORRECTING AMPLITUDE AND PHASE OFFSETS IN A SIGMA-DELTA MODULATOR AND SIGMA-DELTA MODULATOR IMPLEMENTING SAID METHOD - In a method for correcting amplitude and phase offsets in a sigma-delta modulator having a loop including an integrator with a filter and an amplifier, an analog-to-digital converter, a digital-to-analog converter, and an adder-subtractor, an open-loop amplitude/phase frequency response of the modulator is estimated digitally. A phase offset value and an amplitude offset value are calculated by comparing the estimated open-loop amplitude/phase response with a reference amplitude/phase frequency response. The phase and gain offsets of the loop are then compensated for according to the estimated offset values. A sigma-delta modulator implements the method. | 02-09-2012 |
20120062400 | ANALOG DIGITAL CONVERTING DEVICE AND REFERENCE VOLTAGE CONTROLLING METHOD THEREOF - Provided are an analog digital converting device and a reference voltage controlling method thereof. The analog digital converting device includes: a first reference voltage generating circuit generating a first reference voltage; a second reference voltage generating circuit generating a second reference voltage; a first sub analog digital converter receiving an analog input signal and converting the analog input signal into a first digital signal by using the first reference voltage; an amplifier converting the first digital signal into a voltage corresponding to the first digital signal by using the first reference voltage and amplifying a difference between a voltage level of the analog input signal and a voltage level corresponding to the first digital signal to output a residual signal; and a second sub analog digital converter receiving the residual signal and converting the residual signal into a second digital signal by using the second reference voltage. | 03-15-2012 |
20120068866 | COMPENSATION OF CLOCK JITTER IN ANALOG-DIGITAL CONVERTER APPLICATIONS - Processes and systems for use in reducing clock jitter-induced error, obtain a first sample during each cycle of a periodic analog reference signal. The sample includes an error resulting at least in part from jitter-induced timing error of the clock signal. For each respective cycle, a second sample of a discrete-time analog representation of the periodic analog reference signal is also obtained. The second sample is substantially unsusceptible to jitter-induced timing error of the clock signal. Each of the first and second samples corresponds to the same respective cycle of the clock signal. For each cycle, a respective difference between each of the first and second samples is determined. The difference is indicative of timing error of the respective cycle of the clock signal. The difference is converted to a digital representation that can be used to compensate for jitter-induced error. | 03-22-2012 |
20120075129 | CALIBRATION OF IMPAIRMENTS IN A MULTICHANNEL TIME-INTERLEAVED ADC - Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). A number, M, of clock signals drive a corresponding number of main ADC elements with a selected plurality of different clock phases. Each of the ADCs has at least one of an offset correction input, a gain correction input, or a phase correction input. The M digital values output by the ADCs are interleaved to form a digital representation of the input signal. Also provided is a reference ADC that outputs reference digital values in response to at least one of the M clock signals at a time. The output of the reference ADC is compared and/or combined with the output from a selected one of the main ADCs to provide an estimate of offset, gain or phase. The error is accumulated to determine a corresponding correction of offset, gain or phase which is then fed back to the respective input of the corresponding main ADC. | 03-29-2012 |
20120086588 | SYSTEM AND A METHOD OF CORRECTING BASELINE WANDER - A system and method of correcting baseline wander (BLW) are disclosed. An analog-to-digital converter (ADC) converts an analog input to a digital output, and a slicer maps the digital output to one of a plurality of predefined values. A BLW correction unit generates a BLW correction value according to a difference between an input and an output of the slicer. A correction controller generates a fine correction value and a coarse correction value according to the BLW correction value. Specifically, the fine correction value is used to correct the digital output of the ADC, and the coarse correction value is used to correct the analog input of the ADC. | 04-12-2012 |
20120092198 | SYSTEM AND METHOD OF ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter system that includes a pipeline including N successively-cascaded signal converters, each converting, according to a first clock signal, a respective portion of an input signal of the pipeline into digital codes, a code aligner for receiving and aligning the digital codes from the signal converters in the pipeline into a digital output of the system, an error extractor coupled to an amplifier input node of a selected one signal converter via a first switch for extracting an error signal, and a load system coupled to the amplifier input node of the selected one signal converter via a second switch. | 04-19-2012 |
20120098683 | ANALOG-TO-DIGITAL CONVERSION APPARATUS AND OFFSET VOLTAGE CORRECTION METHOD - An analog-to-digital conversion apparatus has a plurality of comparators configured to compare each of a plurality of different reference voltages and an input signal voltage in a parallel manner, a switch unit configured to switch the input signal voltage to a voltage corresponding to an analog input signal voltage or one of the plurality of reference voltages, an encoder configured to convert comparison results of the plurality of comparators into digital signals, and a digital assist circuit configured to control the switch unit so that the input signal voltage has a potential corresponding to the reference voltage in the comparator being the correction target among the plurality of comparators, to generate correction data for correcting the offset voltage generated in the comparator being the correction target based on the digital signal and to output it to the comparator being the correction target. | 04-26-2012 |
20120098684 | Device and Method for Processing an Analogue Signal - Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset. | 04-26-2012 |
20120098685 | VOLTAGE CONVERTER - An analog-to-digital converter including a comparator, a control module, a voltage adjusting module, and an evaluating module is provided. The comparator compares an analog input voltage with a feedback voltage and generates a comparison result. Based on the comparison result, the control module generates a control signal. The voltage adjusting module increases or decreases the feedback voltage toward the analog input voltage according to the control signal. The voltage increase amount and decrease amount provided by the voltage adjusting module are corresponding to a first digital value and a second digital value, respectively. The evaluating module generates the first digital value and the second digital value based on the control signal. According to the first digital value and the second digital value, a digital signal corresponding to the analog input voltage is generated. | 04-26-2012 |
20120098686 | VOLTAGE CONVERTER - A voltage converter for converting an analog input signal into a digital signal is provided. The pulse width of the digital signal is relative to the voltage level of the analog input signal. The voltage converter includes a comparator and a feedback module. After comparing the analog input signal and an analog feedback signal, the comparator generates the digital signal. When the analog input signal is higher than the analog feedback signal, the digital signal has a first voltage level. When the analog input signal is lower than the analog feedback signal, the digital signal has a second voltage level, which is different from the first voltage level. Based on the digital signal, the feedback module adjusts the analog feedback signal toward the analog input signal. | 04-26-2012 |
20120112939 | PIPELINE AD CONVERTER AND METHOD OF CORRECTING OUTPUT FROM THE CONVERTER - A digital correction circuit calculates AD conversion errors EA and EA′ in AD conversion stages subsequent to a target stage of AD conversion. EA is an error between an AD conversion result when a digital output of the target stage is set to 0, and an AD conversion result when it is set to +1 in a state where a higher reference voltage is input to the target stage. EB is an error between an AD conversion result when the digital output is set to 0, and an AD conversion result when it is set to −1 in a state where a lower reference voltage is input to the target stage. The digital correction circuit adds a correcting value of the target stage to the digital output. The correcting value is −(EA+EB)/2 when the digital output is −1, −(EA−EB)/2 when it is 0, and +(EA+EB)/2 when it is +1. | 05-10-2012 |
20120119930 | Background Calibration Method For Fixed Gain Amplifiers - A method for calibrating a fixed gain amplifier configured as a front-end amplification stage of an analog-to-digital converter including sampling a calibration voltage with normal and inversed polarity and with the fixed gain amplifier bypassed and with the fixed gain amplifier connected. An actual gain value of the fixed gain amplifier is computed from offset corrected digital output codes generated from converting the calibration voltage. A gain correction value for the fixed gain amplifier can then be computed based on the ratio of the actual gain to the ideal gain. In another embodiment, a method for calibrating an analog-to-digital converter including a fixed gain amplifier, an input buffer and a modulator generates an offset correction value using normal and polarity inversed input samples. The offset correct value provides correction for at least offset errors in the fixed gain amplifier, the input buffer and the modulator. | 05-17-2012 |
20120127005 | FAST QUANTIZER APPARATUS AND METHOD - An apparatus and method for a fast quantizer comparator comprising three stages: a preamplifier stage, a regeneration latch stage, and a data latch stage. Time delay is reduced by changing the initial voltages of the regeneration latch outputs. The current source is provided at the tail of the comparator, enabling time delay optimization. When the PMOS equalization switch turns off, it makes the clock signal feedthrough and provides charge injection into the outputs. Because of these charges, the time delay of the comparator is variable. Only a very low current sets the output voltages because the resetting time is longer than the comparison time. | 05-24-2012 |
20120139765 | Processing System Compensating DC Offset and Gain Error - A processing system including a first processing module and a second processing module is disclosed. The first processing module transforms and amplifies a grounded signal to generate a first processed signal and transforms and amplifies a predetermined signal to generate a second processed signal. The second processing module transforms the first processed signal to a first digital code according to a first reference voltage group and transforms the second processed signal to a second digital code according to a second reference voltage group. The second processing module adjusts a third reference voltage group according to the first and the second digital codes, and during a normal mode, the second processing module generates a third digital code according to the adjusted third voltage group. | 06-07-2012 |
20120154187 | Error Correction in Thermometer Codes - A thermometer coded line is configured to convert a time interval to a digital code for subsequent processing in order to output a value representative of said time interval. A digital peak detector is coupled to receive output from the thermometer coded line, the detector operating for correction of an undesired code of said digital code in order to ensure a valid output of said value. A majority logic circuit is coupled between the thermometer coded line and the digital peak detector, the logic circuit operating for correction of undesired code of said digital code in order to ensure the valid output of said value. The detector functions to correct any undesired code not corrected by, or introduced by, the logic circuit. | 06-21-2012 |
20120161992 | INTEGRATED NON-LINEARITY (INL) AND DIFFERENTIAL NON-LINEARITY (DNL) CORRECTION TECHNIQUES FOR DIGITAL-TO-ANALOG CONVERTERS (DACS) - INL values are determined for sub-segments of a DAC adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the sub-segments of the DAC, and a second set of correction codes that can be used to ensure that all values of DNL>−1 (to ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2̂N possible digital input codes (that can be accepted by the DAC) to more than 2̂N possible digital output codes, to ensure that all values of DNL>−1. Such stored first and second sets are thereafter used when performing digital to analog conversions. | 06-28-2012 |
20120176258 | Calibration Circuit and Method for Calibrating Capacitive Compensation in Digital-to-Analog Converters - A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor. | 07-12-2012 |
20120176259 | FLASH ANALOG TO DIGITAL CONVERTER WITH METHOD AND SYSTEM FOR DYNAMIC CALIBRATION - A flash analog to digital converter and a method and system for dynamically calibrating the flash analog to digital converter. The analog to digital converter may include a track and hold circuit and a plurality of comparators. The analog to digital converter may also include an under-sampling circuit configured to convert a digitized reference signal into an under-sampled digitized reference signal with a frequency of the calibration frequency divided by a positive number M. The under-sampling circuit may be further configured to calibrate a subsequent signal based on the under-sampled digitized reference signal. | 07-12-2012 |
20120182166 | A/D CONVERSION CIRCUIT, INTEGRATED CIRCUIT DEVICE, ELECTRONIC APPARATUS - An A/D conversion circuit in which a control circuit that has a successive approximation register storing data updated by a successive approximation operation generates correction data for correcting non-linearity between an input analog signal and an output digital signal, and a comparison unit corrects the non-linearity based on the correction data. An A/D conversion circuit includes a comparison unit which performs comparison operation in successive approximation and a control circuit having a successive approximation register storing successive approximation data updated by the successive approximation. The control circuit outputs correction data for correcting non-linearity between an input signal and output data of the A/D conversion circuit to the comparison unit based on one or plural bits of the successive approximation data. The comparison unit corrects the non-linearity of the A/D conversion circuit based on the correction data. | 07-19-2012 |
20120188108 | High Speed, High Resolution, High Precision Voltage Source/AWG System for ATE - A method for compensating a linearity error of a dual digital-to-analog converter, including the steps of receiving a digital data signal which include a plurality of bits, the digital data signal indicating a voltage signal to be generated, the plurality of bits representing a set of consecutive bits being confined within a highest bit and a lowest bit, applying a high-bit-array to a first digital-to-analog converter, the high-bit-array being composed of a consecutive sub-set of the plurality of bits of the digital data signal, the sub-set including the highest bit of the digital data signal, using at least a part of a correction data of a look-up-table for manipulating at least a part of a low-bit-array, being composed of a consecutive sub-set of the plurality of bits of the digital data signal, where the sub-set includes the lowest bit of the digital data signal. | 07-26-2012 |
20120212358 | PIPELINED ADC INTER-STAGE ERROR CALIBRATION - An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error. | 08-23-2012 |
20120229314 | TEST APPARATUS AND TEST METHOD FOR A/D CONVERTER - A test apparatus configured to test an N-bit (N represents an integer) A/D converter is provided. A voltage generating unit outputs a 2 | 09-13-2012 |
20120235841 | DIGITAL CORRECTION TECHNIQUES FOR DATA CONVERTERS - A method and apparatus is disclosed to compensate for impairments within a data converter such that its output is a more accurate representation of its input. The data converter includes a main data converter, a reference data converter, and a correction module. The main data converter may be characterized as having the impairments. As a result, the output of the main data converter is not the most accurate representation of its input. The reference data converter is designed such that the impairments are not present. The correction module estimates the impairments present within the main data converter using its output and the reference data converter to generate corrections coefficients. The correction module adjusts the output of the main data converter using the corrections coefficients to improve the performance of the data converter. | 09-20-2012 |
20120242520 | A/D CONVERSION DEVICE AND COMPENSATION CONTROL METHOD FOR A/D CONVERSION DEVICE - An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×Mf+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC. | 09-27-2012 |
20120249350 | REFERENCE CURRENT COMPENSATION CIRCUIT FOR D/A CONVERTER - A D/A converter having reference node for receiving a reference voltage and together network having a network reference bus connected to the reference node by way of a first electrical connection. The converter network produces a series of reference outputs derived from the reference voltage in response to a digital input applied to the converter, with the converter network sinking a network reference current at the network reference bus which varies with the converter digital input. A reference current compensator circuit is included which provides a compensation current at the network reference bus having a magnitude which varies in response to at least a portion of the digital input, with the compensation current operating to reduce variations in current through the first electrical connection caused by changes in the digital input. | 10-04-2012 |
20120256773 | RESOLVER DIGITAL CONVERTER - This resolver digital converter 10 includes a band pass processing unit that is disposed between a conversion unit and a multiplication unit and passes only a signal of a predetermined band through processing performed with a period that is shorter than the sampling period of an analog-to-digital converter and corrects the gains of digital signals before being input to the multiplication unit by using gain correction values that are set based on the maximum value and the minimum value of each one of digital signals passing through the band pass processing unit. | 10-11-2012 |
20120274490 | MULTIPLIER-FREE ALGORITHMS FOR SAMPLE-TIME AND GAIN MISMATCH ERROR ESTIMATION IN A TWO-CHANNEL TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - Techniques for the estimation of sample-time and gain mismatch errors in a two-channel time interleaved analog to digital converter that are devoid of any multiplication operation. In a sample-time mismatch error evaluation, the signs and the absolute values from the two ADCs are used to provide an estimate of the sample-time mismatch error. In a gain error estimation algorithm, the absolute values of the outputs from the two ADCs are subtracted and accumulated. The errors can then be corrected, in a preferred embodiment, using suitable adaptive sample time and gain correction techniques. | 11-01-2012 |
20120274491 | GRADIENT-BASED APPROACH TO SAMPLE-TIME MISMATCH ERROR CALIBRATION IN A TWO-CHANNEL TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - Correcting phase error in a two-channel TIADC system in a manner that is independent of the Nyquist zone(s) occupied by the input signal. In the preferred approach this is done using the gradient of a phase error estimate. The gradient may be determined from a simplified expression of linear regression; the direction of the adaptation is then controlled by the sign of the gradient. The adaptive algorithm converges to the optimal value regardless of the Nyquist zone occupied by the input signal. | 11-01-2012 |
20120280844 | DIGITAL RECEIVER AND OPTICAL COMMUNICATION SYSTEM THAT USES SAME - A digital receiver includes: an analog-to-digital (AD) converter ( | 11-08-2012 |
20120293347 | COMPENSATED CURRENT CELL TO SCALE SWITCHING GLITCHES IN DIGITAL TO ANALOG CONVERTORS - Compensated current cell to scale switching glitches in digital to analog convertors. A compensated current cell is disclosed that includes first and second switching transistors configured to switch an input current between first and second outputs based on first and second input signals, respectively, a first compensation transistor connected to the first input signal to provide a first compensation current that is connected to the second output, and a second compensation transistor connected to the second input signal to provide a second compensation current that is connected to the first output, the first and second compensation transistors having source terminals that are connected together. In another aspect, switching glitches are scaled based on a size difference between the switching transistors and the compensation transistors. | 11-22-2012 |
20120293348 | System and Method For Digitally Correcting Mismatches In Multipath ADCs - A system and method of reducing the effects of nonidealities of ADCs in multipath converters is disclosed. The system and method employs a variety of measure and correction blocks to determine statistical properties of the output stream of the multipath converter and to apply corrections to the operation of the subconverters of the multipath converter based upon differences in the measured statistics and expected target values, either explicit or implicit, for those statistics. A variety of examples of possible measure and configuration blocks are disclosed, as is the cascading of the measure and correction blocks to correct multiple errors in the output of the multipath converter. Feedforward (purely digital) and feedback (analog and digital) solutions are both disclosed. | 11-22-2012 |
20120306672 | ANALOG-TO-DIGITAL CONVERSION APPARATUS AND SIGNAL PROCESSING SYSTEM - An analog-to-digital conversion apparatus includes: a first analog-to-digital converter and a second analog-to-digital converter that are configured to convert an input analog signal into a digital signal; a difference imparting part configured to provide a difference of at least a fixed signal α between input analog signals to the first and second analog-to-digital converters, to input the input analog signals thereto; a first non-linear compensation part and a second non-linear compensation part that are configured to compensate non-linear distortions of a first output signal and a second output signal depending on the control variable signal to be supplied; and a non-linear detection part configured to estimate how much the non-linear distortions are compensated by the first and second non-linear compensation parts depending on a first signal by the first non-linear compensation part and a second signal by the second non-linear compensation part. | 12-06-2012 |
20120306673 | ANALOG-TO-DIGITAL CONVERSION APPARATUS AND SIGNAL PROCESSING SYSTEM - An analog-to-digital conversion apparatus includes: a first analog-to-digital converter configured to convert an input analog signal into a digital signal; a second analog-to-digital converter configured to convert an analog signal generated by multiplying the input analog signal by α times with a coefficient α into a digital signal; a first non-linear compensation part configured to compensate a non-linear distortion of a first output signal of the first analog-to-digital converter; a second non-linear compensation part configured to compensate a non-linear distortion of a second output signal of the second analog-to-digital converter; and a non-linear detection part configured to estimate how much the non-linear distortions of the first and second analog-to-digital converters are compensated by the first and second non-linear compensation parts depending on first and second signals by the first and second non-linear compensation parts. | 12-06-2012 |
20120319879 | METHOD FOR MODIFYING THE LMS ALGORITHM TO REDUCE THE EFFECT OF CORRELATED PERTURBATIONS - A process allows for the modification of the least-means-square (LMS) algorithm to remove perturbations associated with measured signals in an analog-to-digital converter (ADC). The process includes measuring the perturbations and determining a coefficient associated with the perturbations. The LMS algorithm is modified in accordance with whether a digital or an analog correction of the inter-stage error of a residue amplifier on the ADC is to be made. | 12-20-2012 |
20120326901 | System and Method for Analog to Digital (A/D) Conversion - In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels. | 12-27-2012 |
20120326902 | BACKGROUND CALIBRATION OF OFFSETS IN INTERLEAVED ANALOG TO DIGITAL CONVERTERS - A multi-channel time interleaved ADC (TIADC) provides for offset estimation and correction. The correction is accomplished through analog adjustment of offset rather than by digital correction of their outputs. In certain aspects, polarity reversal circuits may be used to further improve performance. | 12-27-2012 |
20130027233 | ANALOG DIGITAL CONVERTER - An ADC which samples an analog input signal at a sampling frequency and converts the analog input signal to a digital output signal, has N analog digital converter (ADC) channels which convert the analog input signal into the digital output signal by time interleaving, a channel synthesizer which synthesizes channel digital signals output respectively by the ADC channels to generate the digital output signal, an adaptive filter provided at at least one output of the ADC channels, and a correction circuit which generates a coefficient of the adaptive filter in accordance with the digital output signal. The correction circuit calculates a DC component of an image signal component, from among an analog input signal component and the image signal component corresponding to error, both being included in the digital output signal, and calculates the coefficient such that the DC component is suppressed on the basis of the DC component. | 01-31-2013 |
20130027234 | TIME-INTERLEAVED A/D CONVERTER APPARATUS - A time-interleaved A/D converter apparatus has a primary signal A/D converter circuit group that is time-interleaved with a combination of N A/D converter circuits, a correction signal generation part operable to receive the input analog signal and a 1/m-sampling signal having a speed that is 1/m of a rate of the sampling signal inputted to the primary signal A/D converter circuit group, to extract a dispersion of a transmission line that is immanent in the input analog signal, and to output the dispersion as a dispersion compensation control signal used for digital signal compensation, and a signal processing part operable to convert the N digital signals into one digital signal based upon the dispersion compensation control signal and to compensate a dispersion included in the converted digital signal. | 01-31-2013 |
20130044016 | DISTORTION CORRECTING DEVICE - There is provided a distortion correcting device in which a first A/D converter A/D converts a first input signal to obtain a first converted signal, a second A/D converter A/D converts a second input signal to obtain a second converted signal wherein the second input signal is a signal obtained by reducing an amplitude of the first input signal, or the first input signal is a signal obtained by increasing an amplitude of the second input signal, the exponentiator obtains an exponential signal by raising the second converted signal to an n-th power (“n” is an integer of 2 or more), a adaptive correlation controller carries out adaptive correlation control based on the exponential signal and the second converted signal to generate a distortion signal that is an n-th power component contained in the exponential signal, and a distortion remover removes the distortion signal from the first converted signal. | 02-21-2013 |
20130063289 | CORRECTING FOR NON-LINEARITIES IN A CONTINUOUS-TIME SIGMA-DELTA MODULATOR - In higher order sigma-delta modulators (SDMs), there are oftentimes errors introduced by the digital-to-analog (DAC) switches. Namely, parasitic capacitances associated with switches can introduce second harmonic spurs. Here, however, compensation circuits and buffers are provided. The buffers bias the switches in saturation, and the compensation circuits provide a “ground boost” for the buffers. The combination of the buffer and compensation circuit reduces the second harmonic spur, while also improving the Signal-to-Noise Ratio (SNR) and Signal-to-Noise-plus-Distortion Ratio (SNDR). | 03-14-2013 |
20130069808 | ANALOG FRONTEND FOR CCD/CIS SENSOR - A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N−3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage. | 03-21-2013 |
20130076544 | ANALOGUE TO DIGITAL CONVERTER AND SIGNAL PROCESSING SYSTEM - According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals. | 03-28-2013 |
20130076545 | TIME ERROR ESTIMATING DEVICE, ERROR CORRECTION DEVICE AND A/D CONVERTER - A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value. | 03-28-2013 |
20130082853 | DIGITAL TO ANALOG CONVERTER - A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate. | 04-04-2013 |
20130141261 | TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER BANDWIDTH MATCHING - A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level. | 06-06-2013 |
20130141262 | ANALOG-TO-DIGITAL CONVERSION STAGE AND PHASE SYNCHRONIZATION METHOD FOR DIGITIZING TWO OR MORE ANALOG SIGNALS - An analog-to-digital conversion stage ( | 06-06-2013 |
20130154860 | USE OF LOGIC CIRCUIT EMBEDDED INTO COMPARATOR FOR FOREGROUND OFFSET CANCELLATION - A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC. | 06-20-2013 |
20130176153 | Method and System for Broadband Analog to Digital Converter Technology - Nonlinearity correction in a device that performs analog-to-digital conversion on received analog signals, may be calibrated by generating correction-parameters estimation which when applied to the total spectral content reduces distortion resulting from said nonlinearity in originally-unoccupied spectral regions. Digital signals generated based on sampling of the received analog signals may then be corrected, to remove nonlinearity related distortion, based on the estimated correction-parameters. The nonlinearity calibration may be performed during reception and handling of said analog signals. The correction-parameters may be generated based on signals located in particular spectral regions, such as the originally-unoccupied spectral regions. These signals may be injected within the device, into the particular spectral regions, and the signal may have known characteristics to enable estimating the required correction. | 07-11-2013 |
20130176154 | OFF-LINE GAIN CALIBRATION IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADC blocks each including: at least one ADC unit configured to convert an analog input to a digital output; and a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit. | 07-11-2013 |
20130187800 | METHOD AND APPARATUS OF ESTIMATING/CALIBRATING TDC MISMATCH - A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step. | 07-25-2013 |
20130187801 | GAIN AND DITHER CAPACITOR CALIBRATION IN PIPELINE ANALOG-TO-DIGITAL CONVERTER STAGES - A switching scheme is used during a calibration mode for determining calibration coefficients of each calibrated stage of a pipeline analog-to-digital converter (ADC). A calibrated stage of the pipeline ADC includes an amplifier for amplifying a residue voltage of the stage and a sampling capacitor comprising a plurality of sub-capacitors. The plurality of sub-capacitors have a first terminal connected to an input of amplifier and a second terminal connected to one or more switches that selectively couple the second terminal to the input terminal of the stage, a first reference voltage or a second reference voltage lower than the first reference voltage. During foreground calibration, a number of measurements are taken at an output of the amplifier to determine the calibration coefficient of the calibrated stage. | 07-25-2013 |
20130187802 | PIPELINE ANALOG-TO-DIGITAL CONVERTER STAGES WITH IMPROVED TRANSFER FUNCTION - A connection scheme is used to selectively connect a dither capacitor included in a calibrated stage of a pipeline analog-to-digital converter (ADC) in a way that reduces the output voltage swing of the stage. A first terminal of the dither capacitor is coupled to an input of the amplifier. A second terminal of the dither capacitor is coupled to either a first or second reference voltage dependent on a bit value in a Pseudo-Random Binary Sequence (PRBS) if a voltage received by the stage is within a first voltage range. If the stage received voltage is within a second range, the second terminal is coupled to the first reference voltage independent of the PRBS. If the stage received voltage is within a third range, the second terminal is coupled to the second reference voltage independent of the PRBS. | 07-25-2013 |
20130214945 | MULTI-BIT DELTA-SIGMA TIME DIGITIZER CIRCUIT AND CALIBRATION METHOD THEREOF - According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured. | 08-22-2013 |
20130214946 | A/D Converter and Method for Calibrating the Same - An ADC includes sampling means for sampling an input voltage signal, comparator(s) for receiving the sampled signal, and a DAC including circuitry for generating a search signal approximating the input signal and a calibration signal. The search signal and the calibration signal are to be applied to a comparator. The ADC also includes a search logic block for receiving a comparator output signal, for providing input to the DAC for generating the search signal, and for producing a digital output signal. Further, the ADC includes a calibration logic block for producing a control signal to control the circuitry of the DAC and including processing means for observing the output signal, for comparing the output signal with a desired output, and for compensating analogue non-idealities of the ADC. The DAC circuitry is adapted for generating the calibration signal in accordance with the control signal and with the sampled input signal. | 08-22-2013 |
20130222161 | Distortion and aliasing reduction for digital to analog conversion - Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion. | 08-29-2013 |
20130241753 | ANALOG DIGITAL CONVERTER (ADC) AND CORRECTION CIRCUIT AND CORRECTION METHOD THEREFOR - An ADC has ADC channels converting an analog input signal into an digital output signal in a time interleave manner; a channel combiner combining channel digital signals respectively output by the ADC channels and generate the digital output signal; an adaptive filter provided at one of the plurality of ADC channels; and a correction circuit detecting a skew error in the digital output signal, generating a coefficient of the adaptive filter according to the skew error for setting it in the filter. According to the skew error, in a first setting, the correction circuit sets the coefficient such that the adaptive filter phase-shifts to one direction a phase of the channel digital signal and, in a second setting, the correction circuit sets the coefficient such that the adaptive filter phase-shifts to an opposite direction and sets a coefficient with which the skew error is suppressed to a desired level. | 09-19-2013 |
20130241754 | DIGITAL-TO-ANALOG CONVERTER WITH NON-UNIFORM RESOLUTION - A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch. | 09-19-2013 |
20130249719 | SCHEME FOR BALANCING SKEW BETWEEN LANES OF HIGH-SPEED SERIAL DIGITAL INTERFACE - A device that supports communication over parallel serial lanes may include an analog circuit domain, a digital circuit domain, a buffer between the analog domain and the digital domain, and an alignment circuit. The buffer may receive data from the digital domain according to a write clock and send out the received data to the analog domain according to a read clock. The alignment circuit may generate control signals to initiate reading from the buffer when the read clock and write clocks are aligned. In one embodiment, the device may be an analog-to-digital converter (ADC) integrated circuit (IC) chip and the buffer may be a FIFO. | 09-26-2013 |
20130249720 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing. | 09-26-2013 |
20130257635 | DIGITAL CORRECTION CIRCUIT FOR A PIPELINED ANALOG-TO-DIGITAL CONVERTER - A digital correction circuit for a pipelined analog-to-digital converter (ADC) is disclosed. Compared to the conventional digital correction circuit which uses adders to perform operations in ADC digital correction part and hence needs a rather long operation time, the digital correction circuit of this invention can reduce the time needed in operations in the finial digital correction circuits and thus can optimize operation time, by allocating the operations to a plurality of pipeline stages of second sub-circuits configured to synchronize digital codes, each of which can perform part of the operations only with NAND gates, NOR gates, phase inverters and D-type flip-flops, without needing to use adders. | 10-03-2013 |
20130314261 | Digital Correction Techniques for Data Converters - A method and apparatus is disclosed to compensate for impairments within a data converter such that its output is a more accurate representation of its input. The data converter includes a main data converter, a reference data converter, and a correction module. The main data converter may be characterized as having the impairments. As a result, the output of the main data converter is not the most accurate representation of its input. The reference data converter is designed such that the impairments are not present. The correction module estimates the impairments present within the main data converter using its output and the reference data converter to generate corrections coefficients. The correction module adjusts the output of the main data converter using the corrections coefficients to improve the performance of the data converter. | 11-28-2013 |
20130321187 | ANALOG-TO-DIGITAL CONVERTER AND ELECTRONIC APPARATUS - An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level. | 12-05-2013 |
20140002284 | Compensation for Lane Imbalance in a Multi-Lane Analog-To-Digital Converter (ADC) | 01-02-2014 |
20140022101 | TIME INTERLEAVED ANALOG TO DIGITAL CONVERTER MISMATCH CORRECTION - A machine-implemented method can include receiving a common input signal over M parallel time-interleaved (TI) analog to digital converter (ADC) channels, determining a multiple-input, multiple-output finite impulse response (FIR) filter structure for correcting bandwidth mismatches between the M parallel TIADC channels, and providing a common output signal comprising TI data corresponding to the M parallel TIADC corrected channels. | 01-23-2014 |
20140028482 | High Bandwidth Oscilloscope - A method for improving bandwidth of an oscilloscope involves, in preferred embodiments, the use of frequency up-conversion and down-conversion techniques. In an illustrative embodiment the technique involves separating an input signal into a high frequency content and a low frequency content, down-converting the high frequency content in the analog domain so that it may be processed by the oscilloscope's analog front end, digitizing the low frequency content and the down-converted high frequency content, and forming a digital representation of the received analog signal from the digitized low frequency content and high frequency content. | 01-30-2014 |
20140049414 | SYSTEMS AND METHODS FOR CORRECTING AN OFFSET AT AN OUTPUT OF A DIGITAL TO ANALOG CONVERTER - A system including a converter, a buffer, and an offset adjust circuit. The converter is configured to provide, based on a digital input signal, a first output current. The buffer is configured to provide, based on the first output current, a second output current to an output pin. The offset adjust circuit is in communication with the first output current and is configured to, based on the second current at the output pin, adjust the first output current to compensate for a current offset at the output pin. | 02-20-2014 |
20140062738 | SUCCESSIVE EQUALIZER FOR ANALOG-TO-DIGITAL CONVERTER (ADC) ERROR CORRECTION - Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages. | 03-06-2014 |
20140062739 | BUFFER OFFSET MODULATION - One or more techniques for buffer offset modulation or buffer offset cancelling are provided herein. In an embodiment, an output for a sigma-delta analog digital converter (ADC) is provided using an output of a first chop-able buffer (FB) and an output of a second chop-able buffer (SB). For example, the output of the FB is associated with a first offset, the output of the SB is associated with a second offset, and the output of the ADC includes an ADC offset associated with the first offset and the second offset. In an embodiment, buffer offset modulation is provided by modulating the ADC offset using an offset rotation. In an example, the offset rotation is based at least in part on a reference clock and the output of the ADC. The buffer offset modulation mitigates the first offset or the second offset, where such offsets are generally undesired. | 03-06-2014 |
20140062740 | ANALOG TO DIGITAL CONVERTER WITH NOISE REDUCING FEEDBACK PATH - An analog to digital converter including a low pass filter element, a quantizer, and a digital to analog converter provide in a feedback path. The low pass filter element is configured to filter an analog input signal. The quantizer is configured to receive an analog output signal that is based on the filtered analog input signal and convert the analog output signal to a digital output signal. The digital to analog converter is configured to generate an analog feedback signal based on the digital output signal and selectively inject or absorb current associated with the feedback path to reduce noise associated with the digital to analog converter. The analog feedback signal is combined with the analog input signal at an input of the low pass filter element. | 03-06-2014 |
20140070969 | DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER WITH ERROR SUPPRESSION - A delta-sigma analog-to-digital converter (ΔΣ ADC) has a delta-sigma modulator, a decimation filter and an error suppression circuit. The delta-sigma modulator receives an analog input, and converts the analog input into a first digital output. The decimation filter is coupled to the delta-sigma modulator, and generates a second digital output according to the first digital output. The error suppression circuit is coupled to the decimation filter, and receives an error input and injects an error output into the second digital output according to the error input. | 03-13-2014 |
20140077980 | ARRANGEMENT FOR READING OUT AN ANALOGUE VOLTAGE SIGNAL WITH SELF-CALIBRATION - An arrangement for reading out an analog voltage input signal includes an input applying the input signal thereto, and a reference unit generating an analog reference voltage. To perform online self-calibration, the arrangement includes a superposition unit generating a combined analog signal by superimposing the analog reference voltage onto the input signal, a converting unit converting the combined analog signal into a one-bit serial data stream at a conversion sampling rate, and a decomposition unit, which includes at least two digital filters configured to generate from the serial data stream two corresponding digital signals at different data rates, which can be less than the conversion sampling rate. Two data processing units calculate from the corresponding digital signal a digital input voltage representing the input signal and a digital reference voltage representing the analog reference voltage or a disturbance voltage signal representing parasitic voltage components introduced by the superposition unit, respectively. | 03-20-2014 |
20140077981 | METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY - Methods and systems are provided for calibrating nonlinearity correction during analog-to-digital conversions on received analog signals. Correction-parameters may be estimated, such as to reduce, when applied to total spectral content, distortion resulting from the nonlinearity in originally-unoccupied spectral regions. Digital signals generated based on sampling of the received analog signals may then be corrected, to remove nonlinearity related distortion, based on the estimated correction-parameters. The nonlinearity correction calibration may be performed during reception and handling of the analog signals. The correction-parameters may be generated based on signals located in particular spectral regions, such as the originally-unoccupied spectral regions. These signals may be injected within the device, into the particular spectral regions, and the signal may have known characteristics to enable estimating the required correction. | 03-20-2014 |
20140091955 | SYSTEM, APPARATUS AND METHOD TO IMPROVE ANALOG-TO-DIGITAL CONVERTER OUTPUT - According to various embodiments, a system, an apparatus and a method are presented that relate to determining and correcting signal imbalances between output samples of an analog-to-digital (A-D) converter array (that may be implemented as part of a wideband ADC). A statistic module and correction module are associated with the A-D converter array. The statistic module is configured to receive digital samples from the plurality of A-D converters, and generate a statistical sample value for each A-D converter using a set of digital samples received therefrom. The correction module is configured to, for at least one of the plurality of A-D converters, determine an offset value by comparing the statistical sample value for the at least one of the plurality of A-D converters with a reference value, and apply the offset value to a digital sample from that at least one A-D converter to generate a corrected digital sample. | 04-03-2014 |
20140111361 | APPARATUS, METHOD AND SYSTEM FOR CANCELLING AN INPUT-REFERRED OFFSET IN A PIPELINE ADC - An apparatus, method and system for offset compensation in a pipeline analog-to-digital converter. A group of capacitors includes one or more sampling capacitors and one or more feedback capacitors, wherein an input to the pipeline analog-to-digital converter circuit is connected to group of capacitors. An amplifier includes a non-inverting input terminal connected to a ground and an inverting input connected to the group of capacitors. The sampling and feedback capacitors are both partitioned in the same ratio to form partitioned capacitors such that a smaller of the partitioned capacitors is employed for offset compensation with respect to the pipeline analog-to-digital converter. | 04-24-2014 |
20140167989 | CALIBRATION OF INTERLEAVING ERRORS IN A MULTI-LANE ANALOG-TO-DIGITAL CONVERTER - A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples. | 06-19-2014 |
20140167990 | Accurate and Cost Efficient Linear Hall Sensor with Digital Output - One embodiment of the present invention relates to a magnetic sensor circuit having a magnetic field sensor device configured to generate a digital signal proportional to an applied magnetic field. An analog-to-digital converter converts the analog signal to a digital signal that is provided to a digital signal processing unit, which is configured to digitally track the analog output signal. The digital tracking unit comprises a delay removal circuitry configured to generate a plurality of digital signal component corresponding to a chopping phase. A non-delayed offset compensated digital output signal may be generated within the chopping phase by mathematically operating upon (e.g., adding or subtracting) the plurality of digital signal components, generated by the delay removal circuitry. | 06-19-2014 |
20140191889 | ANALOG-DIGITAL CONVERSION CIRCUIT AND METHOD - An analog-digital conversion circuit includes a comparator that receives an analog input signal. A controller generates an N1-bit first signal and an N2B-bit second signal in accordance with an output signal from the comparator. A first digital-analog converter generates a first reference signal from the first signal. A second digital-analog converter generates a second reference signal from the second signal. A correction circuit corrects the first and second signals to generate a digital output signal. The N2B-bit second signal is acquired by adding a Kbit correction signal to an N2A-bit signal. The controller sequentially sets bit values of the first signal and bit values of the second signal in accordance with the output signal of the comparator. The correction circuit generates the (N1+N2A)-bit digital output signal based on a sum of a value acquired by multiplying the N1-bit first signal by 2̂N2A and a value of the N2B-bit second signal. | 07-10-2014 |
20140218222 | AUTOMATIC GAIN CONTROL SYSTEM FOR AN ANALOG TO DIGITAL CONVERTER - Methods and circuits for controlling an automatic gain control (AGC) circuit wherein the AGC circuit is used to adjust the gain of a signal input to an analog to digital converter. The method includes obtaining a plurality of samples from the output of the analog to digital converter and determining whether the amplitude of each sample is greater than a threshold amplitude value. If the amplitude of a sample is greater than the threshold amplitude value then a counter value is incremented. The target average amplitude of the automatic gain control circuit is then periodically adjusted based on the counter value. | 08-07-2014 |
20140232575 | Method and Device for use with Analog to Digital Converter - According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M−1 trains involves respectively M−1 second signals gleaned from the derived signal and the suite of M−1 shift coefficients. | 08-21-2014 |
20140232576 | METHOD AND APPARATUS FOR CALIBRATING DIGITAL BACKGROUND THROUGH CAPACITOR DIVISION AND SWAPPING FOR REDUCING CAPACITOR MISMATCH EFFECT OF ANALOG-TO-DIGITAL CONVERTER - A high-quality Analog to Digital Converter (ADC) is used to calibrate a difference attributable to a capacitor mismatch in a Digital to Analog Converter (DAC). The present invention is advantageous in that it can fabricate a low-power high-resolution ADC by calibrating an error attributable to a capacitor mismatch through a digital background calibration apparatus and method using a Successive Approximation Register (SAR). | 08-21-2014 |
20140232577 | ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD - An analog-to-digital converter according to the present invention includes first and second analog-to-digital conversion cells ( | 08-21-2014 |
20140240151 | ANALOG-TO-DIGITAL CONVERSION DEVICE - An analog-to-digital conversion device includes: an analog-to-digital converter that receives an analog voltage and converts the analog voltage into a digital value to output the converted digital value; and an offset correction unit that arithmetically operates an offset correction value based on a first digital value and a second digital value, the first digital value being to be output from the analog-to-digital converter by the analog-to-digital converter receiving a first analog voltage, the second digital value being to be output from the analog-to-digital converter by the analog-to-digital converter receiving a second analog voltage, the second analog voltage having a voltage value different from that of the first analog voltage, in which after the arithmetic operation of the offset correction value, the analog-to-digital converter outputs a digital value obtained by subtracting the offset correction value from the converted digital value. | 08-28-2014 |
20140253350 | DIGITAL/ANALOG CONVERTER CIRCUIT - The digital/analog converter circuit includes a digital/analog converting unit that receives a digital signal and outputs an output current to an output terminal in response to the digital signal. The digital/analog converter circuit includes an error current detecting unit that outputs a detection signal to the digital/analog converting unit, the detection signal correcting the output current. | 09-11-2014 |
20140253351 | Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) Attenuation Capacitor Calibration Method and Apparatus - A fixed capacitor is coupled between a top plate of an attenuation capacitor and a variable voltage reference. The error in the attenuation capacitor may be calibrated out with the variable voltage reference and the fixed correction capacitor. The variable voltage reference varies the charge on the attenuation capacitor and thereby compensates for error(s) therein. A calibration digital-to-analog converter may be used in conjunction with or substituted for the variable voltage reference, and may be programmed for different charge compensation values from the SAR logic during an iterative SAR DAC capacitive switching process. | 09-11-2014 |
20140253352 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period. | 09-11-2014 |
20140266822 | Digital-To-Time Converter and Calibration of Digital-To-Time Converter - A digital-to-time converter (DTC) comprises a gate controller configured to generate a gate enable signal based on first and second digital values so that the gate enable signal has a first enable period and a second enable period for each pair of a first digital value and a second digital value. A gate conditionally passes a main clock signal to a gate output in response to the gate enable signal, the gate thus providing a gated signal at a gate output. A frequency divider generates a frequency divided signal as the output signal of the digital-to-time converter based on the gated signal. The DTC may be calibrated by a time-to-digital converter connected between an input for the main clock signal and an output of a delay element of the DTC. | 09-18-2014 |
20140266823 | SYSTEMS AND METHODS FOR ESTIMATION OF OFFSET AND GAIN ERRORS IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - The present disclosure relates to the field of background estimation in a time-interleaved analog-to-digital converter (ADC). More specifically, the present disclosure relates to systems and methods for background estimation of offset and gain errors in a time-interleaved ADC based on sample count. The error estimation unit of the time-interleaved ADC system includes a counting unit, a subtractor and an integrator. The method for estimating an offset error in a time-interleaved ADC includes determining signs of the signals and outputting corresponding values by the counting unit. The values are further compared and integrated to estimate the offset error. The method for estimating a gain error in a time-interleaved ADC includes determining the absolute values of the signals and comparing the absolute values with a predetermined threshold value. The comparison results are further integrated to estimate the gain error. | 09-18-2014 |
20140292550 | ANALOG-TO-DIGITAL CONVERSION CIRCUIT, ANALOG-TO-DIGITAL CONVERSION METHOD, AND IMAGE SENSOR - An analog-to-digital conversion circuit includes an analog-to-digital conversion unit configured to analog-to-digital convert an input voltage and generate a digital signal, a resolution control unit configured to: set a resolution of the analog-to-digital conversion unit to N (N is the natural number) bits, in a case where the input voltage is smaller than a first voltage, and set the resolution of the analog-to-digital conversion unit to N−M (1≦M10-02-2014 | |
20140313065 | CLOCK SIGNAL ERROR CORRECTION IN A DIGITAL-TO-ANALOG CONVERTER - In an example, there is disclosed herein a digital-to-analog converter (DAC) including a correction circuit for a clock, including a differential clock. Error correction may take place within the DAC core, by means of replica cells that are substantially similar to conversion cells. Rather than contributing their output to the converted signal, the replica cells may be configured to provide a feedback signal to a clock receiver with information for correcting the clock signal. The feedback signal may be operable to correct errors, for example, in duty cycle and crosspoint, as measured at the DAC core. | 10-23-2014 |
20140354457 | SIGNAL PROCESSOR - An aspect of one embodiment, there is provided a signal processor includes an AD-convertor outputting a conversion result and a conversion end flag, a second comparator configured to compare signal levels, a channel selection signal generation unit to select an input channel to input the AD-convertor, an direction identification flag generation unit to generate an direction identification flag, an edge signal generation unit to generate rising edges and lowering edges, an up-down counter to subject to be up or down on a count value in an output of each of edge signals, and an arithmetic processing unit to interlink the count value of the up-down counter and the conversion result of the AD-convertor to generate output data, wherein the arithmetic processing unit interpolates the count value of the up-down counter in the interlinking by using a correction value corresponding to a value of the direction identification flag in a period between an output of the edge signal and an output of the conversion end flag. | 12-04-2014 |
20140361912 | ANALOG-TO-DIGITAL CONVERTER CIRCUIT, INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND METHOD THEREFOR - An automatic gain control circuit includes an input gain stage for receiving and amplifying an analog input signal; an analog-to-digital converter for receiving the amplified analog input signal and providing a digital output signal; and an overload management module. The overload management module is arranged to receive the digital output signal; determine therefrom whether the received, amplified analog input signal exceeds an operating range of the analog-to-digital converter; and provide a first control signal to the input gain stage to adjust a gain of the input gain stage in response thereto. | 12-11-2014 |
20140368364 | METHOD AND APPARATUS FOR ESTIMATING SAMPLING DELAY ERROR BETWEEN FIRST AND SECOND ANALOG-TO-DIGITAL CONVERTERS OF TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A method for estimating a sampling delay error between a first analog-to-digital converter (ADC) and a second ADC in a time-interleaved ADC includes: receiving a first digital output signal and a second digital output signal generated from the first ADC and the second ADC based on a same analog input signal, respectively; determining a delay amount according to a predetermined sampling delay between the first ADC and the second ADC and a delay adjusting value, and applying the delay amount delay to the second digital output signal to generate a delayed digital output signal, wherein the delay adjusting value Td is used to estimate the sampling delay error Te; calculating a difference between the first digital output signal and the delayed digital output signal; and feeding back the difference for adjusting the delay adjusting value Td according to the difference. | 12-18-2014 |
20140375486 | TIME-TO-DIGITAL CONVERTER AND CONTROL METHOD - A first switching unit configured to switch a first state for inputting a first clock signal input from a first input terminal, and a second state for inputting an output signal of a second delay element, to a first delay element. A second switching unit configured to switch a first state for inputting a second clock signal input from a second input terminal, and a second state for inputting an output signal of a first delay element, to a second delay element. After the two clock signals are respectively taken in the first delay elements and the second delay elements by putting the first and second switching units into the first state, the control unit puts the first and second switching units into the second state. An output unit outputs a phase difference obtained by decoding values stored in FFs in the second state. | 12-25-2014 |
20140375487 | MDAC with differential current cancellation - Various embodiments of the invention provide for cancellation of a residue amplifier output charging current at the reference voltage source of the reference buffer thereby preventing the charging current from altering the effective reference voltage of a reference buffer. In certain embodiments, current cancellation is accomplished by subtracting a current of the same magnitude. | 12-25-2014 |
20150015427 | SIGNAL CONVERSION METHOD, SIGNAL TRANSMISSION METHOD, SIGNAL CONVERSION DEVICE, AND TRANSMITTER - A signal conversion method including converting an input signal into a 1-bit pulse train representing an analog signal is provided. The 1-bit pulse train has a pulse rising waveform f | 01-15-2015 |
20150022384 | System Clock Jitter Correction - A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal. | 01-22-2015 |
20150042496 | METHODS AND DEVICES FOR ANALOG-TO-DIGITAL CONVERSION - Analog-to-digital converter arrangements and corresponding methods are provided, wherein a reduction signal is subtracted from an analog input signal if a signal level of the input signal exceeds a threshold value. | 02-12-2015 |
20150048959 | LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS) - Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC. | 02-19-2015 |
20150054665 | STORAGE MEDIUM STORING DIGITAL DATA CORRECTION PROGRAM AND DIGITAL DATA CORRECTION APPARATUS - Digital data obtained by converting, by an A/D converter, an angular velocity measured by a sensor is transmitted from a remote control to a game machine. A CPU of the game machine corrects the digital data. That is, the CPU sequentially stores sequential digital data in a buffer. A stable range (d1-d2) in which each digital data can be defined to be stable is calculated for the latest digital data. An average value of those of the digital data stored in the buffer that are consecutively present in the stable range retrogressively from the latest digital data is calculated. Using the average value, the latest digital data is corrected. | 02-26-2015 |
20150061904 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND METHOD OF ANALOG-TO-DIGITAL CONVERSION - An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. | 03-05-2015 |
20150070197 | Sampling Input Stage with Multiple Channels - An analog input stage has m differential input channels, wherein m>1. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2 | 03-12-2015 |
20150077278 | SAMPLING - There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line. | 03-19-2015 |
20150102949 | METHOD AND APPARATUS FOR REDUCING CAPACITOR INDUCED ISI IN DACS - A circuit may include a plurality of primary digital-to-analog (DAC) elements for converting a digital input signal into an analog output signal. A control circuit may control each primary DAC element to switch between a first state and a second state based on the digital input signal to provide the analog output signal at an output representing the digital input signal. A plurality of corrective DAC elements may be coupled in parallel to the plurality of primary DAC elements between the control circuit and the output. The plurality of corrective DAC elements may be controlled to mitigate for intersymbol interference (ISI) due to parasitic capacitance in the primary DAC elements. The plurality of corrective DAC elements may not contribute a direct current to the analog output signal. | 04-16-2015 |
20150109155 | SEMICONDUCTOR DEVICE AND ELECTRONIC CONTROL DEVICE - To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch. A correction circuit generates a voltage obtained by adding the second voltage to a voltage between the second node and the first node as a correction voltage. A double integral ADC finds a first integral time elapsed when a difference voltage of the correction voltage to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when the difference voltage of the first voltage to the voltage of the first node is integrated to the correction voltage. | 04-23-2015 |
20150116137 | SYSTEM FOR LINEAR INTERPOLATION IN MULTIPLE DIMENSIONS - A system for galvanic isolation between an analog input signal and an analog output signal, which system performs an analog to digital conversion of the input signals into input digital data. As a result, input parameters can be corrected in a nearly perfect way. | 04-30-2015 |
20150145708 | CONVERTING CIRCUIT AND COMMUNICATION DEVICE - A converting circuit and a communication device are provided. The converting circuit includes: a sample hold circuit for receiving an analog signal; a Digital to Analog Converter (DAC); a comparator being connected with an output end of the sample hold circuit and an output end of the DAC; and a control circuit being connected with an output end of the comparator, wherein when the sample hold circuit receives an analog signal, the control circuit controls the sample hold circuit and the comparator to work, controls an output of the DAC based on an output of the comparator, and outputs a corresponding digital signal; and when the control circuit detects a digital signal is input, the control circuit controls the DAC to convert the digital signal into an corresponding analog signal and output the corresponding analog signal. The converting circuit can reduce chip area and chip cost. | 05-28-2015 |
20150145709 | N-Path Interleaving Analog-to-Digital Converter (ADC) with Background Calibration - A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s | 05-28-2015 |
20150311909 | CONVERTER FOR ANALOG INPUTS - A device having a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, and a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics. The device also having one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, such that a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input. | 10-29-2015 |
20150326239 | CALIBRATION OF HIGH SPEED ASYNCHRONOUS CONVERTOR - An example method includes extracting calibration coefficients of each stage of a pipeline analog-to-digital convertor (ADC). The calculation of the corrected digital output of the pipeline ADC can be based on the digital output of each pipeline stage and the estimated calibration coefficient of the corresponding stage. Therefore, a relaxed design of the operational amplifier and sizing of capacitors in a high speed asynchronous ADC can be achieved. | 11-12-2015 |
20150326240 | CALIBRATION OF TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - Various embodiments describe systems and methods for calibrating gain mismatches and timing errors in and between individual ADC channels of a time-interleaved ADC. In some embodiments, a calibration signal (e.g., a DC signal) can be selectively applied to each ADC channel of a time-interleaved ADC to estimate a gain mismatch of the corresponding ADC channel. The gain mismatch can then be compensated by a gain correction circuit at the digital backend of the time-interleaved ADC. In some embodiments, timing errors between ADC channels of a time-interleaved ADC can be measured by applying a time varying signal to the ADC channels of the time-interleaved ADC. The timing errors can be calibrated by applying a feedback signal to a clock phase generator of the time-interleaved ADC. | 11-12-2015 |
20150341043 | A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value. | 11-26-2015 |
20150341044 | INTERLEAVED A/D CONVERTER - It is a problem that each ADC sampling circuit connected in parallel in an interleaved ADC releases an electric charge depending on an input signal when sampling is performed and other ADCs connected in parallel sample the input signal disturbed thereby so that resolution of the interleaved ADC is decreased. | 11-26-2015 |
20150358027 | SENSOR SIGNAL PROCESSING APPARATUS AND SENSOR APPARATUS - In a sensor signal processing apparatus, a control unit executes at least one of a temperature measurement process and a calculation process in parallel with a signal conversion process. In the temperature measurement process, the control unit causes a second A/D converter to execute the A/D conversion of a temperature signal. In the calculation process, the control unit calculates an offset and a conversion gain of a first A/D converter base on an A/D conversion value output from the second A/D converter and pre-prepared temperature characteristic data of a physical quantity sensor. In the signal conversion process, the control unit sets the calculated offset and the calculated conversion gain to the first A/D converter, and causes the first A/D converter to execute the A/D conversion of the sensor signal. | 12-10-2015 |
20150372689 | THRESHOLD CORRECTION METHOD FOR MULTI-VOLTAGE THRESHOLD SAMPLING DIGITIZATION DEVICE - A threshold correction method is for a multi-voltage threshold sampling digitization device. The method includes: generating a triangular wave, and measuring the slope k1 of the rising edge part and the slope k2 of the falling edge part of the waveform of the triangular wave and the peak value amplitude Vpeak thereof, the width DOT of the part of the pulse higher than an actual working threshold Vt being represented as DOT(Vt)=(Vpeak−Vt)/k1−(Vpeak−Vt)/k2; setting n groups of threshold pairs; calculating a threshold under an actual working state using the measured pulse width DOT according to a formula; and establishing a threshold correction function according to a corresponding relationship between actual working state thresholds and reference voltages set practically, and then correcting a set threshold according to the function. | 12-24-2015 |
20150381193 | MULTI-CHANNEL TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - The present invention provides a multi-channel time-interleaved analog-to-digital converter, including: a clock generation circuit, configured to generate a work clock of the analog-to-digital converter; a channel ADC group, including M ADC channels, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals; a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels; a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected, compensation and reconstruction on the digital output signals output by the channel ADC group; and a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit. | 12-31-2015 |
20160043729 | SEMICONDUCTOR DEVICE - A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted. | 02-11-2016 |
20160043731 | Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation - Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients. | 02-11-2016 |
20160072516 | VOLTAGE REGULATOR WITH LOAD COMPENSATION - A voltage regulation system provides a relatively stable voltage source without introducing the typical costs of a ground buffer. The disclosed voltage regulation system includes a voltage regulator that is operative to detect a change of the load current and regulate a current bypass mechanism to stabilize a total supply current. For example, the voltage regulator includes a current sensor and a current compensation circuit. The current sensor is configure to generate a current compensation signal based on the load current change, whereas the current compensation circuit is configured to adjust a bypass current in response to the current compensation signal. As a result, the bypass current dynamically compensates the load current change such that the ground voltage of a variable load becomes relatively stable over a range of load currents. | 03-10-2016 |
20160079994 | METHODS AND APPARATUS FOR REDUCING TIMING-SKEW ERRORS IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels. | 03-17-2016 |
20160087643 | ANALOG-TO-DIGITAL CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT - A time-interleaved analog-to-digital converter that samples an analog input signal at a sampling frequency and converts the analog input signal into a digital output signal is enabled to perform correction processing on an error by: converting the analog input signal into the digital output signal by a plurality of analog-to-digital conversion circuits in a time-interleaved manner; and performing gain correction processing and skew correction processing with respect to the analog-to-digital conversion circuit, on the basis of a mixed signal, the mixed signal being obtained by mixing an output signal from the analog-to-digital conversion circuit with a signal made by shifting a phase of the output signal by π/2. | 03-24-2016 |
20160087644 | Asynchronous Low-Power Analog-to-Digital Converter Circuit With Configurable Thresholds - An analog-to-digital converter circuit is described that includes register space to keep one or more values to establish upper and lower thresholds of the analog-to-digital converter. The analog-to-digital converter circuit also includes first and second comparators to compare an analog input signal against the upper and lower thresholds and to trigger an analog-to-digital conversion process in response to the analog input signal crossing one of the thresholds. The analog-to-digital converter circuit also includes first logic circuitry to discard a result of the analog-to-digital conversion process if the result is within a prior analog-to-digital conversion process's thresholds. The analog-to-digital converter circuit also includes second logic circuitry to provide the result as an output and generate an interrupt if the result is not within the prior analog-to-digital conversion process's thresholds. | 03-24-2016 |
20160094237 | CIRCUIT, AN INTEGRATED CIRCUIT, A TRANSMITTER, A RECEIVER, A TRANSCEIVER, A METHOD FOR GENERATING A PROCESSED OSCILLATOR SIGNAL, AN APPARATUS FOR GENERATING A PROCESSED OSCILLATOR SIGNAL, AND SOFTWARE-RELATED IMPLEMENTATIONS - A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique. | 03-31-2016 |
20160099722 | METHOD AND APPARATUS FOR CALIBRATING COMPARATOR OFFSET OF SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER - A circuit and method compensates for comparator offset in a successive approximation register analog-to-digital converter. The circuit includes a multiplexed sampler to sample either a common mode voltage or an input signal. The sampled signal is added to a conversion voltage and an offset correction voltage and input to a comparator. The comparator determines a polarity of deviation of the sum of the sampled signal, conversion voltage and off-set correction voltage. Based on the polarity, the offset correction voltage and the conversion voltage are alternately subjected to a successive approximation process to compensate for the offset of the sum from the sampled input signal or sampled common voltage signal. | 04-07-2016 |
20160103423 | Bang-Bang Time to Digital Converter Systems and Methods - A time to digital converter includes a mutual exclusion element and a sampling component. The mutual exclusion element is configured to receive a first clock and a second clock and to generate a first pulse and a second pulse. The mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock. The sampling component is configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse. | 04-14-2016 |
20160118994 | INTERCONNECT STRUCTURES FOR MINIMIZING CLOCK AND OUTPUT TIMING SKEWS IN A HIGH SPEED CURRENT STEERING DAC - A system includes a clock interconnect network having an input node and a plurality of output nodes. The clock interconnect network receives a clock input at the input node and distributes, based on the clock input, a plurality of clock signals via respective ones of the plurality of output nodes. A propagation delay of each of the plurality of clock signals distributed by the clock interconnect network is approximately equal to respective propagation delays of others of the plurality of clock signals distributed by the clock interconnect network. A digital-to-analog converter includes a plurality of segments, each outputting a respective output, and a plurality of drivers. Each of the plurality of drivers receives a respective one of the plurality of clock signals and provides a driver signal to a respective one of the plurality of segments based on the respective one of the plurality of clock signals. | 04-28-2016 |
20160118995 | ANALOG-TO-DIGITAL CONVERSION WITH NOISE INJECTION VIA WAVEFRONT MULTIPLEXING TECHNIQUES - A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality. | 04-28-2016 |
20160118996 | DIGITAL-TO-ANALOG CONVERSION APPARATUS FOR GENERATING COMBINED ANALOG OUTPUT BY COMBINING ANALOG OUTPUTS DERIVED FROM USING DIFFERENT SAMPLING CLOCKS AND RELATED METHOD THEREOF - A digital-to-analog conversion apparatus has a first digital-to-analog converter, at least one second digital-to-analog converter, and a combining circuit. The first digital-to-analog converter is arranged to receive a first sampling clock and a digital input, and convert the digital input into a first analog output according to the first sampling clock. The at least one second digital-to-analog converter is arranged to receive the digital input and at least one second sampling clock different from the first sampling clock, and convert the digital input into at least one second analog output according to the at least one second sampling clock. The combining circuit is arranged to combine the first analog output and the at least one second analog output into a combined analog output of the digital input. | 04-28-2016 |
20160126962 | CLOCK GENERATION CIRCUIT, SUCCESSIVE COMPARISON A/D CONVERTER, AND INTEGRATED CIRCUIT DEVICE - A clock generation circuit includes a first loop circuit configured to generate a first clock, and a second loop circuit configured to generate a second clock including a period different from a period of the first clock. A fluctuation in an amount of delay of the first clock is adjusted based on the second clock and the first clock including the period adjusted is output. | 05-05-2016 |
20160126967 | APPARATUS AND METHOD FOR ANALOG-DIGITAL CONVERTING - Provided is an apparatus for analog-digital converting that includes a Most Significant Bit (MSB)-Digital Analog Converter (DAC) for converting a digital signal into an analog signal, a trim capacitor, a Least Significant Bit (LSB)-DAC, coupled to the trim capacitor, for converting a digital signal into an analog signal, a bridge capacitor connecting the MSB-DAC and the LSB-DAC, a comparator for measuring a voltage value at the MSB-DAC and LSB-DAC and outputting a result of comparing with a sampled voltage value, and a controller for generating first measurement data by digital converting a first measurement value output from the comparator by applying a reference voltage to a unit capacitor of the MSB-DAC, for generating second measurement data by digital converting a second measurement value output from the comparator by applying the reference voltage to the LSB-DAC, and controlling the trim capacitor by comparing the first and second measurement data. | 05-05-2016 |
20160126970 | Receiver with Adjustable Reference Voltages - A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators. | 05-05-2016 |
20160134293 | Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators - A negative-capacitance circuit comprises a first node coupled to a drain of a first transistor and a gate of a second transistor; a second node coupled to a drain of the second transistor and a gate of the first transistor; a capacitor coupled between a source of the first transistor and a source of the second transistor; a first current mirror coupled between a supply voltage and the source of the first transistor; and a second current mirror coupled between the supply voltage and the source of the second transistor. The circuit can be configured to drive the differential capacitive load between the first and second nodes in a shorter time period, thereby increasing the transfer bandwidth of the differential signal. | 05-12-2016 |
20160142068 | ANALOG-TO-DIGITAL CONVERTER - Improvement of conversion precision in an analog-to-digital converter is realized. Therefore, a voltage of a correction signal and a voltage obtained by attenuating the voltage with a fixed attenuation rate by an attenuation circuit | 05-19-2016 |
20160142069 | Multi-path, series-switched, passively-summed digital-to-analog converter - A digital-to-analog converter which minimizes noise and optimizes dynamic range by apportioning a least significant bits portion of an incoming digital signal to a low-path circuit and a most significant bits portion of the incoming digital signal to a high-path circuit. The low-path circuit has a low-path digital-to-analog converter, which feeds a low-path amplifier, which feeds a low-path resistive element, which feeds an output node. The high-path circuit has a high-path digital-to-analog converter, which feeds a high-path amplifier, which feeds a high-path resistive element when a high-path switching element is closed, which feeds an output node. The output node is a simple electrical connection of the outputs of the low-path and high-path resistive elements. The high-path switching element is closed when the incoming digital signal has an amplitude above a switching threshold level. Parameters of the circuit, including the sizes of the least significant bits portion and most significant bits portion of the incoming digital signal, are selected such that the switching threshold level is significantly above the noise level produced by the high-path circuit thereby providing psychoacoustic masking of noise produced by the high-path circuit. | 05-19-2016 |
20160191020 | COMPENSATOR FOR REMOVING NONLINEAR DISTORTION - The present invention is a computationally-efficient compensator for removing nonlinear distortion. The compensator operates in a digital post-compensation configuration for linearization of devices or systems such as analog-to-digital converters and RF receiver electronics. The compensator also operates in a digital pre-compensation configuration for linearization of devices or systems such as digital-to-analog converters, RF power amplifiers, and RF transmitter electronics. The compensator effectively removes nonlinear distortion in these systems in a computationally efficient hardware or software implementation by using one or more factored multi-rate Volterra filters. Volterra filters are efficiently factored into parallel FIR filters and only the filters with energy above a prescribed threshold are actually implemented, which significantly reduces the complexity while still providing accurate results. For extremely wideband applications, the multi-rate Volterra filters are implemented in a demultiplexed polyphase configuration which performs the filtering in parallel at a significantly reduced data rate. The compensator is calibrated with an algorithm that iteratively subtracts an error signal to converge to an effective compensation signal. The algorithm is repeated for a multiplicity of calibration signals, and the results are used with harmonic probing to accurately estimate the Volterra filter kernels. The compensator improves linearization processing performance while significantly reducing the computational complexity compared to a traditional nonlinear compensator. | 06-30-2016 |
20160191033 | DIGITAL TO ANALOG CONVERTER, UNIT FOR THE SAME, AND METHOD FOR USING THE SAME - Disclosed herein is a digital-to-analog converter (DAC) including a clock driver for controlling a clock signal to provide an inverse delay clock signal to allow at least selective adjustment of a return to zero (RZ) section; and a DAC core comprising at least two DAC units for receiving a digital input value, the clock signal and the inverse delay clock signal and providing an analog output value. According to the present invention, distortion of the output of the DAC may be attenuated and loss of the output may be minimized by utilizing the RZ technique. | 06-30-2016 |
20160191069 | ANALOG-TO-DIGITAL CONVERTER FOR CORRECTING ERROR AND ANALOG-TO-DIGITAL CONVERTING METHOD - An analog-to-digital converter includes an upper bit conversion unit suitable for receiving an input signal, and sampling upper bits from the input signal, a lower bit conversion unit suitable for receiving a residual voltage remaining after the sampling of the upper bit conversion unit, and sampling lower bits from the residual voltage, and an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits. | 06-30-2016 |
20160191071 | METHOD AND APPARATUS FOR CALIBRATION OF A TIME INTERLEAVED ADC - A system for calibrating time interleaved ADCs is disclosed and may include a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, the time interleaved ADC comprising: a plurality of active slices, and a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices. An output of each reference slice may be used to correct distortion in an output of the corresponding active slice. Each active slice may sample an input signal at a first rate and each associated reference slice may sample the input signal at a second rate, the second rate being slower than the first rate. Each sample taken by one of the plurality of reference slices may then be taken concurrent with a sample taken by the associated active slice. Each reference slice may include a reference sampling module and a dummy load. | 06-30-2016 |
20160254820 | Digital-To-Analog Converter Using Nonlinear Capacitance Compensation | 09-01-2016 |
20160380643 | Reducing Distortion In An Analog-To-Digital Converter - In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value. | 12-29-2016 |
20160380646 | APPARATUS FOR OVERLOAD RECOVERY OF AN INTEGRATOR IN A SIGMA-DELTA MODULATOR - Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output. | 12-29-2016 |
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20190149166 | COMPUTATIONAL DEVICES USING THERMOMETER CODING AND SCALING NETWORKS ON UNARY ENCODED DATA | 05-16-2019 |