| Entries |
| Document | Title | Date |
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| 20080198048 | Systems and methods for companding ADC-DSP-DAC combinations - Systems and methods for resizing a signal for use with a fixed-point DSP are provided. More specifically, a process called companding is used in conjunction with fixed-point devices to resize a signal to make use of the available range of these devices. In some embodiments, companding is used to improve the signal-to-noise and distortion ratio. Also, information loss associated with quantization and rounding errors can be reduced in some embodiments. | 08-21-2008 |
| 20080238737 | REFERENCE VOLTAGE SHIFTING TECHNIQUE FOR OPTIMIZING SNR PERFORMANCE IN PIPELINE ADCS WITH RESPECT TO INPUT SIGNAL - An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of digital intermediate signals in response to an analog input signal, a first set of threshold and reference voltages and a second set of threshold and reference voltages, where the threshold and reference voltages of the first set are shifted with respect to corresponding threshold and reference voltages of the second set. The second circuit may be configured to generate a digital output signal in response to the plurality of digital intermediate signals. | 10-02-2008 |
| 20080266152 | Digital radio frequency memory - A digital radio frequency memory (DFRM) which converts an incoming analog radio frequency signal to a fourteen bit digital signal allowing for digital signal processing and then retransmitted as an analog RF signal. The DFRM provides a time delay for RF signals by storing the signal. The DFRM also changes the signal frequency in the range of plus or minus 100,000 KHz which places a doppler on the signal. The signal phase is changed in a range of 0 to 359 degrees by the DFRM. | 10-30-2008 |
| 20080272941 | SYSTEM OF MULTI-CHANNEL ANALOG SIGNAL GENERATION AND CONTROLLED ACTIVATION OF MULTIPLE PERIPHERAL DEVICES - The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data buss. Signals on the data buss are used to drive the multiple peripheral devices. | 11-06-2008 |
| 20090009371 | METHOD AND APPARATUS FOR A/D CONVERSION - A method and an apparatus for converting an analog input signal into a digital output signal using a sigma-delta modulator architecture with a digital tracking filter. The digital tracking filter may have an order greater than one, and the signal and noise transfer functions of the sigma-delta modulator architecture are chosen to provide a sigma-delta modulator architecture with a high dynamic range even if a relatively low oversampling ratio is used. | 01-08-2009 |
| 20090058696 | METHOD AND APPARATUS FOR REAL-TIME TIME-DOMAIN INTEGRATION OR DIFFERENTIATION OF VIBRATION SIGNALS - A vibration data collection system performs an integration or differentiation process on incoming digitized vibration data in real time. The system uses a digital Infinite Impulse Response (IIR) filter running at the input data rate to provide the integration or differentiation function. With this approach, the system reduces hardware complexity and data storage requirements. Also, the system provides the ability to directly integrate or differentiate stored time waveforms without resorting to FFT processing methods. | 03-05-2009 |
| 20090066547 | ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERSION WINDOW ADJUSTMENT BASED ON REFERENCE CELLS IN A MEMORY DEVICE - An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array. | 03-12-2009 |
| 20090066548 | METHOD AND SYSTEM FOR COMPENSATION OF DC OFFSET IN AN RF RECEIVER - System and method for processing signals are disclosed. The method may include converting, in an RF receiver, one or more analog samples, which are selected from one of a plurality of output paths of the RF receiver, to one or more digital samples. A digital feedback value may be generated based on an average of the one or more converted digital samples. A scaled version of the generated digital feedback value may be converted to an analog value. The converted analog value may be fed back to one or more of a plurality of input paths of the RF receiver. The one or more analog samples may be selected from among a plurality of output analog samples from the plurality of output paths of the RF receiver. | 03-12-2009 |
| 20090085782 | ADJUSTABLE DAC AND APPLICATIONS THEREOF - A digital to analog converter (DAC) includes at least one digital to analog conversion module and a gated termination. The at least one digital to analog conversion module is coupled to convert at least one bit of a digital signal into an analog signal. The gated termination is coupled to an analog output of the at least one digital to analog conversion module to provide a first termination when a termination selection signal is in a first state and to provide a second termination when the termination selection signal is in a second state. | 04-02-2009 |
| 20090102688 | MULTISTAGE ANALOG/DIGITAL CONVERTER AND METHOD FOR CALIBRATING SAID CONVERTER - A multistage analog/digital converter for converting in multi-step cycles an input signal into respective digital codes, each cycle step resolving at least one bit of a respective digital code. The converter includes: a sampling circuit inputting the signal and outputting a first sequence of analog samples; a generation block of a pseudorandom sequence of samples; a summing node, such as to input the first sequence and the pseudorandom sequence, obtaining in output a second sequence of analog samples including non-pseudorandom samples; a converter having a controllable digital gain receiving the second sequence and outputting bits of the digital codes; a feedback loop with a loop gain and including an analog amplifier; a digital calibration block to match the digital gain to the loop gain and including a prediction block to produce a digital estimation of said input signal starting from the bits resulting from converting the non-pseudorandom samples. | 04-23-2009 |
| 20090167574 | Amplifier gain control circuit for the wireless transceiver - An amplifier gain control circuit for the wireless transceiver comprises at least one amplifier, an analog to digital converter (ADC), a digital to analog converter (DAC) and a bias circuit, wherein the ADC is used for receiving an analog gain control voltage to generate a digital control signal that can be used for controlling the gain of the amplifier, the DAC is used for receiving the digital signal to generate an analog signal, and the bias circuit is used for receiving the analog signal and the analog gain control voltage to further fine-tune the gain of the amplifier by the analog process for correcting the least bit error during the digital process, therefore, the amplifier during the gain adjustment will be prevented to operate in the nonlinear area. | 07-02-2009 |
| 20090195422 | AREA AND POWER EFFICIENT ANALOG TO DIGITAL CONVERTER AND METHODS FOR USING SUCH - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide analog to digital converter circuits that are capable of converting an input voltage to a digital representation thereof. Such analog to digital converter circuits include at least a first comparator and a second comparator. An input of the first comparator is electrically coupled to a first storage device, and another input of the first comparator is electrically coupled to the input voltage. An input of the second comparator is electrically coupled to a second storage device, and another input of the second comparator is electrically coupled to the input voltage. The analog to digital converter circuits further include a reference voltage generation circuit that provides the first reference voltage to the first storage device, and subsequently provides the second reference voltage to the second storage device. | 08-06-2009 |
| 20090195423 | Analog to digital converters - An analog to digital converter (ADC) converts an analog signal to a digital signal. The ADC includes an input channel, a sampling circuit coupled to the input channel, an integrator coupled to the sampling circuit, and a feedback circuit coupled to the integrator. The input channel receives the analog signal. The sampling circuit samples the analog signal. The integrator receives the sampled analog signal and a feedback signal and integrates a superposition of the sampled analog signal and the feedback signal. The feedback circuit generates the digital signal according to an output of the integrator and sends the feedback signal indicative of the digital signal to the integrator. | 08-06-2009 |
| 20090267814 | CIRCUIT ARRANGEMENT, L[OCAL] I[NTERCONNECTED] NE[TWORK] COMPRISING SUCH CIRCUIT ARRANGEMENT AS WELL AS METHOD FOR PROCESSING INPUT SIGNALS OF THE LIN - Circuit arrangement, L[ocal]I[nterconnected]N[etwork] comprising such circuit arrangement as well as method for processing input signals of the LIN In order to further develop a circuit arrangement ( | 10-29-2009 |
| 20090289821 | PIPELINE ANALOG-TO-DIGITAL CONVERTER HAVING OPERATIONAL AMPLIFIER SHARED BY SAMPLE AND HOLD CIRCUIT AND LEADING MULTIPLYING DIGITAL-TO-ANALOG CONVERTER - A pipeline analog-to-digital converter includes a sample and hold circuit; a plurality of multiplying digital-to-analog converters having a leading MDAC coupled to the sample and hold circuit; and an operational amplifier, shared by the sample and hold circuit and the leading MDAC. The shared operational amplifier configured to be used by the sample and hold circuit when the sample and hold circuit enters a hold phase and used by the leading MDAC when the sample and hold circuit enters a sample phase can greatly reduce the power consumption of the pipeline ADC. | 11-26-2009 |
| 20090303090 | ISOLATION UNIT FOR A CONVENTIONAL 2-CONDUCTOR COMMUNICATION CONNECTION INCLUDING A SENSOR, A MEASUREMENT TRANSMITTER AND A CONTROL UNIT - For a conventional 2-conductor communication connection, which includes a sensor, a measurement transmitter and a control unit, an isolation unit is provided, which serves for transmission of digital signals, which are not transmitted by the measurement transmitter. Thus, in the case of a conventional 2-conductor communication connection, digital communication between the sensor and the control unit becomes possible. | 12-10-2009 |
| 20100013684 | AD converter and AD conversion method - An exemplary object of the present invention is to achieve both of high-speed operation by parallel processing and a simple configuration by sequential comparison processing, so as to realize high accuracy of AD conversion processing. An AD converter according to the present invention includes a parallel-type AD converting unit that generates an upper bit digital signal composed of a plurality of bits by parallel processing based on an input analog signal input from a predetermined input circuit, a sequential comparison type AD converting unit that generates a digital signal by sequential comparison processing based on a converted analog signal that is generated by converting the upper bit digital signal into an analog signal, and a reconversion controller that detects an indefinite bit included in the upper bit digital signal and reconverts the indefinite bit by the sequential comparison type AD converting unit. | 01-21-2010 |
| 20100019942 | Interpolation method and a circuit for carrying out said method used in a high-resolution encoder - Intermediate digital signals Fi(α), Gi(α), i=1, . . . I, are generated, which result from a comparison of reference potentials of the first input analogue signal at a shifted value of its observed argument and with a suitably reduced amplitude to the potential, which is inverse to said potential, of the third input analogue signal at the same shifted value of the observed argument and with the amplitude reduced in said way, the shifted argument values being uniformly distributed within the first half-period. A value U of the voltage is measured at any value of the observed argument as at that time the highest one of the voltages at terminals with said reference potentials. An actual peak amplitude A of the input analogue signals is determined as A=k | 01-28-2010 |
| 20100026535 | SEGMENTED OPTICS CIRCUIT DRIVE FOR CLOSED LOOP FIBER OPTIC SENSORS - Systems and methods for improving output resolution of an optical drive circuit in an optical sensor. The optical sensor circuit includes an optics circuit that generates analog measurement data, a detector circuit that detects the analog measurement data and converts the analog measurement data to a digital measurement data, and a signal processing circuit that demodulates the digital measurement data and generates a segmented digital signal based on the demodulated digital measurement data. The optical sensor circuit further includes an optics drive circuit that generates an analog drive signal based on the segmented digital signal. The analog drive signal is then used to drive the optical circuit. | 02-04-2010 |
| 20100045495 | SWITCHED CAPACITOR CIRCUIT AND PIPELINE A/D CONVERTER - There is provided a switched capacitor circuit and a pipeline A/D converter which are capable of suppressing electric power from being increased by utilizing a level-shift capacitor, even in a case where the switched capacitor circuit and the pipeline A/D converter are configured by utilizing a CLS technique. In the estimate phase, the capacitor Cc | 02-25-2010 |
| 20100060494 | Analog to Digital Converter - An analog to digital converter (ADC) can operate in an amplifier configuration or a converter configuration. In the amplifier configuration, the ADC receives an input voltage and scales the input voltage by a factor during at least one clock cycle. In the converter configuration, the ADC uses the scaled input voltage to determine a digital value corresponding to the input voltage. | 03-11-2010 |
| 20100085225 | SUCCESSIVE APPROXIMATION ADC WITH BINARY ERROR TOLERANCE MECHANISM - A successive approximation ADC is disclosed. A comparator receives and compares a sampled input signal and an output of a DAC. Non-binary successive approximation register (SAR) control logic controls sampling of the input signal and controls a sequence of comparisons based on comparison result of the comparator. The SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled. A binary-error-tolerant corrector is then used to compensate the sampling error. | 04-08-2010 |
| 20100141490 | Model based distortion reduction for power amplifiers - A method of processing a signal is disclosed. The method comprises generating a digital signal, converting the digital signal to an analog signal, and generating an amplified analog signal having distortions. The method further comprises converting the amplified analog signal to a feedback digital signal at a sample rate and updating a model of the distortions based on the feedback digital signal. | 06-10-2010 |
| 20100182173 | FLIP-FLOP AND PIPELINED ANALOG-TO-DIGITAL CONVERTER UTILIZING THE SAME - A flip-flop includes a sense amplifier stage and a latch stage. The sense amplifier includes a first P type transistor and generates a first sensed signal and a second sensed signal in a first node and a second node, respectively. When the first P type transistor is turned on, the first node is connected to the second node. The latch stage generates a first output signal and a second output signal according to the first and the second sensed signals. | 07-22-2010 |
| 20100219995 | Demodulator Capable of Compensating Offset Voltage of RF Signal and Method Thereof - A demodulator capable of compensating for an offset voltage of a radio frequency (RF) signal, and a method of compensating for the offset voltage of the RF signal are provided. The demodulator includes an analog-to-digital conversion (ADC) unit for converting a first analog signal corresponding to a difference between the RF signal comprising the offset voltage and an analog reference signal into a first digital signal, and a compensation voltage generation unit for converting the first digital signal into an offset compensation voltage. The ADC unit converts a second analog signal corresponding to a difference between the RF signal comprising the offset voltage and the offset compensation voltage into a second digital signal. Accordingly, the offset voltage included in the RF signal is compensated for, and thus distortion and a signal-to-noise ratio (SNR) of the RF signal are reduced. This leads to an improvement of the reception sensitivity of an RF receiver. | 09-02-2010 |
| 20100225509 | ANALOG-DIGITAL CONVERTER WITH PIPELINE ARCHITECTURE ASSOCIATED WITH A PROGRAMMABLE GAIN AMPLIFIER - A device may include a programmable gain amplifier and an analog-digital converter with pipeline architecture having several stages. The first stage of the analog-digital converter may incorporate the programmable gain amplifier and an analog-digital conversion circuit with a programmable threshold. | 09-09-2010 |
| 20100259428 | METHOD AND APPARATUS FOR RECONSTRUCTING DIGITIZED DISTORTED SIGNALS - A method of reproducing an original analog signal modified by a distortion and sampled. The distortion may be linear or nonlinear, and the samples may be either ideal or non-ideal. The method determines a stationary point of a cost function based on an error vector. The method iteratively computes approximated analog signals until the approximated analog signals converge to the original analog signal. The method may utilize Fr?chet derivatives and Moore-Penrose pseudo inverse transformations in order to iteratively compute the original analog signal. An apparatus performing said method is also disclosed. | 10-14-2010 |
| 20100295714 | Pipelined Analog-to-Digital Converter - A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, at least one of the stages includes a sample and hold circuit. The sample and hold circuit includes a first output connected to an input of a sub-ADC, an output of the sub-ADC connected to an input of a Digital-to-Analog Converter (DAC), an output of the DAC connected to a node, and a second output connected to the node. The sample and hold circuit is configured to independently scale a signal produced by the first output and a signal produced by the second output. | 11-25-2010 |
| 20100302082 | DEVICE FOR RECEIVING A RF SIGNAL WITH LOOP-THROUGH OUTPUT AND METHOD FOR LOOPING A RF INPUT SIGNAL THROUGH A DEVICE FOR RECEIVING RF SIGNALS - A device for receiving a RF signal ( | 12-02-2010 |
| 20100309032 | ANALOG-TO-DIGITAL CONVERTER, ANALOG-TO-DIGITAL CONVERSION METHOD, AND OPTICALLY COUPLED INSULATING DEVICE - An analog-to-digital converter includes a first switch circuit, a first integrator, a second switch circuit, a second integrator, a quantizer and a digital-to-analog converter. The first switch circuit receives an external analog signal, outputs the analog signal in reverse phase, and outputs the analog signal in positive phase. The first integrator receives and integrates the analog signal with cross-coupling. The second switch circuit outputs an output of the first integrator and a common mode output potential of the first integrator. The second integrator samples and integrates an output of the second switch circuit. The quantizer single-bit-quantizes an output of the second integrator to provide the output as a digital signal output. The digital-to-analog converter receives an output of the quantizer and provides the output as an analog signal output. Each of the first and second integrators receives and integrates an output of the digital-to-analog converter with cross-coupling. | 12-09-2010 |
| 20100315271 | INTEGRATED CIRCUITS FOR CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS, SYSTEMS, AND OPERATING METHODS THEREOF - An integrated circuit that is capable of converting an analog signal to at least one digital signal is provided. The integrated circuit includes a first input end capable of receiving a first analog signal. A first set of 2 | 12-16-2010 |
| 20100315272 | CAPACITIVE TRANSDUCER CIRCUIT AND METHOD - A capacitive transducer circuit comprises a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analogue signal on an input terminal, the first analogue signal being generated by the capacitive transducer, and to generate a second analogue signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. The output of a voltage source which provides the other bias voltage for the capacitive transducer may be filtered by a low pass filter. The low pass filter may comprise a switched capacitor filter circuit. | 12-16-2010 |
| 20100328119 | SWITCHED-CAPACITOR CIRCUIT HAVING A CAPACITOR ARRAY CIRCUIT, AND ANALOG-TO-DIGITAL CONVERTER USING SAID SWITCHED-CAPACITOR CIRCUIT - A capacitor array circuit receives a plurality of input signals, generate a single output signal by combining the plurality of input signals, and output the single output signal. A comparator receives the output signal of the capacitor array circuit. A current source, which is disposed between a predetermined fixed voltage source and an output terminal of the switched-capacitor circuit, supplies the current to the output terminal until the output signal of the comparator changes. A plurality of input capacitors in the capacitor array circuit receives a plurality of input signals in parallel with each other. At least one additional regulating capacitor in the capacitor array circuit store the charge to compensate for an offset component caused by the delay in the comparator. The respective output terminals of the plurality of input capacitors and the at least one additional regulating capacitor are combined into one. | 12-30-2010 |
| 20100328120 | Comparator Based Asynchronous Binary Search A/D Conveter - The present invention is related to an analog-to-digital converter circuit ( | 12-30-2010 |
| 20110025534 | Linearity enhancement circuit, A/D converter, and reception apparatus - A linearity enhancement circuit is disclosed which includes: a first shift amount creation block creating a first shift amount in keeping with the immediately preceding output code of an n-bit A/D converter; a first shifter circuit bit-shifting input code data by the first shift amount that has been supplied, the first shifter circuit further outputting the bit-shifted input code data; a register storing the output of the first shifter circuit in order to output the stored data as the input code data to the first shifter circuit thereby forming a loop circuit in conjunction with the first shifter circuit, the register further outputting the stored code data as a second shift amount; and a second shifter circuit bit-shifting the output code of the A/D converter by the second shift amount that has been supplied, the second shifter circuit further outputting the bit-shifted output code to an n-bit D/A converter. | 02-03-2011 |
| 20110084860 | APPARATUS AND METHOD FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipelined analog-to-digital converter includes a control and correction circuit; and a plurality of MDAC stages. At least one of the MDAC stages includes: an MDAC input to receive an analog input voltage; and a dual latch flash ADC comprising one or more dual latch comparators. At least one of the dual latch comparators includes: a pre-amplifier having an input coupled to the MDAC input, and an output; a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output; a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch may generate a first digital signal; and a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch may generate a second digital signal. | 04-14-2011 |
| 20110090103 | ANALOG-TO-DIGITAL CONVERTER - A sequential comparison-type analog-to-digital converter (ADC) that has improved precision and which is capable of high-speed operation is disclosed, the analog-to-digital converter comprising a digital-to-analog converter that outputs a plurality of different reference analog signals according to a multibit digital signal, a plurality of comparators that compare an input analog signal with the plurality of reference analog signals, and a sequential comparison control circuit that changes bit values of the multibit digital signal in order from higher bits so that at least one of the plurality of reference analog signals becomes closer to the input analog signal and decides the bit values in order from higher bits based on the comparison results and at the same time, correcting the decided higher bit values, wherein the sequential comparison control circuit decides the bit values of the multibit digital signal down to a predetermined bit based on the comparison results of the plurality of comparators and at the same time, correcting the bit values, and decides the bits lower than the predetermined bit based on the comparison result of one of the plurality of comparators. | 04-21-2011 |
| 20110115657 | METHOD AND APPARATUS FOR PULSE WIDTH MODULATION SIGNAL PROCESSING - A signal processor ( | 05-19-2011 |
| 20110133963 | Successive aproximation A/D Converter - A successive approximation A/D converter, includes a reference voltage generation circuit, a sample/hold circuit, a D/A converter circuit, a comparator, and a control circuit. A potential difference between the comparison target voltage generated by the D/A converter circuit and the internal analog voltage is applied to one input terminal of the comparator through a first signal line, and the reference voltage generation circuit is connected to the other input terminal of the comparator through a second signal line and a switch. Capacitive elements are disposed between the high potential power supply and the second signal line, and between the second signal line and the low potential power supply, respectively. The control circuit turns ON the switch to charge the first and second capacitive elements during a period when the sample/hold circuit samples and holds the internal analog voltage and turns OFF the switch in response to end of the period. | 06-09-2011 |
| 20110133964 | OVERSAMPLING A/D CONVERTER - An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier. | 06-09-2011 |
| 20110175759 | OPERATIONAL AMPLIFIER AND PIPELINE AD CONVERTER - A differential voltage interconnect (W | 07-21-2011 |
| 20110181452 | Usage of Speaker Microphone for Sound Enhancement - The method and system use a speaker available in an audio end device when not in use as a microphone. The speaker is utilized for enhancing the sound quality received by the person or device at the near end, i.e., the user of the device, or the speaker at the far end, i.e., the speaker with whom the near-end speaker is communicating. Exemplary applications are shown for such utilization, including single or dual microphone near-end automatic listening enhancement, acoustic echo cancellation or suppression with or without double talk detection, and microphone array noise reduction. | 07-28-2011 |
| 20110187566 | NOISE SHAPING FOR DIGITAL PULSE-WIDTH MODULATORS - A noise shaper that compares an input signal to a feedback output signal, which is a truncated version of the input signal, and generates the difference between the two signals (i.e., the error). The noise shaper then integrates the errors by adding to the error multiple of its delayed versions, and quantizes the integrated errors in such a way that the spectrum of the quantization noise is shaped toward high frequencies to be removed by a LC low-pass filter used in conjunction with the noise shaper. The low frequency content of the desired signal is mostly unaffected. | 08-04-2011 |
| 20110193730 | PIPELINED A/D CONVERTER - Multiple stages sequentially convert respective input analog signals to partial digital data. Each stage includes: a partial A/D converter; a partial D/A converter; an adder that adds/subtracts the analog signal from the previous stage and an output from the partial D/A converter; and a gain amplifier that amplifies an output of the adder and supplies to the next stage. The pipelined A/D converter further includes: a correction value adding unit that adds a correction value to the output from the decoder unit; a correction value calculating unit that, based on the output from the correction value adding unit, calculates an error between the median of the output data and an ideal median at two points in the stage input/output characteristics, saves the calculated value as the correction value and supplies it to the correction value adding unit; and a control unit that controls the above units so as to perform the correction operation. Thereby, aliasing at decoding of the stage output is prevented, enabling an output range to be used effectively. | 08-11-2011 |
| 20110199244 | Pipelined ADC Calibration - A method of calibrating a pipelined analog to digital converter ( | 08-18-2011 |
| 20110210876 | Plug-in power line conditioner - A plug-in power line conditioner is configured to receive an AC voltage from a circuit and insert a correction signal onto the circuit. | 09-01-2011 |
| 20110215955 | SYSTEM INCLUDING FEEDBACK CIRCUIT WITH DIGITAL CHOPPING CIRCUIT - A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The chopping circuit is configured to receive the digital output signals and provide error signals that represent ripple error in the digital output signals. The integrator circuit is configured to accumulate the error signals and provide an accumulated error signal. The digital to analog converter circuit is configured to convert the accumulated error signal into an analog signal that is received by the second circuit to reduce the ripple error. | 09-08-2011 |
| 20110215956 | ANALOG-TO-DIGITAL CONVERTER AND CORRECTION METHOD THEREOF - An analog-to-digital (AD) converter device, includes: a capacitive digital-to-analog converter (DAC) including a reference capacitor group having capacitors which are weighted with a ratio, one terminal of each of the capacitors being coupled to a common signal line, the other terminal of each of the capacitors being coupled to one of reference power supplies via one of switches; a comparator to compare a voltage of the common signal line with a reference voltage; a successive approximation routine circuit to control the switches based on a comparison result of the comparator; an offset correction circuit to correct an offset of the comparator; and a DAC correction circuit to correct an error in a voltage change of the common signal line, the offset correction circuit and the DAC correction circuit performing a correction so that a residual offset of the comparator and a residual error of the capacitive DAC cancel. | 09-08-2011 |
| 20110227766 | Adaptive Ternary A/D Converter for Use in an Ultra-Wideband Communication System - In an ultra-wideband communication system, a 1-trit ternary analog-to-digital converter (“ADC”) having dynamic threshold adaption and providing an output in ternary form [+1, 0, −1]. The ternary ADC includes a pair of 1-bit binary ADCs, one being configured in a non-inverting form, and one being configured in an inverting form. Each binary ADC includes an feedback network mechanism, thereby allowing for simultaneous and independent adaptation of the pair of thresholds, compensating for the effects of any DC offset that may be present. The use of a trit-based ternary encoding scheme improves system entropy. | 09-22-2011 |
| 20110234433 | A/D CONVERTER - An A/D converter includes a capacitive DAC configured to perform conversion of high-order bits by receiving a differential signal, a resistive DAC configured to perform conversion of low-order bits, a resistive correction DAC configured to operate to correct the capacitive DAC, and a comparator. The capacitive DAC includes a positive-side capacitive DAC and a negative-side capacitive DAC operating in a complementary fashion, and the comparator, which includes a plurality of differential circuits, is configured to compare output potentials of the positive-side capacitive DAC and the negative-side capacitive DAC. The positive-side capacitive DAC and the negative-side capacitive DAC include first capacitive elements each formed from interconnect layers excluding an uppermost interconnect layer, and the comparator includes second capacitive elements each provided between adjacent ones of the differential circuits and formed from interconnect layers including the uppermost interconnect layer. | 09-29-2011 |
| 20110234434 | TWO-WIRE TRANSMITTER - There is provided a two-wire transmitter capable of obtaining a signal reflecting a continuous change in a sensor signal, and in addition, facilitating a configuration or processing in a subsequent stage. The two-wire transmitter that outputs an analog voltage signal V | 09-29-2011 |
| 20110241912 | ADC - This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit. In another embodiment the DAC signal is routed through a separate second buffer circuit. By use of a single buffer circuit, or where there is ideal matching of the buffer circuits in the latter embodiment, the distortion effects are completely eliminated; however, for practical imperfectly matched buffer circuits according to the latter embodiment, the gain and off-set mismatches can be accommodated through calibration of the buffers or, in suitable applications, through the DAC calibration. | 10-06-2011 |
| 20110254715 | CONTROLLER TO CONTROL ELECTRICAL POWER OF LOAD IN CONSTANT - A heater controller for controlling a heater precisely in the equi-power mode is disclosed. The controller includes a current source, a voltage monitor to detect a voltage drop caused in the heater, and a controller. The voltage drop may be converted to the digital form as refereeing to the first reference, while, the heater current is converted from the digital form as referring to the second reference. The second reference shows substantial temperature dependence, while, the first reference has lesser temperature dependence. The control corrects the temperature dependence of the second reference as referring to the first reference. | 10-20-2011 |
| 20110260898 | MISMATCH COMPENSATORS AND METHODS FOR MISMATCH COMPENSATION - In a compensator for compensating mismatches, and in methods for such compensation, the compensator compensates for mismatches in output signals of a system with mismatches during normal operation of the system with mismatches. The compensator comprises: a mismatch estimator that monitors at least two mismatched signals output by the system with mismatches during normal operation and that generates matching parameters indicating an amount of mismatch between the at least two mismatched signals, the mismatch estimator updating the matching parameters during normal operation of the system with mismatches, and a mismatch equalizer that compensates mismatches in the mismatched signals output by the system with mismatches during normal operation of the system with mismatches in response to the matching parameters. | 10-27-2011 |
| 20110267210 | Shaping Inter-Symbol-Interference in Sigma Delta Converter - A signal converting system is described that has a multi-segment digital to analog converter coupled to one or more error shaping loops. Each error shaping loop includes a quantizer with a feedback loop configured to generate a control signal responsive to a stream of symbols and to an error signal. Each error shaping loop also includes an inter-symbol-interference (ISI) shaping loop coupled to receive the control signal and to produce an ISI portion of the error signal that is responsive to inter-symbol transition rate. | 11-03-2011 |
| 20110279295 | PIPELINED ANALOG-TO-DIGITAL CONVERTER AND ITS SINGLE REDUNDANCY BIT DIGITAL CORRECTION TECHNIQUE - The present invention pertains to the technical field of A/D converter, to be more specific, a pipeline A/D converter and its single redundancy bit digital correction. The related single redundancy bit digital correction features the following steps: substages except for the last one quantizes input voltage, calculates the residual voltage, which is amplified and shifted to the middle part of the reference voltage range, and outputs to the following substage until the last one, which only quantizes the input voltage; The code and offset code of each substage, corresponding to the quantized thermometer code is calculated; the offset codes of all stages are added by weight to get total offset code; codes of all substages are added by weight, to which the total offset code is added. The comparator offset error is corrected to obtain an output code; the present invention released the A/D converter that applies the foregoing digital correction; the present invention is capable of reducing the number of substages of high speed and high resolution pipeline A/D converter and identifying the negative or positive overflows of input signals. | 11-17-2011 |
| 20110279296 | Data Converter Having a Passive Filter - Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC). | 11-17-2011 |
| 20110285561 | Impedance Matched Transmission Circuit With Analog-To-Digital Converter - An impedance matching transmission circuit for a transducer has a transmission medium connected to the transducer. A transmitting circuit is connected to the transmission medium with the transmitting circuit terminating in a reference circuit element. The transmitting circuit comprises an analog to digital converter having an analog input connected to the reference circuit element, and having a digital output. A digital to analog converter receives the digital output and generates an analog output signal in response thereto. A driver circuit is connected to the transmission medium and receives the analog output signal and supplies a driver signal to the transmission medium. | 11-24-2011 |
| 20110285562 | Continuous-time delta-sigma ADC with compact structure - A continuous-time delta-sigma Analog to Digital Converter (ADC) includes: a loop filter, for receiving and noise-shaping an analog input signal, and outputting a first loop voltage; a first summing resistor, for transforming a first feedback current to be a first feedback voltage, and summing the first loop voltage and the first feedback voltage so as to generate a first summing voltage, wherein the first summing voltage is equal to a sum of the first loop voltage and the first feedback voltage; a quantizer, for outputting a digital output signal according to the first summing voltage; and a current Digital to Analog Converter (DAC), for generating the first feedback current according to the digital output signal. | 11-24-2011 |
| 20110309959 | METHOD FOR IMPROVING THE RESOLUTION AND FOR CORRECTING DISTORTIONS IN A SIGMA-DELTA MODULATOR, AND SIGMA-DELTA MODULATOR IMPLEMENTING SAID METHOD - In a method for improving resolution and for correcting distortions for a sigma-delta modulator, a modulator converts an analog input signal into a secondary output digital signal sampled at a frequency f | 12-22-2011 |
| 20110309960 | POWER SUPPLY APPARATUS FOR TEST APPARATUS - A power supply apparatus is provided for a test apparatus configured to supply a power supply signal to a DUT. An A/D converter performs analog/digital conversion of an analog observed value that corresponds to a power supply signal so as to generate a digital observed value. A digital signal processing circuit generates, by means of digital processing, a control value adjusted such that the digital observed value received from the A/D converter matches a predetermined reference value. A D/A converter performs digital/analog conversion of the control value, and supplies the resulting value to the DUT as the power supply signal. A digital signal processing circuit is configured to be capable of changing the content of its signal processing. | 12-22-2011 |
| 20110316729 | COMPLEX BANDPASS DELTASIGMAAD MODULATOR AND DIGITAL RADIO RECEIVER - To provide a complex bandpass ΔΣAD modulator capable of suppressing the influence of an image component caused by a mismatch between I- and Q-channels on a signal component with low power consumption. | 12-29-2011 |
| 20120001781 | Digital Background Calibration System and Method for Successive Approximation (SAR) Analogue to Digital Converter - The invention provides a digital background calibration system and method for a successive approximation analog-to-digital converter comprising a digital to analog converter (DAC) having a plurality of weighted capacitors to be calibrated; means for splitting each of said weighted capacitors into a plurality of sub-capacitors and at least one redundant capacitor; means for multiplying the voltage level of at least one of the sub-capacitors with a PN sequence; and means for calibrating the weighted capacitor from the multiplied sub-capacitor and the redundant capacitor. | 01-05-2012 |
| 20120001782 | Delta Sigma ADC - A ΔΣADC is provided that is capable of suppressing increase of a circuit scale without losing noise shaping function even when a switching speed of a switch for performing time-division process is lower than a sampling rate of the ΔΣADC. For a code values provided by a comparator ( | 01-05-2012 |
| 20120026023 | SUCCESSIVE APPROXIMATION AD CONVERSION CIRCUIT - A successive approximation AD conversion circuit has improved conversion accuracy without prolonging the time necessary for conversion. The successive approximation AD conversion circuit includes a plurality of amplifier stages cascaded together through coupling capacitances, and a comparator circuit which determines whether an input analog voltage is greater or less than comparison voltages. The comparator circuit includes a first comparator unit and a second comparator unit having a common initial amplifier stage among a plurality of amplifier stages, and, respectively, a first amplifier stage and second amplifier stage connected after the common stage through respective coupling capacitances; and first and second comparison point shift circuits connected respectively to input terminals of the first and second amplifier stages. The first and second comparison point shift circuits are configured to shift the comparison voltages by a specified amount in opposite directions, when amplifying the potential difference between the input analog voltage and the comparison voltages. | 02-02-2012 |
| 20120032824 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER, AND OPERATING CLOCK ADJUSTMENT METHOD THEREFOR - A successive approximation register analog-to-digital converter includes: a digital-to-analog converter to generate an analog voltage based on an input voltage sampled in accordance with a sampling clock and a digital code; a comparator to receive the analog voltage; a controller to generate the digital code based on an output of the comparator; a delay circuit to delay a signal based on the output of the comparator and to feed back the delayed signal to a reset terminal of the comparator; an adjustment circuit to count a number of edges of a signal generated in a loop that feeds back the delayed signal, and to adjust an amount of delay of the delay circuit based on a count value; and a sampling clock generation circuit to generate the sampling clock based on the signal generated in the loop and the external clock signal. | 02-09-2012 |
| 20120038498 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATING THE SAME - To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction. | 02-16-2012 |
| 20120038499 | SIGNAL STATISTICS AND COMPRESSION-BASED ANALOG-TO-DIGITAL CONVERTERS - A method of adaptively and losslessly quantizing an analog signal to a digital signal in an analog-to-digital converter (ADC), is disclosed. According to one embodiment, the quantizing is based on one or more of an instantaneous amplitude of the analog signal, frequencies of the analog signal, and patterned contents of the analog signal, and the method comprises sampling the analog signal; quanitizing the analog signal by a quantizer core, wherein the quantizer core comprises a digital-to-analog converter (DAC), a comparator, and a voltage reference, wherein the quantization is one of efficient lossless and adaptive compression quantization, or a traditional quantization method; determining by an analog compression engine (ACE) whether the sampled analog signal is above or below a defined threshold, wherein the defined threshold includes one or more of an amplitude threshold, a frequency threshold, and a patterned adaptive threshold; adaptively manipulating the sampled signal mathematically through at least one of the DAC or voltage reference of the quantizer core; and outputting the digital signal. | 02-16-2012 |
| 20120044100 | CONTINUOUS TIME SIGMA-DELTA A/D CONVERTER AND ELECTRICAL SYSTEM COMPRISING THE A/D CONVERTER - A continuous time sigma-delta analog-to-digital converter comprising: a summator of an input analog signal and a feedback signal; a feed-forward integrator path connected to the summator and configured to provide a digital signal; a feedback digital-to-analog converter to convert the digital signal into a feedback analog signal; a feedback low pass filter structured to filter the feedback analog signal and provide the feedback signal to the summator. | 02-23-2012 |
| 20120056765 | METHOD FOR CONTROLLING THE LOOP DELAY IN A SIGMA-DELTA MODULATOR, AND SIGMA-DELTA MODULATOR IMPLEMENTING SAID METHOD - In a method for controlling the loop delay in a sigma-delta modulator having a loop including an integrator, an analog-to-digital converter, a digital-to-analog converter, and an adder-subtractor, at least one phase-control programmable digital command representing a phase shift is applied to one of the clock signals of the converters of the loop to adjust the relative phase between a clock signal of the analog-to-digital converter and a clock signal of the digital-to-analog converter. A sigma-delta modulator for converting an analog signal implements the method. | 03-08-2012 |
| 20120056766 | NON-LINEARITY CORRECTION THAT IS INDEPENDENT OF INPUT COMMON MODE, TEMPERATURE VARIATION, AND PROCESS VARIATION - In pipeline analog-to-digital converters (ADCs) the third harmonic can degrade the performance of the ADC, and conventional circuits that attempt to cancel this third harmonic are oftentimes sensitive to process variation, temperature variation, and common mode variations. Here a correction circuit is provided that includes a compensator that adjusts control voltages for MOS capacitors to generally ensures that the difference between the gate-source voltages and threshold voltages of MOS capacitors is generally maintained across variations of process, temperature, and common mode. | 03-08-2012 |
| 20120068865 | FAST DATA WEIGHTED AVERAGE CIRCUIT AND METHOD - A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer. | 03-22-2012 |
| 20120075128 | SUCCESSIVE APPROXIMATION A/D CONVERTER - A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error. | 03-29-2012 |
| 20120081243 | DIGITAL-TO-ANALOG CONVERTER, ANALOG-TO-DIGITAL CONVERTER INCLUDING SAME, AND SEMICONDUCTOR DEVICE - Provided are a capacitor digital-to-analog (DAC), an analog-to-digital converter (ADC) including the capacitor DAC, and a semiconductor device. The DAC includes at least one dummy capacitor configured to cause capacitors included in a capacitor array to have a capacitance that is an integer multiple of the capacitance of a unit capacitor. | 04-05-2012 |
| 20120112936 | QUANTIZATION CIRCUIT HAVING VCO-BASED QUANTIZER COMPENSATED IN PHASE DOMAIN AND RELATED QUANTIZATION METHOD AND CONTINUOUS-TIME DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER - A quantization circuit includes a quantizer and a compensation circuit. The quantizer includes a voltage-to-phase converter and a phase difference digitization block. The voltage-to-phase converter is arranged for generating a phase signal according to an input voltage. The phase difference digitization block is arranged for generating a quantization output according to a phase difference between a phase of the phase signal and a reference phase input. The compensation circuit is arranged for applying compensation to the phase difference digitization block according to the quantization output. | 05-10-2012 |
| 20120112937 | ANALOG-TO-DIGITAL CONVERSION DEVICE AND ANALOG-TO-DIGITAL CONVERSION METHOD - An analog-to-digital conversion device which converts an analog input signal into a digital signal and output it includes a signal characteristic detection unit for detecting a predetermined characteristic of the input signal; a control signal generation unit for setting a resolution based on the signal characteristic detected by the signal characteristic detection unit, generating a control signal that indicates only an operation required for performing the analog-to-digital conversion at the resolution, and outputting it; and an analog-to-digital conversion unit for restricting the operation based on the control signal and converting the input signal into the digital signal at the set resolution. | 05-10-2012 |
| 20120112938 | A/D CONVERTER CIRCUIT, ELECTRONIC APPARATUS AND A/D CONVERSION METHOD - An A/D converter circuit includes a comparison circuit that performs a process to compare an added signal of a sampled signal of an input signal and a code signal with a D/A output signal, or a process to compare the sampled signal with an added signal of the D/A output signal and the code signal, a control circuit that outputs output data obtained based on successive approximation result data and the code data as A/D conversion data of the input signal, a first D/A converter circuit that D/A converts the data for successive approximation, a second D/A converter circuit that D/A converts code data that changes over time, and a correction section that performs a correction process, to correct the successive approximation result data so as not to overflow due to code shifting using the code data. | 05-10-2012 |
| 20120119929 | INTEGRATORS FOR DELTA-SIGMA MODULATORS - Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier. | 05-17-2012 |
| 20120127004 | A/D CONVERSION INTEGRATED CIRCUIT - An A/D conversion integrated circuit including a plurality of A/D converters which can inhibit noises from being propagated by capacitive coupling from a conductor which transmits a digital signal is provided. In an A/D converter | 05-24-2012 |
| 20120133534 | Analog-to-Digital Converter - In a successive approximation ADC, resolution is limited because a distortion occurs in an A/D conversion result due to a voltage dependence of a sampling capacitance. An A/D converter includes a sampling capacitor part in which capacitors equal in capacitance value to each other are connected inversely, a successive approximation A/D conversion part that conducts A/D conversion on the sampling charge, a digital correction part that corrects capacitance variation of internal DAC capacitors in the successive approximation A/D conversion part, and a digital correction part that digitally corrects a third-order or more factor of a voltage dependence of the sampling charge. | 05-31-2012 |
| 20120133535 | Interleaved Pipelined Binary Search A/D Converter - The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed. | 05-31-2012 |
| 20120139764 | Continuous Time Sigma-Delta ADC with Embedded Low-Pass Filter - A filtering analog to digital converter (ADC) includes an integrator receiving at its input an analog input signal. A filtering capacitor at the input of the integrator filters out a large portion of out-of-band interferers in the analog input signal. The integrator produces an output that is quantized to produce a digital output. A feedback path between the quantizer output and the integrator input includes a digital to analog converter (DAC). | 06-07-2012 |
| 20120146819 | SIGMA-DELTA DIFFERENCE-OF-SQUARES LOG-RMS TO DC CONVERTER WITH FORWARD PATH MULTIPLIER AND CHOPPER STABILIZATION - A sigma-delta (ΣΔ) difference-of-squares LOG-RMS to digital converter for true RMS detection by merging a ΣΔ modulator with an analog LOG-RMS to DC converter based on a difference-of-squares. Chopper-stabilization, implemented through commutators running at two different frequencies, can be employed to reduce sensitivity to DC offsets and low-frequency errors, resulting in an extension of the useful input-referred dynamic range. High-order ΣΔ LOG-RMS converters can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The resulting implementations are ΣΔ difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range. | 06-14-2012 |
| 20120146820 | PIPELINED ANALOG DIGITAL CONVERTOR - Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to measure and correct a pipelined conversion stage gain error and an offset error due to a finite voltage gain operational amplifier and capacitor mismatch. The pipelined analog-to-digital converter includes a pipelined conversion stage error measuring and correcting circuit measuring and correcting an error generated from an conversion stage, so that an error of a conversion stage is minimized and a chip realization area and power consumption are reduced. | 06-14-2012 |
| 20120146821 | PIPELINED ANALOG DIGITAL CONVERTOR - Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit. | 06-14-2012 |
| 20120146822 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD USING THE SAME - A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes a Sample-and-Hold Amplifier (SHA) for sampling and holding an externally input analog voltage, a comparator for comparing a level of the sampled and held analog voltage with a level of an analog signal corresponding to n bits and generating a comparison signal according to result of comparison, an SAR logic circuit for sequentially generating a digital signal from a Most significant Bit (MSB) to a Least Significant Bit (LSB) in response to the comparison signal, a Digital-to-Analog Converter (DAC) for providing the analog signal to the comparator, and an output register for holding the sequentially generated digital signal from the MSB to the LSB to generate an n-bit digital signal, wherein, upon externally receiving a start signal, the SAR logic circuit generates a digital signal of a MSB having a one-bit phase delay compared with the start signal. | 06-14-2012 |
| 20120161990 | INTEGRATOR AND OVERSAMPLING A/D CONVERTER HAVING THE SAME - A high order integrator is configured using an operational amplifier, a first filter connected between an input terminal of the integrator and an inverted input terminal of the operational amplifier, and a second filter connected between the inverted input terminal and output terminal of the operational amplifier. The first filter includes n serially-connected first resistance elements, n-1 first capacitance elements each connected between each interconnecting node of the first resistance elements and the ground, and n-1 second resistance elements each connected between each interconnecting node of the first resistance elements and the ground. The second filter includes n serially-connected second capacitance elements, n-1 third resistance elements each connected between each interconnecting node of the second capacitance elements and the ground, and n-1 third capacitance elements each connected between each interconnecting node of the second capacitance elements and the ground. | 06-28-2012 |
| 20120161991 | Offset Cancellation For Analog To Digital Converters - An offset cancellation circuit for canceling an offset voltage in an amplifier is provided herein. The offset cancellation circuit includes a current source configured to provide an offset current, a switching stage comprising first and second switches, and a cascode stage. The cascode stage comprises a first cascode device configured to receive the offset current from the first switch and inject the offset current into a first differential end of the amplifier, and a second cascode device configured to receive the offset current from the second switch and inject the offset current into a second differential end of the amplifier. Offset voltages are common to many differential circuits as a result of mismatch. The injection of current by the offset cancellation circuit can reduce or eliminate an offset voltage, while the cascode stage can prevent parasitic capacitance associated with the offset cancellation circuit from creating further mismatch. | 06-28-2012 |
| 20120169520 | A/D CONVERSION DEVICE AND RADIO DEVICE - This A/D convertor includes: a first D/A conversion unit configured to sample an analog input signal, and to generate a first difference signal by performing successive comparison of the analog input signal based on a reference voltage; a precharge capacitor unit configured to hold the reference voltage; a first comparing unit configured to compare the first difference signal with a reference value to generate a first digital signal; and an amplifying unit configured to calculate by using the first difference signal and the reference voltage to generate a residual signal. | 07-05-2012 |
| 20120188107 | CONTINUOUS-TIME OVERSAMPLED CONVERTER HAVING ENHANCED IMMUNITY TO NOISE - An apparatus includes a clock source and an oversampled continuous-time digital-to-analog converter. Noise signal is added to the clock signal as the clock signal is generated and/or routed. The oversampled continuous-time digital-to-analog converter includes a sigma-delta modulator to perform noise shaping on input data samples and provide intermediate data samples; a filter to filter the intermediate data samples and generate filtered samples, the filter having a transfer function that has a stop band at a frequency range that includes the frequency of the noise signal or a component of the noise signal; and a continuous-time digital-to-analog converter to convert the filtered samples to an output analog signal. | 07-26-2012 |
| 20120194364 | ANALOG-TO-DIGITAL CONVERTING SYSTEM - A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate. | 08-02-2012 |
| 20120194365 | DELTA-SIGMA MODULATOR AND SIGNAL PROCESSING SYSTEM - A ΔΣ0 modulator includes: a plurality of integrators cascaded to an input of an analog signal; a quantizer for quantizing an output signal of the integrator at a last stage and outputting a resultant digital signal; a DA converter for feedback for converting the digital signal obtained by the quantizer into an analog signal and supplying the analog signal to an input side of at least the integrator at a first stage; and an adder, arranged at an input stage side of the integrator at the last stage, for adding an output of the integrator at a preceding stage of the integrator at the last stage to at least one path signal supplied from at least another path via a first resistor having at least a first coefficient. The integrator at the last stage includes an operational amplifier, an integration capacitor, and a second resistor having a second coefficient. | 08-02-2012 |
| 20120194366 | MULTI-BIT DIGITAL TO ANALOGUE CONVERTER AND A DELTA-SIGMA ANALOGUE TO DIGITAL CONVERTER - The present invention relates to a multi-bit digital to analogue converter (DAC) and to a delta-sigma analogue to digital converter employing such a DAC. The DAC has a multi-bit input, a plurality of elements for processing an input signal received at the input and a selector for selecting, based on the input signal, one or more of the DAC elements to process the signal. The DAC has control means for controlling the selector such that if the input to the DAC is below a predetermined level for a predetermined period of time the selector is operative to select only a single one of the DAC elements to process the input signal. Also disclosed is a delta-sigma analogue to digital converter (ADC) employing such a DAC. | 08-02-2012 |
| 20120200437 | DELTA-SIGMA MODULATOR AND SIGNAL PROCESSING SYSTEM - Disclosed herein is a delta-sigma modulator including: a plurality of integrators configured to be connected in cascade to the input of an analog signal; a quantifier configured to quantify an output signal from the final-stage integrator among the plurality of integrators so as to output a digital signal; a zero-order feedback path configured to compensate for an internal loop delay in the output of the quantifier; and a voltage output type digital-analog converter configured to be located on the zero-order feedback path and to convert the output digital signal from the quantifier into an analog signal, wherein the voltage output type digital-analog converter is connected in capacity to the final-stage integrator and switches an output amplitude in accordance with a calibration code that is supplied. | 08-09-2012 |
| 20120200438 | SIGNAL PROCESSING CIRCUIT - A signal processing circuit includes a production part configured to produce a first analog signal, an A/D conversion part configured to convert the first analog signal output from the production part to a first digital signal, a processing part configured to process the first digital signal output from the A/D conversion part into a second digital signal, and a D/A conversion part configured to convert the second digital signal to a second analog signal and output the second analog signal via an output terminal. | 08-09-2012 |
| 20120206281 | SELF-HEALING ANALOG-TO-DIGITAL CONVERTERS WITH BACKGROUND CALIBRATION - Calibration of an analog-to-digital converter (ADC) is accomplished via a reference comparator, a first and second multiplexer (MUX), and a finite state machine (FSM). By sampling an analog input with the reference comparator and comparing the results with those of the ADC using the FSM, all the comparators in the ADC can be calibrated without interrupting the ADC's normal operation. The first MUX provides a same reference voltage to the reference comparator as a comparator selected for the calibration, and the second MUX provides the FSM with the output of the selected comparator. The FSM then performs a comparison of the reference comparator and the selected comparator, extracts the polarity of the mismatch, and updates the contents of a memory with the extracted polarity. An offset control in the selected comparator receives a signal corresponding to the extracted polarity stored in the memory and injects offset current into the comparator. | 08-16-2012 |
| 20120212356 | Tracking analog-to-digital converter (ADC) with a self-controlled variable clock - A tracking analog-to-digital converter “ADC” with a self-controlled variable clock comprises: a digital register; a digital-to-analog converter “DAC” coupled to said digital register providing an analog feedback signal; a comparator coupled to an analog input signal and said analog feedback signal and providing a comparison signal based on a comparison between said analog input signal and said analog feedback signal, said comparison signal being coupled to the digital register; a means for determining comparator readiness to determine if said comparator is ready, indicating that said comparison signal can be reliably read, said means for determining comparator readiness further comprising a determination of a comparison ready indicator; a means for clocking to generate a clock signal to drive said digital register in response to said means for determining comparator readiness determining that said comparator is ready; and said digital register being configured to count in response to said clock signal based on said comparison signal of the comparator. | 08-23-2012 |
| 20120212357 | D/A CONVERSION CIRCUIT, A/D CONVERSION CIRCUIT AND ELECTRONIC APPARATUS - A D/A conversion circuit includes a first D/A converting section which is connected with an output node, a first serial capacitor which is disposed between the output node and a first node, a second D/A converting section which is connected with the first node, and a control circuit. The first D/A converting section includes a first capacitor array section and a first switch array section. The second D/A converting section includes a second capacitor array section and a second switch array section. The control circuit performs a switch control for dynamically changing allocation of the capacitors to the respective bits of input digital data for the first switch array section of the first D/A converting section. | 08-23-2012 |
| 20120229313 | ANALOG TO DIGITAL CONVERTER CIRCUIT - The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design | 09-13-2012 |
| 20120249348 | PIPELINED ADC HAVING ERROR CORRECTION - A pipeline stage of a pipelined analog-to-digital converter (ADC) circuit can include an ADC to convert an analog input to a digital output, a first plurality of digital-to-analog converters (DACs) sufficient in number to produce an analog output corresponding to the digital output, and a second plurality of DACs configured to have their output added into the analog output, where a succeeding pipeline portion can convert the amplified analog residue to at least one second digital output and a digitized residue. A mapping circuit can selectively exchange inputs between a selected one of the first plurality of DACs and one of the second plurality of DACs, and a calibration signal circuit can provide first and second calibration signals to inputs of the selected one of the first plurality of DACs and another of the second plurality of DACs. The calibration signals can be correlated to each other, but uncorrelated to the analog input and digital output of the first pipeline stage, and have unequal effects on the amplified analog residue or the digitized residue. A correction circuit can correct the digital output of the pipeline stage for circuit path errors in circuit paths including the first plurality and second plurality of DACs based on the results of a correlation between the calibration signals and the second digital output or digitized residue. The effects, on the amplified analog residue or the digitized residue, of the first and second calibration signals, upon travelling through the selected one of the first plurality of DACs and the other of the second plurality of DACs, can at least partially offset each other. | 10-04-2012 |
| 20120249349 | FIELD DEVICE CONTROLLING SYSTEM - A device monitoring unit obtains, through respective digital communication routes, a combination of a digital setting value for an analog output value to an analog communication route in a field device, a digital value of an AD converting device in an input/output unit, and one of the digital setting values stored in a memory of the input/output unit, to check the status of the communication through the analog communication route based on the values obtained. | 10-04-2012 |
| 20120256772 | Hardware Efficient On-Chip Digital Temperature Coefficient Voltage Generator and Method - An on-chip DC voltage generator and hardware efficient method provide for generating linear DC voltages with a programmable negative temperature coefficient. A temperature-dependent DC voltage is digitally derived from an on-chip temperature readout, a programmable digital word to control the temperature coefficient and a programmable digital word to adjust the digital level. The digital result is applied to a resistor string digital to analog converter (DAC) to generate an analog DC voltage with a negative temperature slope. Additionally, another programmable digital word for trimming allows convergence at a given temperature of voltages having a common level but different temperature coefficients. These voltages can be applied to the word line in the flash memory and track the threshold voltage of the memory cell, which has a negative temperature coefficient, such that the difference between the gate voltage and the threshold voltage is constant over temperature. | 10-11-2012 |
| 20120262315 | SELF-TIMED DIGITAL-TO-ANALOG CONVERTER - A tracking module that tracks the operation of a digital-to-analog converter (DAC). The DAC tracking module may be included on-chip with a DAC, and be formed with similar circuit components as a DAC. The DAC tracking circuit may output a signal indicating that the DAC within a SAR ADC has settled to an approximate value during each bit conversion. A differential solution is also provided. Power may be optimized because optimal conversion speed may be achieved, and a comparator within the DAC may be turned off or placed in a standby mode at the end of bit conversions, and before the next conversion cycle in response to the signal output by the DAC tracking module. | 10-18-2012 |
| 20120262316 | METHOD TO REDUCE VOLTAGE SWING AT COMPARATOR INPUT OF SUCCESSIVE-APPROXIMATIONS-REGISTER ANALOG-TO-DIGITAL CONVERTERS - A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations. | 10-18-2012 |
| 20120262317 | SYSTEM INCLUDING FEEDBACK CIRCUIT WITH DIGITAL CHOPPING CIRCUIT - A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The digital to analog converter circuit is configured to convert an error signal into an analog signal that is received by the second circuit to reduce ripple error. | 10-18-2012 |
| 20120274488 | PRE-CHARGED CAPACITIVE DIGITAL-TO-ANALOG CONVERTER - Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors. | 11-01-2012 |
| 20120274489 | SUCCESSIVE APPROXIMATION REGISTER ADC WITH A WINDOW PREDICTIVE FUNCTION - A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC. | 11-01-2012 |
| 20120280841 | Zero-power sampling SAR ADC circuit and method - A switched-capacitor circuit ( | 11-08-2012 |
| 20120280842 | System and Method For Supporting Different Types of Oscillator Circuits - In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module. | 11-08-2012 |
| 20120280843 | BROADBAND DELTA-SIGMA ADC MODULATOR LOOP WITH DELAY COMPENSATION - An exemplary delta-sigma modulator loop applied to convert a continuous-time input signal into a discrete-time output signal. The delta-sigma modulator loop includes a conversion unit, a sampling unit, a quantization unit, a compensation unit, and a digital-to-analog converter unit. The conversion unit converts an error signal relevant to the input signal through a transfer function to generate a converted signal. The sampling unit samples the converted signal to generate a sampling signal. The quantization unit quantizes the sampling signal to obtain the output signal. The compensation unit receives the output signal and compensates a time delay of the received output signal to generate a compensation signal. The digital-to-analog converter unit is electrically coupled to the compensation unit and the conversion unit to convert the compensation signal to generate a feedback signal for regulating the error signal. | 11-08-2012 |
| 20120286980 | Analog-to-Digital Converter with a Resolution Booster - An analog-to-digital converter with a resolution booster is provided. The analog-to-digital converter may include a successive approximation analog-to-digital converter, a resolution booster, and an output combiner. The successive approximation analog-to-digital converter may be configured to convert an analog signal into digital data. The resolution booster may be selectively activated to enhance the resolution of the successive approximation analog-to-digital converter, and the output combiner may be configured to combine the respective outputs of the successive approximation analog-to-digital converter and the resolution booster. | 11-15-2012 |
| 20120293345 | Successive Approximation Register (SAR) Analog-To-Digital Converter (ADC) Having Optimized Filter - A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path. | 11-22-2012 |
| 20120293346 | OFFSET CORRECTION DEVICE OF COMPARATOR - A comparator offset correction device opens an open switch | 11-22-2012 |
| 20120299758 | AMPLIFYING CIRCUIT AND ANALOG DIGITAL CONVERSION CIRCUIT WITH THE SAME - An analog to digital converting device includes a first digital conversion (ADC) circuit configured to convert an inputted analog signal into a first digital signal, a first multiplying digital to analog converting (MDAC) circuit configured to amplify a difference between a first converted signal and the inputted analog signal, a second ADC circuit configured to convert an output of the first MDAC circuit into a second digital signal, a second MDAC circuit configured to amplify difference between a second converted signal converted from the second digital signal and the output of the first MDAC circuit, a third ADC circuit configured to convert an output of the second MDAC circuit into a third digital signal, and a common amplifying circuit shared by the first and the second MDAC circuits, wherein the common amplifying circuit consumes current based on which MDAC circuit the common amplifying circuit operates with. | 11-29-2012 |
| 20120306671 | MEASUREMENT METHOD AND APPARATUS FOR ADC CALIBRATION - An uncalibrated converter element in an analog-digital converter may be replaced with two or more smaller elements having an effective total net value that is equal to that of the uncalibrated converter element. In an exemplary case where the element is capacitor, one or more of these smaller capacitors may be independently calibrated by switching the smaller capacitor between two voltages, such as a reference voltage and ground, and then calculating a difference of corresponding digital output codes generated by the backend ADC with previously calibrated capacitors associated with lesser significant bits. The total capacitance of the uncalibrated capacitor may be apportioned between the smaller capacitors so that the individual maximum charge contribution of each smaller capacitor to the converter output together with any expected manufacturing variance does not exceed the aggregated contribution of the previously calibrated capacitors. | 12-06-2012 |
| 20120319877 | SYSTEM AND METHOD OF ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system. | 12-20-2012 |
| 20120319878 | Analog-to-Digital Converter - A current input analog-to-digital converter and a corresponding current measurement circuit is disclosed. In accordance with one example of the invention, an analog-to-digital conversion circuit includes a register for storing a digital register value and a digital-to-analog converter that is configured to provide a reference current at a circuit node which is set in accordance to the digital register value. The electric potential of the input node is responsive to the reference current set. A comparator circuit is configured to compare the potential of the circuit node with at least one threshold, thus assessing whether the potential of the circuit node is at least approximately at a desired value. Control circuitry is responsive to the comparator circuit and is configured to adjust the digital register value stored in the register and to adjust the reference current until the comparator indicates that the potential of the circuit node does not deviate from the desired value. | 12-20-2012 |
| 20120326900 | SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER AND CONVERSION METHOD THEREOF - A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result. | 12-27-2012 |
| 20130002459 | Modified Dynamic Element Matching For Reduced Latency In A Pipeline Analog To Digital Converter - A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors. | 01-03-2013 |
| 20130009795 | NOISE SHAPING FOR DIGITAL PULSE-WIDTH MODULATORS - A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output. | 01-10-2013 |
| 20130009796 | CLOCK GENERATOR CIRCUIT FOR SUCCESSIVE APPROXIMATIOM ANALOG TO-DIGITAL CONVERTER - A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio. | 01-10-2013 |
| 20130015987 | MIMO DELTA-SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER USING NOISE CANCELINGAANM Shabra; AymanAACI WoburnAAST MAAACO USAAGP Shabra; Ayman Woburn MA US - A multi-input-multi-output-system (MIMO) is provided that includes a first input signal and a second input signal. A plurality of analog-to-digital converter (ADC) cell structures receive as input a combination of the first input signal and the second input signal as well as a combination of quantization noise signals from the respective other ADC cell structures of the plurality of ADC cell structures. The ADC cell structures generate a plurality of first output signals and the noise quantization signals. A plurality of adder modules receive the first output signals and performing either addition or subtraction on a selected combination of the first output signals, the adder modules generate a plurality of second output signals. A plurality of division modules receive the second output signals and perform a division operation on the second output signals by a predetermined factor. The division modules generate a plurality of final output signals of the MIMO. | 01-17-2013 |
| 20130015988 | Stochastic Analog-to-Digital (A/D) Converter And Method For Using The SameAANM Verbruggen; BobAACI Kessel-LoAACO BEAAGP Verbruggen; Bob Kessel-Lo BEAANM Craninckx; JanAACI BoutersemAACO BEAAGP Craninckx; Jan Boutersem BE - An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described. The A/D converter circuit includes:
| 01-17-2013 |
| 20130021180 | RECONFIGURABLE DELTA-SIGMA MODULATOR ADC USING NOISE COUPLING - A reconfigurable analog-to-digital (ADC) modulator structure that includes a plurality of ADC structures being coupled to each other through their respective noise quantization transfer functions. Each ADC structure receives as input an analog signal and each ADC structure outputting a plurality of first output signals. An adder module receives the first output signals and performs addition on the first output signals and generates a second output signal. A division module receives the second output signal and performs division on the second output signal by a predetermined factor. | 01-24-2013 |
| 20130021181 | NON-BINARY SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER - A successive approximation analog to digital converter (SA-ADC) employs a binary-weighted digital to analog converter (DAC) to perform a non-binary search in determining a digital representation of a sample of an analog signal. In an embodiment, a subset of iterations needed to convert an analog sample to a digital value is performed using non-binary search with a radix of conversion less than two. As a result, search windows in iterations corresponding to the non-binary search overlap, and correction of errors due to a comparator used in the SA-ADC is rendered possible. Error correction being possible due to the non-binary search, the comparator is operated in a low-bandwidth, and hence low-power, mode during the non-binary search. The non-binary search in combination with the binary-weighted architecture of the DAC offer several benefits such as for example, less-complex implementation, shorter conversion time, easier and compact layout and lower power consumption. | 01-24-2013 |
| 20130027231 | Modified Dynamic Element Matching For Reduced Latency In A Pipeline Analog To Digital Converter - A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC. | 01-31-2013 |
| 20130027232 | ANALOG-TO-DIGITAL CONVERTERS AND ANALOG-TO-DIGITAL CONVERSION METHODS - An analog-to-digital converter is provided and comprises a most significant bit (MSB) conversion module, a successive approximation register analog-to-digital converter (SAR ADC) module, and an operation module. The MSB conversion module receives an analog signal to be converted, and converts the analog signal to an MSB with M bits, and obtains a redundancy signal. The SAR ADC module is coupled to the MSB conversion module. The SAR ADC receives the redundancy signal and processes the redundancy signal to be a least significant bit (LSB) with N bits. The operation module is coupled to the MSB conversion module and the SAR ADC module. The operation module receives the MSB with the M bits and the LSB with the N bits and generates a first digital signal with (M+N) bits. Each of M and N is positive, and (M+N) is a positive integer. | 01-31-2013 |
| 20130033390 | ANALOG INPUT SYSTEM, ANALOG OUTPUT SYSTEM, AND ANALOG INPUT/OUTPUT SYSTEM - To increase the number of analog inputs at low cost, an analog input system includes: one or more analog slave units each connected to a bus to which a CPU unit is connected, and each including an A/D-conversion device converting an analog value outputted by an external device into a first digital value, a buffer memory buffering a second digital value to be transferred to the CPU unit, and a nonvolatile storage device containing specific information of its own unit; and an analog master unit connected to the bus and including an operation section performing operation processing based on the specific information stored in the storage device with the first digital value being used as an input, to calculate the second digital value, the master unit performing on each of the slave input units the operation processing and processing of transferring the calculated second digital value to the buffer memory. | 02-07-2013 |
| 20130038476 | Analog to Digital Converter with Dual Integrating Capacitor Systems - In one embodiment, an apparatus comprises a first capacitor system and a second capacitor system. Each capacitor system is removably coupled to the same portion of an analog to digital converter (ADC) and the same sensing circuit. Each capacitor system stores charge received through the sensing circuit when coupled to the sensing circuit and provides the charge received through the sensing circuit to the ADC for conversion into a digital value when coupled to the ADC. When the control signals are in a first state, the first capacitor system receives charge through the sensing circuit and the second capacitor system is coupled to the portion of the ADC. When the one or more control signals are in a second state, the second capacitor system is coupled to the sensing circuit to receive charge through the sensing circuit and the first capacitor system is coupled to the portion of the ADC. | 02-14-2013 |
| 20130044013 | CONFIGURABLE CONTINUOUS TIME SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter (ADC) includes a continuous time filter, a quantizer, a continuous time digital-to-analog converter, a discrete time DAC, and a switch. The quantizer has an input terminal coupled to the output terminal of the continuous time filter, and a plurality of output terminals. The continuous time DAC has a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal. The discrete time DAC has a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal. The switch has a first input terminal coupled to the output terminal of the continuous time DAC, a second input terminal coupled to the output terminal of the discrete time DAC, and an output terminal coupled to the input terminal of the continuous time filter. | 02-21-2013 |
| 20130044014 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER WITH CAPACITOR MISMATCH CALIBRATION AND METHOD THEREOF - A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits. | 02-21-2013 |
| 20130044015 | ELECTRONIC DEVICE AND METHOD FOR MEASURING DNL OF AN SAR ADC - The device comprises a successive approximation register, a capacitive digital-to-analog converter comprising a plurality of capacitors, the plurality of capacitors being coupled with a first side to a common node; a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage at the common node with another voltage level, and a SAR control stage for providing a digital code representing a conversion result. The device is configured to operate in a calibration mode, where the device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors by coupling one side of the first capacitor to the reference voltage, to perform a regular conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor and to provide the conversion result of the regular conversion cycle for calibrating the first capacitor. | 02-21-2013 |
| 20130057417 | COMPARATOR OFFSET CANCELLATION IN A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - A successive approximation analog-to-digital converter (ADC) includes an adjustable voltage source that applies an adjustable voltage to an input of a comparator of the ADC to cancel an offset of the ADC. The ADC also includes a control that suspends adjustments of the adjustable voltage when the adjustable voltage converges on the offset. The adjustable voltage source is a digital-to-analog converter. | 03-07-2013 |
| 20130057418 | PIPELINED A/D CONVERTER CIRCUIT PROVIDED WITH A/D CONVERTER CIRCUIT PARTS OF STAGES EACH INCLUDING PRECHARGE CIRCUIT - A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal. | 03-07-2013 |
| 20130069807 | COMPRESSIVE SENSE BASED RECONSTRUCTION ALGORITHM FORNON-UNIFORM SAMPLING BASED DATA CONVERTER - Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, a reconstruction algorithm is proposed for a compressive sensing successive approximation register (SAR) analog-to-digital converter (ADC). Accordingly, an analog signal is converted to a first digital signal at a sampling frequency that is less than a Nyquist frequency for the analog signal, and a second digital signal is constructed from the first digital signal with a box constrained linear optimization process such that the second digital signal is approximately equal to an analog-to-digital conversion of the analog signal at the Nyquist frequency for the analog signal. | 03-21-2013 |
| 20130082852 | ANALOG TO DIGITAL CONVERTER - An analog to digital converter converts an input analog signal to a digital representation using successive approximation logic to generate a plurality of digital values approximating the analog signal. Evaluation logic evaluates each of the digital values by converting each of the digital values in a digital to analog converter (DAC) to a DAC analog signal and comparing the DAC analog signal to the input analog signal to determine a comparison result used by the successive approximation logic to generate a next one of the digital values. An evaluation time period for one or more bits of the digital representation is longer than for one or more other bits in the digital representation. The DAC includes a resistor ladder. Reference voltages of the DAC are increased for evaluation of the least significant bit (LSB) to obtain more accurate results without increasing a number of resistors. | 04-04-2013 |
| 20130088374 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER WITH COMPARATOR INPUT TOGGLING - A successive approximation analog-to-digital converter (SA-ADC) includes a reference generator configured to output a first voltage and a second voltage; a comparator, the comparator having a positive input and a negative input thereto, the comparator being configured to receive the first voltage and the second voltage; and a comparator input toggle located between the reference generator and the comparator, wherein the comparator input toggle is configured to receive the first and second voltages from the reference generator and provide the first and second voltages to the comparator, wherein the comparator input toggle is further configured to switch between a first position, in which the first voltage is connected to the positive input, and the second voltage is connected to the negative input, and a second position, in which the second voltage is connected to the positive input, and the first voltage is connected to the negative input. | 04-11-2013 |
| 20130093609 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER WITH A DIRECT SWITCHING TECHNIQUE FOR CAPACITOR ARRAY THROUGH COMPARATOR OUTPUT AND METHOD THEREOF - A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, in which the capacitors of the capacitor array are one-to-one corresponding to the switches. The method includes the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result. | 04-18-2013 |
| 20130106628 | Digital Error Correction in an Analog-to-Digital Converter | 05-02-2013 |
| 20130106629 | MULTI-BIT SUCCESSIVE APPROXIMATION ADC | 05-02-2013 |
| 20130113638 | METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAME - A method and an apparatus for evaluating weighting of elements of a DAC and a SAR ADC using the same are provided. An equivalent weighting of each composed element is obtained by adding a reference element with a reference weighting, an auxiliary DAC, and a search circuit into the SAR ADC, and the equivalent weighting is represented by the reference weighting. The SAR ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and the successive approximation result of each input signal. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC. | 05-09-2013 |
| 20130120170 | PIPELINED ADC WITH A VCO-BASED STAGE - A method for converting an analog signal to a digital signal is provided. Initially, a digital representation of a portion of an analog signal is generated. Residue of the analog signal is then sampled at a sampling instant so as to generate a residue sample. A signal having a frequency that is proportional to the voltage of the residue sample is generated, and the signal is measured to generate coarse and fine measurements of the frequency. A digital representation of the residue sample from the coarse and fine measurements is then generated. | 05-16-2013 |
| 20130120171 | REDUCING THE EFFECT OF NON-LINEAR KICK-BACK IN SWITCHED CAPACITOR NETWORKS - A method and device involve a circuit having a switched capacitor network that is switchably connected to an input signal. A randomly determined amount of dither is injected into a circuit having a switched capacitor network that is switchably connected to an input signal. After injecting the dither, at least one correlation value is determined. The correlation value(s) indicates a degree of correlation between the injected dither and an output of the circuit. Distortion caused by an amount of charge kicked back into the circuit when the switched capacitor network is reconnected to the input signal may then be reduced. The reduction is calculated as a function of the correlation value(s). | 05-16-2013 |
| 20130120172 | METHOD AND DEVICE FOR REDUCING INTER-CHANNEL COUPLING IN INTERLEAVED AND MULTI-CHANNEL ADCs - A method and a corresponding device for reducing inter-channel coupling in a circuit having a plurality of channels includes injecting a randomly determined amount of dither into a first channel of a circuit having a plurality of channels, and after injecting the dither, obtaining an output signal of a second channel in the plurality of channels. A correlation value indicating a degree of correlation between the injected dither and the output signal is determined, and an amount of charge applied to the second channel due to cross-coupling with the first channel is reduced. The amount of the reduction is calculated as a function of the correlation value. | 05-16-2013 |
| 20130120173 | PIPELINED ANALOG-TO-DIGITAL CONVERTER - An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage. | 05-16-2013 |
| 20130127646 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (DAC) - An embodiment of a multiplying digital-to-analog converter (MDAC), an embodiment of a method for converting a digital signal to an analog signal, an embodiment of a pipelined analog-to-digital converter (ADC), and a method of converting an analog signal to a digital signal in a plurality of cascading stages. | 05-23-2013 |
| 20130127647 | SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN - A successive approximation register analog to digital converter (SAR ADC) and a method of linearity calibration therein are provided. Each composed element E | 05-23-2013 |
| 20130135125 | Electronic Device and Method for Analog to Digital Conversion Using Successive Approximation - The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value. | 05-30-2013 |
| 20130135126 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND OPERATION METHOD THEREOF - Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier. | 05-30-2013 |
| 20130135127 | PIPELINED ADC HAVING ERROR CORRECTION - A stage of a pipelined analog-to-digital converter can include first and second pluralities of digital-to-analog converters (DACs), the first plurality sufficient in number to produce a residue from the stage, the second plurality having their outputs added into an analog output of the stage. A mapping circuit can exchange inputs between selected ones of the first and second pluralities of DACs, and a calibration circuit can provide first and second calibration signals to the selected one of the first plurality and another of the second plurality of DACs. The calibration signals can correlate to each other, but be uncorrelated to an analog input and digital output of the stage, and have unequal and partially offsetting effects on the stage's residue. A correction circuit can correct the digital output of the stage for circuit path errors based on a correlation between the calibration signals and an output of a succeeding stage. | 05-30-2013 |
| 20130141260 | PIPELINE ANALOG-TO-DIGITAL CONVERTER - A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator. | 06-06-2013 |
| 20130169454 | System and Method for a Successive Approximation Analog to Digital Converter - In accordance with an embodiment, a method of performing a successive approximation analog-to-digital (A/D) conversion includes determining a voltage range of an analog input voltage in a single cycle using a multi-bit flash A/D converter, determining an initial D/A value for a successive approximation based on determining the voltage range, and successively approximating the analog input voltage. Successively approximating includes providing the initial D/A value to a D/A converter, comparing an output of the D/A converter with the analog input voltage, and determining a further D/A value based on the comparing. | 07-04-2013 |
| 20130176152 | SYSTEM AND METHOD OF ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system. | 07-11-2013 |
| 20130194114 | Analog-to-Digital Converter, Signal Processor, and Method for Analog-to-Digital Conversion - An analog-to-digital converter for converting an input signal includes a sigma-delta modulator for receiving an analog modulator input signal and for providing a digital modulator output signal and an interference cancellation loop. The interference cancellation loop includes a digital filter, a digital-to-analog converter, and a signal combiner. The digital filter is configured to amplify the sigma-delta output signal in a frequency band, attenuate the sigma-delta output signal outside the frequency band and a transition band surrounding the frequency band, and provide a filtered digital feedback signal. The digital-to-analog converter is configured to convert the filtered digital signal to a cancellation signal. The signal combiner is configured to combine the input signal with the cancellation signal resulting in the modulator input signal, in order to at least partially cancel interference signal portions within the input signal. | 08-01-2013 |
| 20130194115 | SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER - An apparatus implements analog-to-digital conversion with released requirement on the reference settling errors and improved immunity to the noise originated from the power supply, ground and the positive and negative references. It includes a comparator comparing the specified reference levels with the analog input, multi DAC sub-circuits with separate non-binary search schemes applied to and a digital control logic controlling the reference search process. No cross-talk occurs among the different non-binary search algorithms. Each redundancy scheme is localized in a respective DAC sub-circuit and covers the reference levels only in the current DAC. The non-binary search algorithms are fulfilled in the digital domain and trade the non-binary search step sizes with the number of the search steps to introduce redundancy to the reference levels. | 08-01-2013 |
| 20130194116 | CONTINUOUS-TIME INCREMENTAL ANALOG-TO-DIGITAL CONVERTER - In accordance with embodiments of the present disclosure, a continuous-time incremental analog-to-digital converter (ADC) may include a plurality of resettable integrators and a feed-in gain element. Each integrator may be configured to convert a sum of signals received at its input to a signal indicative of an integral over time of the sum of signals. The plurality of integrators may include a first-stage integrator configured to receive at its input the baseband signal and a final-stage integrator configured to produce at its output a final-stage analog signal. The plurality of integrators may be arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator. The feed-in gain element may be coupled between the input of the first-stage integrator and the input of another integrator of the plurality of integrators. | 08-01-2013 |
| 20130214944 | SWITCHED-CAPACITOR MDAC WITH COMMON-MODE HOP REGULATION - A switched-capacitor digital-to-analog converter (DAC) circuit can include first and second sets of capacitors, an amplifier, a reference signal generator and interconnecting switches. The first and second sets of capacitors can be connected to first and second analog input signals responsive to a first clock signal, and to first and second reference voltages responsive to a second clock signal and digital control signals. The amplifier can be connected to the first and second sets of capacitors in response to the second clock signal. The reference signal generator can provide to the first and second sets of capacitors, responsive to the first clock signal, a common-mode reference signal to set a common-mode voltage at inputs of the amplifier, and can include components to replicate the operation of the first and second sets of capacitors. The switched-capacitor DAC circuit can be used to implement a multiplying DAC in a pipeline analog-to-digital converter. | 08-22-2013 |
| 20130234870 | PIPELINED ADC STAGE FILTERS - A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range. | 09-12-2013 |
| 20130249718 | OVERSAMPLING A/D CONVERTER - An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier. | 09-26-2013 |
| 20130265180 | INTEGRATED CIRCUIT - A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period. | 10-10-2013 |
| 20130265181 | A/D CONVERTER CIRCUIT, ELECTRONIC APPARATUS AND A/D CONVERSION METHOD - An A/D converter circuit includes a comparison circuit that performs a process to compare an added signal of a sampled signal of an input signal and a code signal with a D/A output signal, or a process to compare the sampled signal with an added signal of the D/A output signal and the code signal, a control circuit that outputs output data obtained based on successive approximation result data and the code data as A/D conversion data of the input signal, a first D/A converter circuit that D/A converts the data for successive approximation, a second D/A converter circuit that D/A converts code data that changes over time, and a correction section that performs a correction process, to correct the successive approximation result data so as not to overflow due to code shifting using the code data. | 10-10-2013 |
| 20130278452 | SYSTEM AND METHOD OF CLOCKING LOW SAMPLE RATE ANALOG TO DIGITAL CONVERTERS WHILE MINIMIZING LINEARITY ERRORS - A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate. | 10-24-2013 |
| 20130278453 | ANALOG-TO-DIGITAL CONVERTER SYSTEM AND METHOD - An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented. | 10-24-2013 |
| 20130285843 | MULTI-BIT PER CYCLE SUCCESSIVE APPROXIMATION REGISTER ADC - A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage. | 10-31-2013 |
| 20130285844 | METHOD AND APPARATUS FOR ANALOG-TO-DIGITAL CONVERTER - Aspects of the disclosure provide an analog-to-digital converter (ADC). The ADC includes a comparator module and a digital-to-analog converter (DAC). The comparator module is configured to compare a first voltage sampled from an analog signal and a second voltage output from the digital-to-analog converter (DAC), and output a pulse to indicate a result of the comparison. The DAC is configured to enable a switching unit corresponding to a digital bit to switch a state based on the pulse, and settle the second voltage. | 10-31-2013 |
| 20130321184 | SAR Assisted Pipelined ADC and Method for Operating the Same - A method for operating a SAR assisted pipelined ADC includes enabling a SAR ADC in a current stage circuit for converting an input analog voltage into a digital code during a first time interval, resetting an operational amplifier of an MDAC in the current stage circuit during the first time interval, maintaining the SAR ADC of the current stage circuit in an enabled state for outputting during a second time interval, and enabling the MDAC in the current stage circuit during the second time interval. The method also includes enabling the SAR ADC in the current stage circuit for sampling during a third time interval and connecting the output terminal of the MDAC in the current stage circuit to the input terminal of the next stage circuit during the third time interval. The first, second, and third time intervals are continuous and do not overlap each other. | 12-05-2013 |
| 20130321185 | MULTIPLYING ANALOG-TO-DIGITAL CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER USING THE SAME - A multiplying analog-to-digital converter is provided. A sample-and-hold unit samples an analog signal, to obtain a sample level. A analog-to-digital converting unit converts the analog signal to a digital signal. A digital-to-analog converting unit converts the digital signal to a recovered signal level. A operating unit provides an output signal according to the difference between the sample level and the recovered signal level. A comparator compares a level of the output signal with an upper threshold level and a lower threshold level, and accordingly provides an indicating signal, wherein the upper and lower threshold levels define a predetermined level range. When the indicating signal indicates that the level of the output signal is outside the predetermined level range, a controller shifts a value of the digital signal and accordingly provides an adjusted digital signal. | 12-05-2013 |
| 20130321186 | SIGNAL RECEIVING DEVICE AND ELECTRONIC APPARATUS USING THE SAME - A signal receiving device and an electronic apparatus using the same are provided. The signal receiving device includes a signal conversion unit, a signal analysis unit, and an impedance unit. The signal conversion unit receives an analog input signal and converts the analog input signal into a digital input signal. The signal analysis unit receives the digital input signal and analyzes a signal characteristic thereof to generate an impedance adjustment signal. The impedance unit coupled to the signal analysis unit and a signal input terminal of the signal receiving device receives the impedance adjustment signal to dynamically adjust an input impedance of the signal input terminal. Thereby, the signal receiving device analyzes an input signal to dynamically adjust the input impedance of the signal receiving device, so as to maintain an amplitude gain of the input signal to be within a limited input range of the signal receiving device. | 12-05-2013 |
| 20130335245 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD OF ANALOG TO DIGITAL CONVERSION - An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. | 12-19-2013 |
| 20130342376 | ANALOG-TO-DIGITAL CONVERSION LOOP FOR PSI5 AND WSS SYSTEMS - An analog-to-digital conversion loop adapted to generate a digital output signal corresponding to a low-pass filtered replica of an analog input signal, including an analog adder configured to receive the input analog signal and an analog feedback signal, adapted to generate an analog error signal corresponding to the difference between the analog input signal and the analog feedback signal; an analog-to-digital converter having a nonlinear input-output conversion characteristic defining a larger quantization step the more the input to be converted differs from a null value, configured to receive the analog error signal and to generate a corresponding digital error signal a digital integrator configured to receive the digital error signal, configured to generate the digital output signal corresponding to the time integration of the digital error signal; a digital-to-analog converter, configured to receive the digital output signal and to generate the analog feedback signal as analog replica of the digital output signal. | 12-26-2013 |
| 20140015699 | System and Method for Analog to Digital (A/D) Conversion - In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels. | 01-16-2014 |
| 20140035767 | Successive-Approximation-Register Analog-to-Digital Converter and Method Thereof - A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data. | 02-06-2014 |
| 20140043175 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) - An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. | 02-13-2014 |
| 20140055291 | DATA PROCESSING SYSTEM - The present invention provides a data processing system which can increase resolution and which has excellent tracking with respect to the switching of a conversion range and is small in conversion error. The data processing system, which obtains an A/D conversion result after an n (where n: positive integer)-bit extension made to the resolution of an A/D converter, divides the input range of the A/D converter by m (2 | 02-27-2014 |
| 20140062734 | ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER - A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result. | 03-06-2014 |
| 20140062735 | ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER HAVING ADAPATIVE REFERENCE CONTROL - A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result. | 03-06-2014 |
| 20140062736 | CIRCUITRY AND METHOD FOR REDUCING AREA AND POWER OF A PIPELINE ADC - A pipeline ADC (analog-to-digital converter) ( | 03-06-2014 |
| 20140062737 | Adaptive Ternary A/D Converter for Use in an Ultra-Wideband Communication System - In an ultra-wideband communication system, a 1-trit ternary analog-to-digital converter (“ADC”) having dynamic threshold adaption and providing an output in ternary form [+1, 0, −1]. The ternary ADC includes a pair of 1-bit binary ADCs, one being configured in a non-inverting form, and one being configured in an inverting form. Each binary ADC includes an feedback network mechanism, thereby allowing for simultaneous and independent adaptation of the pair of thresholds, compensating for the effects of any DC offset that may be present. The use of a trit-based ternary encoding scheme improves system entropy. | 03-06-2014 |
| 20140070968 | REDUCING THE EFFECT OF ELEMENTS MISMATCH IN A SAR ADC - An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition. | 03-13-2014 |
| 20140077978 | BANDPASS-SAMPLING DELTA-SIGMA DEMODULATOR - An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As. | 03-20-2014 |
| 20140077979 | SUCCESSIVE APPROXIMATION AD CONVERTER - A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC. | 03-20-2014 |
| 20140091954 | Sub-gate delay adjustment using digital locked-loop - A delay locked loop (DLL) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (PFD) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal. | 04-03-2014 |
| 20140097975 | METHOD FOR ESTIMATING CAPACITANCE WEIGHT ERRORS AND SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER USING THE SAME - A method for estimating capacitance weight errors of a digital-to-analog converter and a successive approximation (SA) analog-to-digital converter (ADC) using the same are disclosed, and the SA ADC includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC. | 04-10-2014 |
| 20140125504 | DELAY COMPENSATED CONTINUOUS TIME SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER - A continuous time sigma delta analog to digital converter is provided. The continuous time sigma delta analog to digital converter may include, but is not limited to, an analog to digital converter having a feedback loop, and a feedback loop controller coupled to the analog to digital converter, the feedback loop controller configured to adjust delay in the feedback loop by controlling a variable delay component in the feedback loop. | 05-08-2014 |
| 20140167988 | DIGITAL-TO-ANALOG CONVERTER (DAC) CIRCUIT AND WEIGHT ERROR ESTIMATION/CALIBRATION METHOD THEREOF - The present invention discloses a DAC circuit and a weight error estimation/calibration method thereof. In the method, an output switching circuit dynamically selects several conversion cells (at least containing know weight conversion cells (KWCC)) as a reference conversion cell group (RCCG) from all conversion cells, and dynamically selects at least one unknown weight conversion cell (UWCC) from all UWCCs. An ADC digitalizes the difference of the output of RCCG and the sum of the outputs of the UWCCs, and inputs the result to a digital controller. The digital controller controls the input of the RCCG according to the output of the ADC to make the output of the RCCG approximate the output of the UWCC. The digital controller uses the outputs of the ADC to work out the actual weights of the UWCCs and stores the actual weights in a calibration memory. | 06-19-2014 |
| 20140184432 | ANALOG TO DIGITAL CONVERTER AND METHOD FOR EVALUATING CAPACITOR WEIGHTING OF DIGITAL-TO-ANALOG CONVERTER THEREOF - A method for evaluating capacitor weighting of an analog-to-digital (ADC) is provided. An equivalent weighting value of each composed capacitor in each sub-capacitor-array may be obtained by adding the switch device to the ADC which enables each sub-capacitor-array in a digital-to-analog (DAC) to be measured by each other. The ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and successive approximation result of each input signal. | 07-03-2014 |
| 20140197971 | SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER - Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. | 07-17-2014 |
| 20140210653 | Data-driven noise reduction technique for Analog to Digital Converters - A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τ | 07-31-2014 |
| 20140247169 | Multi-Level Sigma-Delta ADC With Reduced Quantization Levels - A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer. | 09-04-2014 |
| 20140266821 | CONTINUOUS-TIME OVERSAMPLING PIPELINE ANALOG-TO-DIGITAL CONVERTER - A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. | 09-18-2014 |
| 20140300499 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM - Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | 10-09-2014 |
| 20140327560 | SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER (SAR ADC) AND METHOD THEREOF - A SAR ADC and a method thereof are provided. Particularly, in each bit determining duration of last several bit determining durations, a comparer is used to consecutively compare a first potential with a second potential on a sampling and digital-to-analog converting circuit a plurality of times to obtain a plurality of comparison results, and then an SAR control circuit generates a corresponding output bit according to the obtained plurality of comparison results. | 11-06-2014 |
| 20140368363 | Sampling front-end for Analog to Digital Converter - A sampling front-end for analog to digital converter is presented that shares a high speed N-bit ADC at front-end and interleaves the pipelined residue amplification with shared amplifier, which achieves high speed, low power and compact area with high density capacitive DAC structure. | 12-18-2014 |
| 20150029048 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD OF OPERATING BUILT-IN SELF-TEST DEVICE FOR TESTING THE CONVERTER - Provided is a successive approximation register analog-to-digital converter (SAR ADC) including a digital-to-analog converter (DAC) generating and outputting first and second level voltages based on first and second analog input signals and a reference voltage signal; a comparator comparing the first and second level voltages and outputting a comparison signal according to a comparison result; and an SAR logic generating a digital signal based on the comparison signal, wherein the DAC includes: first and second input switches controlling reception of the first and second analog input signals, respectively; a first discharge switch connected electrically to the first input switch, the first discharge switch discharging leakage current according to an operation of the first input switch; and a second discharge switch connected electrically to the second input switch, the second discharge switch discharging leakage current according to an operation of the second input switch. | 01-29-2015 |
| 20150035689 | Multi-stage parallel super-high-speed ADC and DAC of logarithmic companding law - Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law has a voltage follower switch having zero voltage drop, and also has a lossless threshold switch group, wherein a quantization voltage of A/D conversion or D/A conversion is directly obtained through voltage-dividing resistance thereof. The ADC and DAC simplify a conversion process and reduce a conversion error. The ADC and DAC provide multi-stage multi-bit parallel super-high-speed A/D conversion and D/A conversion with logarithmic companding law of a high conversion rate and the low conversion error. | 02-05-2015 |
| 20150048958 | SIGNAL CONVERTER AND METHOD FOR OPERATING A SIGNAL CONVERTER - In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter. | 02-19-2015 |
| 20150084795 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM - Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | 03-26-2015 |
| 20150091744 | ACCURACY ENHANCEMENT TECHNIQUES FOR ADCs - Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error. | 04-02-2015 |
| 20150365100 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM - Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | 12-17-2015 |
| 20150372691 | SYSTEM AND METHOD FOR MULTI CHANNEL SAMPLING SAR ADC - A device includes a SAR, a comparator, a DAC and a multichannel passive S/H component. The multichannel passive S/H component is able to sample and hold a plurality of analog voltages in parallel. The multichannel passive S/H component is further able to serially feed the plurality of sampled and held analog voltages to the SAR, comparator and DAC, such that each analog voltage is serially converted to a digital representation. | 12-24-2015 |
| 20150381196 | METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) - Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits. | 12-31-2015 |
| 20160013803 | SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER | 01-14-2016 |
| 20160020781 | Interleaved Delta-Sigma Modulator - A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop. | 01-21-2016 |
| 20160036460 | A Frequency Selective Circuit Configured to Convert an Analog Input Signal to a Digital Output Signal - A frequency selective circuit configured to convert an analog input signal to a digital output signal comprises an analog-to-digital converter ( | 02-04-2016 |
| 20160170434 | APPARATUS AND METHOD FOR COMPENSATING OUTPUT SIGNAL | 06-16-2016 |
| 20160191070 | GENERATION OF ANALOG SIGNAL BASED ON ONE-BIT SIGNAL - An analog signal generation apparatus includes: a converter which converts an input waveform signal into a one-bit signal; a control section which, in response to a mute-off instruction, controls a pulse width time length of the one-bit signal, output from the converter, to progressively increase from zero to a target value; and a filter which converts the one-bit signal, controlled by the control section, into an analog signal. The control section may further perform, in response to a mute-on instruction, control for progressively decreasing the pulse width time length of the one-bit signal, output from the converter, from a current value to zero. The mute-off instruction is given in response to turning-on of a power supply, and the mute-on instruction is given in response to a power supply OFF instruction. | 06-30-2016 |
| 20160380644 | TELESCOPIC AMPLIFIER WITH IMPROVED COMMON MODE SETTLING - Telescopic amplifier circuits are disclosed. In an embodiment, a telescopic amplifier includes an input stage for receiving differential input signals, an output stage for outputting differential output signals at the drains of a first output transistor and a second output transistor, a tail current transistor coupled to sources of a first input transistor and a second input transistor, a common mode feedback circuit coupled to the differential output signals and outputting a common mode output signal, and a circuit element coupled between the common mode output signal and a gate of the tail current transistor. In an embodiment the circuit element is a resistor. In another embodiment the circuit element is a source follower transistor. In additional embodiments a phase margin of the common mode feedback open loop gain of the amplifier is determined by the value of the resistor. Additional embodiments are disclosed. | 12-29-2016 |
