| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341101000 | Parallel to serial | 37 |
| 20090201183 | DEVICE FOR THE PARALLEL-SERIAL CONVERSION OF SEVERAL SIGNAL PARAMETERS EACH DETECTED BY A DETECTOR - A device for parallel-serial conversion of several evaluation parameters determined respectively by a detector from detected signal values. The device includes a primary buffer memory for the synchronized buffering of each determined evaluation parameter, a synchronization unit for the generation of a synchronization signal for the synchronized buffering and a unit for the serial readout of the evaluation parameters stored in a synchronized manner in the primary buffer memory. A synchronization signal generated by the synchronization unit is derived from a release signal which provides the highest data rate of all the release signals associated respectively with the determined evaluation parameters. | 08-13-2009 |
| 20090273493 | Parallel-to-serial converter - A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit. | 11-05-2009 |
| 20090273494 | CLOCK GENERATORS FOR GENERATION OF IN-PHASE AND QUADRATURE CLOCK SIGNALS - Clock generator embodiments are provided to generate half-rate I and Q clock signals. The generators are configured to insure fan-out limitations, to insure correct phasing at startup, to reduce the number of signal inverters in a critical path, and to reduce the total number of inverter structures to thereby substantially extend generator operational frequency. An exemplary generator embodiment requires only two tri-state inverters and four inverters. These clock generators are particularly suited for variety of electronic systems such as high speed data serializers. | 11-05-2009 |
| 20090309771 | DATA TRANSMISSION CIRCUIT AND DATA COMMUNICATION SYSTEM - A data transmission circuit that converts parallel data signals into a serial data signal to transmit the serial data signal includes a clock generation circuit, an output circuit, and a shift register circuit for securely conducting data communication among internal elements regardless of the improvement in data transfer rate, the increase in manufacturing variance, the variation in power supply voltage and temperature, and the like. The clock generation circuit generates a clock signal. The output circuit is provided to output the serial data signal. The shift register circuit acquires the parallel data signals and sequentially transfers the acquired parallel data signals to the output circuit in a bitwise manner with the use of a shift operation synchronized with the clock signal from the clock generation circuit. | 12-17-2009 |
| 20100109923 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of synchronization blocks configured to sequentially synchronize a plurality of input signals swinging in a complementary metal oxide semiconductor (CMOS) region with multi-phase clock signals to output a plurality of output signals swinging in a current mode logic (CML) region, a plurality of first swing region converting blocks configured to convert the plurality of output signals to a plurality of converted output signals swinging in the CMOS region, a serialization block configured to serialize a plurality of converted output signals, thereby outputting a serialized signal swinging in the CML region, and a second swing region converting block configured to convert the serialized signal to a serialized output signal swinging in the CMOS region. | 05-06-2010 |
| 20100123609 | Parallel to Serial Conversion Circuit - A parallel to serial conversion circuit includes a plurality of switching units and a voltage output unit providing an operating voltage for the switching units. Each of the plurality of switching units is operable to receive a first clock signal and a second clock signal which have the same frequency, a phase shift exists between the first clock signal and the second clock signal for each of the switching units, and a phase difference exists between the first clock signals received by adjacent two switching units of the plurality of switching units. The plurality of switching units receive data bits of parallel data in sequence according to the phase difference, particularly, each of the plurality of switching units receives one data bit within a time window corresponding to the phase shift. In comparison with the prior art, the inventive solution implement the parallel to serial conversion using a single system clock frequency, so that the complexity and power consumption of the system is reduced. | 05-20-2010 |
| 20100289677 | CIRCUIT AND METHOD FOR PARALLEL TO SERIAL CONVERSION - A parallel to serial conversion circuit makes output data normally swing even in a high-speed operation. The parallel to serial conversion circuit includes a main selection block configured to drive an output node sequentially in response to data on a first line and data on a second line, and a subsequent selection block configured to drive the output node sequentially in response to data on a subsequent first line and data on a subsequent second line, wherein the output node is driven by inverted data of the data on the subsequent first line and inverted data of the data on the subsequent second line. | 11-18-2010 |
| 20100289678 | Parallel-to-serial data sort device - A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals. | 11-18-2010 |
| 20100302080 | APPARATUS AND METHOD FOR PROCESSING PARALLEL DIGITAL INPUT SIGNALS FROM PLURALITY OF CIRCUIT BREAKERS - An apparatus for processing digital input signals transferred from a plurality of circuit breakers includes: a plurality of signal input terminals configured to receive a plurality of digital input signals, which are generated from the plurality of circuit breakers and indicate an ON/OFF state of the plurality of circuit breakers, in parallel; a digital input signal parallel-to-serial converting unit configured to convert the parallel digital input signals from the plurality of signal input terminals into serial digital input signals, and output the converted serial digital input signals according to a control signal; and a controller configured to receive and process the serial digital input signals transferred from the digital input signal parallel-to-serial converting unit, and transmit the control signal to the digital input signal parallel-to-serial converting unit. | 12-02-2010 |
| 20100302081 | PARALLEL-SERIAL CONVERTER - There is provided a parallel-serial converter including a selector to convert parallel data to serial data, a flip-flop to which the serial data are input so as to latch the serial data, a generator to generate replica data simulating the serial data, a detector to detect a first switching point of the replica data and a second switching point subsequent to the first switching point, and a controller to control relative timings of timing converted to the serial data in the selector and timing when the serial data is latched in the flip-flop, based on the first switching point and the second switching point. | 12-02-2010 |
| 20100328117 | PARALLEL-TO-SERIAL CONVERTING CIRCUIT - A parallel-to-serial converting circuit includes a first alignment unit configured to receive and serially align parallel data included in a first group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit also includes a second alignment unit configured to receive and serially align parallel data included in a second group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit further includes a third alignment unit configured to serially align and output the serially aligned parallel data that is output from the first alignment unit and the second alignment unit. The first alignment unit and the second alignment unit drive an output node in response to activated data of received parallel data. | 12-30-2010 |
| 20100328118 | DATA TRANSMITTING CIRCUIT AND METHOD - A data transmitting circuit that converts parallel data into serial data to output the serial data, includes a first data input port that receives first parallel data at a first data rate based on a reference input clock; a second data input port that receives second parallel data at a second data rate lower than the reference input clock, a data expansion unit that generates expanded data by expanding a bit number of the second parallel data to a bit number of the first parallel data, a serial data generation unit that performs a process for generating first serial data by performing a serial conversion on the first parallel data based on the reference input clock and a process for generating second serial data by performing a serial conversion on the expanded data, and a data output port that outputs the first serial data or the second serial data. | 12-30-2010 |
| 20110057820 | DATA SERIALIZER APPARATUS AND METHODS - Some embodiments include apparatus and methods having an output line, clock nodes to receive clock signals, the clock signals being out of phase with each other, and selector circuits to receive data in parallel. In at least one embodiment, the selector circuits are responsive to the clock signals to transfer the data serially to the output line. Such apparatus and methods can also include a control unit to influence a portion of a signal that represents at least a portion of the data at the output line. Additional apparatus and methods are described. | 03-10-2011 |
| 20110063144 | DATA TRANSFER APPARATUS - A data transfer apparatus includes a clock generation unit to generate a clock signal, a control unit to output parallel data and a reset signal, and a plurality of transmission units. Each of the plurality of transmission units uses continuous rising edges of a bit clock to sample the reset signal multiple times so that a phase shift of the reset signal between the transmission units is reduced, and the phase of the frequency dividing clock is aligned in each transmission unit. | 03-17-2011 |
| 20110068959 | PARALLEL-TO-SERIAL CONVERTER AND PARALLEL DATA OUTPUT DEVICE - A parallel data output device includes a first latch circuit that latches and outputs one of at least two data signals input in parallel in accordance with a first clock signal; a second latch circuit that latches and outputs another of the at least two data signals in accordance with a second clock signal; and a phase set circuit that shifts at least one of a phase of the first clock signal and a phase of the second clock signal based on the phase of the first clock signal and the phase of the second clock signal. | 03-24-2011 |
| 20110090101 | DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS - Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons. | 04-21-2011 |
| 20110102211 | PARALLEL-TO-SERIAL CONVERSION CIRCUIT AND METHOD THEREOF - A parallel-to-serial conversion circuit for converting pieces of parallel data into serial data, and a parallel-to-serial converting method thereof include: a shifter configured to sequentially shift an initiation signal to generate a plurality of transfer activation signals; a valid duration generator configured to define valid durations of the plurality of pieces of parallel data based on a clock and the plurality of transfer activation signals; and an output unit configured to receive the plurality of pieces of parallel data whose valid duration has been defined and to drive an output in response to a piece of data from among the received parallel data whose valid duration has begun. | 05-05-2011 |
| 20110122002 | PARALLEL-SERIAL CONVERTER CIRCUIT - In a parallel-serial converter circuit of a multistage configuration, there is formed a clock propagation path so that when multistage connected data converters are operated according to the timing of a clock signal, a reference clock signal or a clock signal in which the reference clock signal has been frequency-converted, is given sequentially to the data converter of the first stage up to the data converter of the final stage. As a result, even in a case where variations occur in power supply voltage, timing deviation of data signals and clock signals input to the data converters of the second and subsequent stages can be suppressed, and parallel-serial conversion of high-speed data signals can be reliably executed. | 05-26-2011 |
| 20110156938 | DATA OUTPUT CIRCUIT - A data output circuit is presented. The data output circuit includes: a data serializer and a driver. The data serializer is configured to generate serial data using first parallel data. The driver is configured to drive the serial data to generate output data. The data serializer is also configured to generate the serial data by multiplexing second parallel data generated by changing a power domain of the first parallel data. | 06-30-2011 |
| 20110156939 | PULSE EDGE SELECTION CIRCUIT, AND PULSE GENERATION CIRCUIT, SAMPLE-HOLD CIRCUIT, AND SOLID-STATE IMAGE SENSOR USING THE SAME - A pulse edge selection circuit includes an input stage which selects and passes one clock from among a plurality of clocks and an output stage which outputs the clock to an edge detection circuit. The output stage has a combination of a plurality of NOR gates and a plurality of NAND gates, which are connected alternately, both the NOR gates and NAND gates having a plurality of input terminals. If the edge detection circuit is a type which detects falling edges of clocks and generates a pulse which rises on the falling edge of a first clock and falls on the falling edge of a second clock, a NOR gate is used as an output gate which outputs the first clock and the second clock. On the other hand, if a pulse is generated on rising edges, a NAND gate is used as an output gate. | 06-30-2011 |
| 20110181451 | PARALLEL-SERIAL CONVERTER - A parallel-serial converter includes a converter circuit that converts parallel data into serial data; a first sampling circuit that samples, according to a first clock signal, the serial data output from the converter circuit; a second sampling circuit that samples, according to a second clock signal that is an inverse of the first clock signal, replica data that is synchronized with the serial data; a third sampling circuit that samples, according to plural third signals respectively having different phases, output from the second sampling circuit; and a control circuit that controls sampling timing of the first sampling circuit, based on each output from the third sampling circuit. | 07-28-2011 |
| 20120001779 | SERIALIZER CIRCUIT - The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a pixel array, a pair of analog-to-digital converter (ADC) circuit blocks, a pair of input/output (I/O) circuit blocks coupled to the pair of ADC circuit blocks respectively, and a plurality of serial link terminals coupled to the pair of IO circuit blocks. The pixel array may comprise a plurality of chemically-sensitive pixels formed in columns and rows. Each chemically-sensitive pixel may comprise: a chemically-sensitive transistor, and a row selection device. | 01-05-2012 |
| 20120007755 | PARALLEL TO SERIAL CONVERSION APPARATUS AND METHOD OF CONVERTING PARALLEL DATA HAVING DIFFERENT WIDTHS - Various exemplary embodiments of this disclosure provide parallel to serial conversion apparatuses that includes a bit-swapping circuit that generates bit-swapped parallel data by swapping bits of input parallel data, and a parallel to serial conversion circuit that acquires M1 and M2 bits of the bit-swapped parallel data in a first and a second mode, respectively. The parallel to serial conversion circuit generates serial data by arranging the acquired bits of the bit-swapped parallel data in a first specified order in the first mode and in a second specified order in the second mode The bit-swapping circuit swaps the bits of the input parallel data such that the parallel to serial conversion circuit acquires 1st to M1-th and 1st to M2-th bits of the input parallel data in the first and second modes, respectively, and arranges the acquired bits of the input parallel data in the same order. | 01-12-2012 |
| 20120280839 | Transforming circuit and system between parallel data and serial data - A transforming circuit between parallel data and serial data includes a current source, a clock input sub-circuit, and a parallel data input sub-circuit. The clock input sub-circuit includes a first clock signal terminal and a second clock signal terminal. The transforming circuit between parallel data and serial data also includes a clock control sub-circuit and a serial data output control sub-circuit. The clock control sub-circuit includes four switching elements. A first and a third switching elements are controlled by the second clock signal terminal, and a second and a fourth switching elements are controlled by the first clock signal terminal. The serial data output control sub-circuit includes a fifth switching element and a sixth switching element to speed up the falling edge of the output signal flip, a seventh switching element and an eighth switching element to limit the output signal amplitude. A transforming system thereof is also provided. | 11-08-2012 |
| 20120280840 | MULTIPLE-MODE BROADBAND WIRELESS COMMUNICATION DEVICE AND METHOD - Provided is a multi-mode ultra broadband wireless communication apparatus and method, and a multi-mode ultra broadband transmitting apparatus may include a baseband outputting unit to parallelly output multiple digital signals, a mid-frequency processing unit to up-convert the outputted parallel digital signals to mid-frequencies, and the up-conversion is performed in a range where the outputted parallel digital signals do not cause interference with each other, a parallel-to-serial converter to convert, to a serial digital signal, the converted parallel digital signals that are up-converted to the mid-frequencies, a digital-to-analog converter to convert the serial digital signal to an analog signal, and a radio frequency processing unit to up-convert the analog signal to multiple transmission frequencies respectively corresponding to desired communication services. | 11-08-2012 |
| 20120299756 | Single Stage and Scalable Serializer - According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops. | 11-29-2012 |
| 20120313799 | PARALLEL-TO-SERIAL CONVERSION CIRCUIT, INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND PARALLEL-TO-SERIAL CONVERSION METHOD - A parallel-to-serial conversion circuit includes a plurality of parallel-to-serial conversion units, each being configured to include a dividing circuit configured to divide a clock signal having a second clock cycle to generate a clock signal having a first clock cycle, a parallel input circuit configured to input a signal having a plurality of bits parallel to one another in the first clock cycle, and a serial output circuit configured to serially output the signal having the plurality of bits input to the parallel input circuit bit-by-bit in the second clock cycle, wherein, among the plurality of parallel-to-serial conversion units, one of the dividing circuits has a synchronization signal interface that causes an output clock signal to synchronize with a clock signal output from the other dividing circuit in another parallel-to-serial conversion unit. | 12-13-2012 |
| 20130027229 | METHOD AND APPARATUS FOR SERIALIZING BITS - A circuit for serializing bits including a clock circuit and a serializer. The clock circuit may be configured to generate a plurality of clock signals from a received master clock signal. A plurality of bits may be transmitted to the serializer in response to a transition of a first clock signal. The serializer may comprise a system of latches and a rotary circuit. The system of latches may be configured to receive a first half of the plurality of bits in response to a first transition of a second clock signal and to receive a second half of the plurality of bits in response to a transition of a third clock signal. The rotary circuit may be configured to receive the plurality of bits from the system of latches and to output each bit at a particular time based on a plurality of rotary clock signals. | 01-31-2013 |
| 20130176151 | SERIALIZER - A serializer includes a clock generator configured to receive N reference clock signals (φ_) (where N is a natural number) having different phases, and generate first clock signals (φ_) and second clock signals (φd_); a logic circuit configured to generate output signals (φo_) of N parallel data pieces using the first clock signals and the second clock signals; and a drive circuit configured to serialize data corresponding to N output signals received from the logic circuit, and output the serialized data. | 07-11-2013 |
| 20130187799 | SERIALIZER AND DATA SERIALIZING METHOD - The invention provides a serializer. In one embodiment, the serializer converts parallel input data into serial output data according to a full swing clock and a noiseless differential clock, and comprises a plurality of parallel-input-serial-output (PISO) shift registers, a plurality of current-mode-logic (CML) D flip-flops, and at least one multiplexer. The PISO shift registers respectively selects a plurality of received input bits from the input bits of the parallel input data, and respectively serializes the received input bits according to the full swing clock to generate a plurality of first middle data signals. The CML D flip-flops respectively latches the first middle data signals to generate a plurality of second middle data signals. The at least one multiplexer receives the second middle data signals, and interleaves the second middle data signals according to the noiseless differential clock to generate the serial output data. | 07-25-2013 |
| 20130265179 | DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS - Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons. | 10-10-2013 |
| 20130328704 | Scalable Serializer - According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops. | 12-12-2013 |
| 20140043174 | PARALLEL-TO-SERIAL CONVERTER CIRCUIT - A first multiplexer, at each given cycle, outputs a second input data signal, after outputting a first input data signal. A second multiplexer, at each given cycle, outputs a fourth input data signal, after outputting a third input data signal. The second multiplexer outputs the third input data signal at a timing that coincides with the timing at which the second input data signal is output from the first multiplexer. At each given cycle, a third multiplexer, after outputting the first input data signal and the second input data signal output from the first multiplexer, outputs the third input data signal and the fourth input data signal output from the second multiplexer. | 02-13-2014 |
| 20140266820 | INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION - In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects. | 09-18-2014 |
| 20140285367 | CURRENT COMPENSATION CIRCUIT - A first circuit operates in synchronization with a first clock having a first frequency, and generates N parallel data sets for every cycle period of the first clock. An interface circuit time-division multiplexes the N data sets received from the first circuit. A second circuit processes the N data set thus time-division multiplexed, in synchronization with a second clock having a second frequency which is N times the first frequency. A judgment unit judges whether or not the N data sets are effective data which instructs a flip-flop group, configured as a state holding element included in the second circuit, to generate an effective state transition. In a cycle period in which the N data sets are ineffective, a data replacement unit replaces at least a part of the N data sets with current compensation data D | 09-25-2014 |
| 20150123826 | SERIALIZERS - Serializers are provided. The serializer includes a first drive control signal generator and a second drive control signal generator. The first drive control signal generator amplifies a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal. The second drive control signal generator amplifies a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal. | 05-07-2015 |
| 20160254804 | Serial data signal edge detection | 09-01-2016 |
