| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341100000 | Serial to parallel | 63 |
| 20080218389 | Serial-To-Parallel Converter Circuit and Liquid Crystal Display Driving Circuit - A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (| 09-11-2008 | |
| 20080258946 | Pattern Matching Apparatus - This invention relates to a pattern recognition correlator implemented entirely in the electronic domain. The correlator has a serial to parallel conversion means to convert input serial binary data into at least one input parallel binary electrical signal and a comparator to compare the or each input parallel data signal with a reference parallel binary data signal. The serial to parallel conversion means may comprises a demultiplexer to effectively slow the data update rate and a series of latch circuits to provide the parallel data signal. The comparator may be arranged to perform bit addition and may be arranged such that a zero total sum is an indication of correlation. The bit addition may be performed b an array of logic gates. | 10-23-2008 |
| 20080266150 | SERIAL DATA COMMUNICATION UNIT AND MEASURING DEVICE USING THE SAME - A serial data communication unit includes a parallel-serial converter for separating n-bit parallel data containing decision data into plural groups, and converting the parallel data into serial data every group to output, a serial-parallel converter for reconverting the serial data fed from the parallel-serial converter every group into the n-bit parallel data to output, and a deciding circuit into which data located in bit positions corresponding to the decision data out of the parallel data from the serial-parallel converter is input. | 10-30-2008 |
| 20080303700 | Amplifier circuit, digital-to-analog conversion circuit, and display device - Disclosed is a digital-to-analog conversion circuit in which first and second serial DACs and an amplifier circuit for driving a data line are provided. In a first data period, the first serial DAC converts a first digital signal received in the first data period to a first signal, the second serial DAC holds a signal obtained by converting a digital signal received in a data period one period before the first data period, and the amplifier circuit amplifies and outputs the signal held in the second serial DAC, to the data line. In a second data period following after the first data period, the second serial DAC converts the second digital signal received in a second data period, the first serial DAC holds the first signal converted in the first data period, and an amplifier circuit amplifies and outputs the first signal held in the first serial DAC, to the data line. | 12-11-2008 |
| 20090015449 | Serial-to-parallel conversion circuit and method of designing the same - The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data and a strobe when a first-stage memory device in a shift register latches data and when the memory device holds the data; providing a logical circuit for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period. | 01-15-2009 |
| 20090021405 | SYSTEMS AND METHODS FOR PERFORMING OFF-CHIP DATA COMMUNICATIONS AT A HIGH DATA RATE - An electronic device is described. The electronic device includes a first integrated circuit (IC) and a second integrated circuit (IC). The electronic device also includes a multiplexer configured to multiplex a parallel data signal into a serial data signal, and a transmitter configured to transmit the serial data signal from the first IC to the second IC. The electronic device further includes a receiver configured to receive the serial data signal. The receiver includes a clamp circuit configured to clamp the voltage swing of an analog node within a determined range. The clamp also helps to extend the bandwidth of the receiver. | 01-22-2009 |
| 20090027243 | MCU WITH INTEGRATED VOLTAGE ISOLATOR TO PROVIDE A GALVANIC ISOLATION BETWEEN INPUT AND OUTPUT - An integrated circuit comprises a first microcontroller unit located on a first die. The first microcontroller unit includes a first processing core for providing a parallel stream of data. A second microcontroller unit is located on a second die and includes a second processing core for receiving the parallel stream of data. Voltage isolation circuitry transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream and provides galvanic isolation between the first microcontroller unit and the second microcontroller unit. | 01-29-2009 |
| 20090040082 | DEVICE FOR PROCESSING BINARY DATA WITH SERIAL/PARALLEL CONVERSION - A device for processing binary data comprises at least one transmission link having an input for receiving a serial bit stream and an output for forwarding bits in a parallel format, and a serial/parallel converter providing n≧2 successive data bits of the serial bit stream as n-bit data words in the parallel format. The serial/parallel converter comprises a 1-to-n demultiplexer which is constructed and controllable in such a manner that the successive data bits of the serial bit stream appear in succession at intervals equal to a bit period T | 02-12-2009 |
| 20090066546 | HIGH-SPEED SERIAL INTERFACE CIRCUIT AND ELECTRONIC INSTRUMENT - A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage. The present invention can prevent a partial characteristic variation by NBTI by inputting a free-running clock into a logic block, and operating it. | 03-12-2009 |
| 20090073010 | DATA CONVERSION - A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams. | 03-19-2009 |
| 20090091480 | HIGH-FREQUENCY MODULE FOR PERFORMING EFFECTIVE PHASE COMPENSATION OF CLOCK FOR INPUT DIGITAL SIGNAL - A high-frequency module includes a high-speed logic circuit for processing an input digital signal having a transmission rate of several tens of Gbps by detecting the level of the input digital signal by using a clock having a frequency of several tens of GHz; a variable delay circuit for adding a specific amount of delay to the clock, and outputting the clock to the high-speed logic circuit, wherein the amount of delay is variably set in accordance with a manipulation signal; a phase comparator for measuring a phase difference between the input digital signal and the clock which is input into the high-speed logic circuit, and outputting a phase-difference signal in accordance with the phase difference; a filter for extracting a direct-current signal, which indicates the phase difference, from the phase-difference signal input from the phase comparator; and a controller for generating the manipulation signal assigned to the variable delay circuit, by using the direct-current signal input from the filter. | 04-09-2009 |
| 20090096644 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, PATTERN DETECTION METHOD AND SERIAL-PARALLEL CONVERSION METHOD - A shift register SR configured to successively take in and hold input serial data on the basis of a first clock signal, a pattern detection section configured to detect a predetermined pattern contained in the serial data taken in the shift resister and a second clock generation section configured to determine timing of output of the serial data held in the shift register on the basis of a result of this detection are provided to detect the desired pattern contained in the serial data in the course of transferring the serial data for conversion from the serial data to parallel data to the shift resister, and to determine timing of conversion to the parallel data on the basis of a result of this detection, thus reducing the latency and achieving an improvement in communication speed and a reduction in circuit area. | 04-16-2009 |
| 20090109071 | SERIAL DATA ANALYSIS IMPROVEMENT - A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demultiplexed into a plurality of multi-bit lanes, such as n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section at a data rate that is optimal for the receiver section. In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal. | 04-30-2009 |
| 20090128380 | Current-controlled CMOS logic family - Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C | 05-21-2009 |
| 20090135032 | DUAL PURPOSE SERIALIZER/DE-SERIALIZER FOR POINT-TO-POINT AND POINT-TO-MULTIPOINT COMMUNICATION - A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics. | 05-28-2009 |
| 20090146852 | MULTI-SPEED BURST MODE SERIALIZER/DE-SERIALIZER - A multi-speed burst mode serializer/de-serializer (SerDes). A configurable SerDes can be designed to operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. | 06-11-2009 |
| 20090167572 | Serial/Parallel data conversion apparatus and method thereof - A serial/parallel data conversion apparatus and a method thereof are used to convert serial data into parallel data by a delay pulse and three stage registers, wherein the device includes a first data register, a second data register, a third data register, a frequency divider and a delay controller. Moreover, the first data register converts the serial data into the parallel data according to a first working clock signal. The frequency divider performs a frequency division for the first working clock signal for producing a second working clock signal. The second data register acquires the parallel data from the first register according to the second working clock signal. The delay controller delays the second working clock signal to produce a third working clock signal. Finally, the third data register obtains the parallel data from the second register according to the third working clock signal. | 07-02-2009 |
| 20090167573 | Data transmission circuits and data transceiver systems - A data transmission circuit is disclosed. The transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data in synchronization with the serial clock. The transmission clock generator receives the serial clock to generate a transmission clock that has a same delay as the N-bit serial data, and the data transmission circuit simultaneously transmits the N-bit serial data and the serial clock. | 07-02-2009 |
| 20090207057 | Dual Purpose Serializer/De-Serializer for Point-To-Point and Point-To-Multipoint Communication - A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics. | 08-20-2009 |
| 20090231171 | LOW POWER SERDES ARCHITECTURE USING SERIAL I/O BURST GATING - A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. Word data bits are framed and sent along with clock pulses that define when the bits may be reliably received. High speed, typically, CTL logic is used for the transmission line drivers and together with the clock pulse, a data word is sent faster than the computer system can send the next word to the serializer/deserializer. The disclosure frames the word and detects the word end, whereupon the system is placed into the standby mode. In addition the serializer/deserializers may be placed in a master/slave arrangement where the slave can be arranged to use the master's clock to send word data bits back to the master. | 09-17-2009 |
| 20090231172 | CIRCUIT AND METHOD FOR DRIVING, ELECTRO-OPTIC DEVICE, AND ELECTRONIC APPARATUS - There is provided a driving circuit that drives an electro-optic device by outputting data signals that are subjected to serial-to-parallel conversion into m channels through m (m is a natural number greater than or equal to 2) image signal lines to a plurality of data lines. The driving circuit includes an adjusting section that adjusts the m-channel data signals so that, when a reference signal whose signal level is a reference level is input, the m-channel data signals at least partly reach signal levels different from the reference level for each channel, the number of continuous channels of signals at the same signal level is smaller than a predetermined number, and the differences between the signal levels and the reference level fall within a predetermined range. | 09-17-2009 |
| 20090243899 | Interface control circuit - An interface control circuit including a physical layer receiver, a lane receiver, a bridge circuit, a transmitter command encoder, a lane transmitter and a physical layer transmitter is provided. The physical layer receiver receives and converts serial data into parallel data, and determines to transmit the parallel data in a high speed transmission mode or a low power transmission mode according to the serial data. The lane receiver receives and decodes the parallel data. The bridge circuit outputs the decoded parallel data. If the serial data includes a read command, the transmitter command encoder encodes the parallel data. The lane transmitter receives target parallel data from the bridge circuit, and transmits the target parallel data in the low power transmission mode according to the encoded parallel data. The physical layer transmitter converts the target parallel data into target serial data and outputs the target serial data. | 10-01-2009 |
| 20090261997 | Multi-Speed Burst Mode Serializer/De-Serializer - A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds. | 10-22-2009 |
| 20100045493 | SYSTEM AND METHOD FOR FLEXIBLE PHYSICAL LAYOUT IN A HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT - A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on a value of the layout select tag. | 02-25-2010 |
| 20100079316 | Digital signal transmitting apparatus and digital signal transmitting method - A digital signal transmitting apparatus includes an encoder which converts parallel input signals of multiple channels into serial data in a manner synchronized with a first clock signal, and a decoder which converts the serial data into parallel output signals of the multiple channels in a manner synchronized with a second clock signal operating in a manner asynchronous with the first clock signal. The serial data has a different period and a different duty factor corresponding to each combination of the logical values of the parallel input signals of the multiple channels. | 04-01-2010 |
| 20100097249 | SERIAL SIGNAL RECEIVING DEVICE, SERIAL TRANSMISSION SYSTEM AND SERIAL TRANSMISSION METHOD - A serial signal receiving device, includes: a serial-parallel converter that converts a transmitted serial signal into a parallel signal, wherein the serialized signal is obtained by the plural signal; a storage unit that stores phase difference information indicating a phase difference among the plural signals; and a correcting unit that corrects a phase relation among the plural signals of the parallel signal output from the serial-parallel converter based on the phase difference information stored by the storage unit. | 04-22-2010 |
| 20100103002 | HIGH-SPEED SERIAL INTERFACE CIRCUIT AND ELECTRONIC INSTRUMENT - A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage. The present invention can prevent a partial characteristic variation by NBTI by inputting a free-running clock into a logic block, and operating it. | 04-29-2010 |
| 20100238055 | SIGNAL TRANSMISSION SYSTEM AND SIGNAL CONVERSION CIRCUIT - A signal transmission system in which a serializer IC connected to first parallel signal wirings and a deserializer IC connected to second parallel signal wirings are connected by a transmission line. Among input terminals of the serializer IC, redundant input terminals which are not connected to the first parallel signal wirings are connected to one wiring obtained by branching off the first parallel signal wirings. When parallel signals are converted into a serial signal, their bit data is arranged into the serial signal which is temporally continuous. Thus, the number of transition times of the serial signal is reduced and radiation noises can be suppressed. | 09-23-2010 |
| 20100302079 | METHOD FOR ALIGNING A SERIAL BIT STREAM WITH A PARALLEL OUTPUT - The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. | 12-02-2010 |
| 20100328116 | DEVICES FOR CONVERSION BETWEEN SERIAL AND PARALLEL DATA - Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a serial data stream. A rotator circuit may receive the delayed serial data streams and rearrange bits in the serial data streams. Register circuits may receive the output of the rotator circuit and collectively output, in parallel, a number of bits of one of the serial bit streams. | 12-30-2010 |
| 20110006932 | PROGRAMMABLE DESERIALIZER - A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first flip-flop group is controlled by a first clock signal. The second flip-flop group includes a plurality of flip-flops, where the second flip-flop group is controlled by a second clock signal, and the flip-flops of the second flip-flop group are respectively connected to output nodes of the flip-flops of the first flip-flop group. The programmable frequency divider is coupled to each of the flip-flops of the second flip-flop group, and is utilized for receiving a control signal and generating the second clock signal by performing a frequency-dividing operation according to a frequency-dividing factor set by the control signal. | 01-13-2011 |
| 20110012761 | SEMICONDUCTOR INTEGRATED DEVICE - In one embodiment, a semiconductor integrated device includes a plurality of semiconductor chips each having a first internal circuit and a second internal circuit and being stacked while displaced from each other. The first internal circuit processes a data signal in accordance with a predetermined process. The second internal circuit receives a request signal from a transmission source and determines whether the request signal is a request to itself or not. When the request signal is the request to the second internal circuit itself, the second internal circuit receives a data signal from a transmission source and outputs the data signal to the first internal circuit. When the request signal is not the request to the second internal circuit itself, the second internal circuit transfers the request signal to a transfer destination, receives the data signal from the transmission source and transfers the data signal to the transfer destination. | 01-20-2011 |
| 20110018747 | Data Generator Providing Large Amounts of Data of Arbitrary Word Length - A waveform memory | 01-27-2011 |
| 20110057819 | Semiconductor device having plural semiconductor chips laminated to each other - In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced. | 03-10-2011 |
| 20110090099 | System and method for encoding and decoding serial signals formed by a plurality of color lights - The present invention is to provide a method for encoding and decoding serial signals formed by a plurality of color lights, which is applied to an encoding/decoding system comprising an encoding device and a decoding device, and comprises steps of generating a driving signal corresponding to at least one first serial code set by the encoding device, so as to drive a multi-color LED to generate a plurality of color lights having different wavelengths and interval time of flash intervals; and receiving the color lights by the decoding device, decoding the color lights according to a decoding procedure of the decoding device for obtaining the first serial code set, and sending an actuation signal when determining that the first serial code set is identical to a second serial code set, so as to provide a variety of more sophisticated, safer and uneasy interfered encoding/decoding functions to various wireless control procedures. | 04-21-2011 |
| 20110090100 | TRANSFORMING SIGNALS USING PASSIVE CIRCUITS - Passive signal combiners are employed to transform at least one signal from one domain to another. In some aspects the transformation comprises an NFL an IFFT, a DFT, or an IDFT. In some implementations the passive signal combiners comprise a set of planar waveguides (e.g., which may be referred to as beamformers or Rotman lenses) that have multiple inputs and outputs and are configured to provide orthogonal output signals. In some implementations an electrical signal (e.g., received via an antenna element) is coupled to passive beamformers that transform the electrical signal from one domain to another domain. Here, a transformation of the electrical signal by a given passive beamformer may have a first resolution, and outputs from the passive beamformers may correspond to orthogonal groups. A combiner circuit may be used to combine the outputs from the passive beamformers and produce a combined output having a second resolution and an associated error. In some aspects, this error may be less than a cumulative error associated with the passive beamformers if a single passive beamformer was instead employed to transform the electrical signal at the second resolution. Also, by using at least partially different bandwidths for components in the circuits, a higher effective bandwidth for the transformation may be achieved. | 04-21-2011 |
| 20110109486 | PSEUDO-ORTHOGONAL CODE GENERATOR - A pseudo-orthogonal code generator is provided. The pseudo-orthogonal code generator simplifies overall configuration and provides a more efficient operating speed by implementing a pseudo-orthogonal code generator using combined circuits instead of using a read only memory (ROM) circuit. The pseudo-orthogonal code generator reduces its overall size by reducing gate area. | 05-12-2011 |
| 20110156936 | MOBILE INDUSTRY PROCESSOR INTERFACE - An optimized Mobile Industry Processor Interface (MIPI) includes a transmitter physical (PHY) layer configured to convert input data into serial data and transmit the serial data in synchronization with a high-speed clock, a receiver PHY layer configured to convert the serial data into 8-bit parallel data in synchronization with the clock received from the transmitter, a bit merge block configured to merge the parallel data received from the receiver PHY layer so as to form 32-bit data using multiple lanes and to transmit the 32-bit data to a receiver protocol layer, the receiver protocol layer being configured to decode and recognize the data received from the bit merge block. | 06-30-2011 |
| 20110156937 | Multi-Speed Burst Mode Serializer/De-Serializer - A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds. | 06-30-2011 |
| 20120038497 | Transmission Interface and System Using the Same - A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data. | 02-16-2012 |
| 20120075127 | DATA TRANSFER METHOD, AND CODE CONVERSION CIRCUIT AND APPARATUS - A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line. | 03-29-2012 |
| 20120154185 | Providing A Feedback Loop In A Low Latency Serial Interconnect Architecture - In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed. | 06-21-2012 |
| 20120154186 | LOW POWER SERIAL TO PARALLEL CONVERTER - A serial-to-parallel converter includes a sampling unit that may, in response to a serial clock signal, sample a serial data stream and provide an even serial data stream, and an odd serial data stream. The serial-to-parallel converter also includes a strobe generator and a number of latches. The strobe generator generates a plurality of enable signals based upon the serial clock signal. The frequency of a given enable signal corresponds to a fractional multiple of a frequency of the serial clock signal. In response to a particular respective enable signal, each of a first portion of the latches may latch and output a particular respective even data bit. Each of a second portion of the latches may latch and output a particular respective odd data bit. The serial-to-parallel converter further includes a number of output flip-flops to output the data bits in parallel in response to an output clock signal. | 06-21-2012 |
| 20120200436 | Method for Power Reduction in Data Serialization/De-serialization Using Data Pre-load Scheme - A method is provided for saving power in 1:N serializer and N:1 de-serializer by pre-loading the state of shift registers. Pre-loading the last stage of N shift registers with the last parallel data bit value in the multiplexor minimizes state changes in shift registers in the serializer. Pre-loading the 1 | 08-09-2012 |
| 20120223847 | Method and Apparatus for Direct Digital Synthesis of Signals Using Taylor Series Expansion - A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single adder. Values stored in the ROMs may produce one component of a sinusoid signal, and each of the ROMs may be of a different size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series expansion of a sinusoid function. | 09-06-2012 |
| 20120249347 | VARIABLE BITRATE EQUIPMENT - The present invention refers to a signal concentrator comprising:
| 10-04-2012 |
| 20130093607 | CONVERSION DEVICE - The disclosed conversion device converts an analog input signal into a digital signal and outputs thereof, wherein the conversion device comprises a feedback signal generator for performing mismatch shaping on the digital signal that has been converted and output, and then performing digital-analog conversion to generate a feedback signal; a subtractor for subtracting the feedback signal from the analog input signal and outputting thereof; a serial-parallel converter for converting the signal output from the subtractor into a plurality of parallel signals and outputting thereof; a vector filter for performing signal processing on the plurality of parallel signals output by the serial-parallel converter and outputting a plurality of signals; a quantizer for quantizing the plurality of signals output by the vector filter and outputting digital signals; and a parallel-serial converter for converting the digital signals output by the quantizer into serial signals and outputting thereof. | 04-18-2013 |
| 20130093608 | SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF - Provided are a signal processing apparatus and a signal processing method. The signal processing method include receiving a serial signal including an information frame including channel information and data information of a corresponding channel, extracting a clock signal from the serial signal, generating a load signal when a clock count reaches a maximum clock count by calculating the clock signal; converting the serial signal to a parallel signal according to the load signal, and changing the maximum clock count by comparing parallel-converted parallel channel information with a load count indicating the number of local signals. | 04-18-2013 |
| 20130127645 | SERIAL TRANSMISSION SYSTEM INCLUDING TRANSMITTER APPARATUS AND RECEIVER APPARATUS, FOR USE IN TRANSMISSION OF AV DATA - A transmitter apparatus is provided for converting parallel data of natural number n×12 bits into n pieces of serial data, and transmitting n transmission signals each of natural number m bits. In the transmitter apparatus, a dividing buffer divides inputted parallel data into n pieces of 12-bit parallel data, and an encoder circuit 12B14B-converts the n pieces of 12-bit parallel data into n pieces of 14-bit parallel data, respectively, and outputs resulting data. A parallel-to-serial converter circuit parallel-to-serial converts the n pieces of 14-bit parallel data into n pieces of 1-bit serial data, respectively, and outputs resulting data, and an m-bit driver circuit amplifies and transmits the n pieces of 1-bit serial data, as n transmission signals each of m bits, respectively, to n transmission paths. | 05-23-2013 |
| 20130141258 | HIGH-FREQUENCY SEMICONDUCTOR SWITCH AND TERMINAL DEVICE - A high-frequency semiconductor switch includes a serial-parallel conversion circuit, a power supply circuit, and a drive circuit. In the serial-parallel conversion circuit, a parallel data signal is formed from a serial data signal input thereto. In the power supply circuit, a first positive voltage, a second positive voltage, and a negative voltage are formed from a high-potential power source supplied thereto. The drive circuit is supplied with the first positive voltage, the second positive voltage, and the negative voltage, and includes an inverter to which the parallel data signal is input and a differential type of level shifter to which the parallel data signal and the output signal of the inverter is provided. The drive circuit outputs the second positive voltage as a high level signal, and the negative voltage as a low level signal, to a switching circuit, and the switching circuit performs selective switching based thereon. | 06-06-2013 |
| 20130201041 | Digital-to-Analog Converter (DAC) With Common Mode Tracking And Analog-to-Digital Converter (ADC) Functionality To Measure DAC Common Mode Voltage - A circuit includes a first circuit portion operable as a digital-to-analog converter (DAC) for generating a DAC common mode voltage signal (outp), a second circuit portion having a comparator for comparing the DAC common mode voltage (outp) against a received signal common mode voltage (vsumdc), the comparator providing a single bit output, and a single bit register configured to receive the single bit output of the comparator, the single bit output used to control a feedback circuit, the feedback circuit configured to control the DAC common mode voltage signal. | 08-08-2013 |
| 20130241751 | PROVIDING A FEEDBACK LOOP IN A LOW LATENCY SERIAL INTERCONNECT ARCHITECTURE - In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed. | 09-19-2013 |
| 20130249717 | Delaying Data Signals - In one embodiment, multiple (serializer-deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals. | 09-26-2013 |
| 20140002283 | DATA INTERFACE ALIGNMENT | 01-02-2014 |
| 20140111360 | TRANSMISSION INTERFACE AND SYSTEM USING THE SAME - A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data. | 04-24-2014 |
| 20140218221 | Techniques For Alignment of Parallel Signals - Receiver circuits in serial lanes each generate a synchronous clock signal that is aligned with a master clock signal to allow synchronous transfer of data onto the master clock domain without corruption. A serial-to-parallel converter circuit in each receiver circuit converts a serial data signal into parallel data signals in response to one of the synchronous clock signals. Phase detection circuitry generates an indication of a phase shift based on a phase offset between the synchronous and master clock signals. A clock signal generation circuit provides an adjustment to a phase of the synchronous clock signal based on the indication of the phase shift. The serial-to-parallel converter circuit adjusts positions of bits indicated by the parallel data signals based on the adjustment to the phase of the synchronous clock signal. | 08-07-2014 |
| 20140340247 | DESERIALIZERS - Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal. | 11-20-2014 |
| 20150048957 | DATA INPUT/OUTPUT DEVICE AND SYSTEM INCLUDING THE SAME - A data input/output (I/O) device includes a plurality of data units and an I/O assembly. The plurality of data units is coupled to a global I/O (GIO) line through corresponding local I/O (LIO) lines and configured to receive or transmit a plurality of data groups through the corresponding LIO lines. At least one of the plurality of data units have a different operation speed. The I/O assembly performs serial/parallel conversion operations on the plurality of data groups including a high-speed data group and outputs results of the serial/parallel conversion operations. The high-speed data group is output from the at least one of the plurality of data units having the different operation speed. | 02-19-2015 |
| 20150145707 | DIGITAL SERIAL-TO-PARALLEL CONVERTER AND GaAs MMIC USING THE SAME - A digital serial-to-parallel converter capable of minimizing a malfunction of a circuit by more stably performing an operation of a D flip flop in implementing a GaAs MMIC digital serial-to-parallel converter and a GaAs MMIC using the same are disclosed. The digital serial-to-parallel converter includes: a converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal; a plurality of D flip flops configured to transmit the serial data received through the converter to a D flip flop of a next stage by the clock signal received through the converter and output the serial data of the D flip flop of the next stage by the load signal received through the converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals. | 05-28-2015 |
| 20150303909 | CIRCUIT FOR GENERATING ACCURATE CLOCK PHASE SIGNALS FOR HIGH-SPEED SERDES - Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer. | 10-22-2015 |
| 20160072522 | DATA PROCESSING APPARATUS AND METHOD OF PROCESSING DATA - A data processing apparatus includes an inputting portion; a first retrieving portion; a second retrieving portion; a clock determining portion; a first serial parallel converting portion; a second serial parallel converting portion; and a combining portion. The inputting portion receives a serial data including a clock bit. The first retrieving portion obtains a first retrieved data. The second retrieving portion obtains a second retrieved data. The clock determining portion determines whether the clock bit is included in the first retrieved data or the second retrieved data. The first serial parallel converting portion performs parallel conversion to obtain a first parallel data. The second serial parallel converting portion performs parallel conversion to obtain a second parallel data. The combining portion combines the first parallel data and the second parallel data to output a parallel data. | 03-10-2016 |
| 20160126977 | COMMUNICATION APPARATUS, IMAGE FORMING APPARATUS, COMMUNICATION METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - A communication apparatus includes a serializer configured to convert parallel data into serial data and output the serial data; and a deserializer configured to convert the serial data output from the serializer into parallel data and output the parallel data. The serializer is configured to add first data used for detecting unique data in the parallel data before the unique data, add second data used for detecting the unique data after the unique data, and add third data whose length is variable to each of the first data and the second data. | 05-05-2016 |
| 20180026657 | HIGH-SPEED SERIAL DATA RECEIVING APPARATUS | 01-25-2018 |
