| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341096000 | To or from constant distance codes | 8 |
| 20160149587 | EFFICIENT DECODER FOR CURRENT-STEERING DIGITAL-TO-ANALOG CONVERTER - A decoder for a current-steering digital-to-analog converter (DAC) is described herein. In an embodiment, the decoder is a dynamic element matching (DEM) row/column decoder that randomizes pairs of row control signals and column control signals that are provided to a matrix of current cells. The randomization is performed in a manner that ensures that the pairs of row control signals are randomized as pairs. In another embodiment, the decoder is an N-dimensional decoder, where N is any integer greater than two. The N-dimensional decoder comprises an N number of decoders that are each configured to provide respective control signals that are provided to current source(s) in current cell(s) in a respective dimension of an N-dimensional matrix of current cells for enabling current source(s) included therein. Such decoders advantageously allow for a simpler, more efficient design compared to a non-segmented, unary DAC due to the smaller area and lower power consumed. | 05-26-2016 |
| 20160182083 | Systems and Methods for Decoder Scheduling With Overlap and/or Switch Limiting | 06-23-2016 |
| 341097000 | Gray to binary | 2 |
| 20120075126 | EMI REDUCTION WITH SPECIFIC CODING OF COUNTER SIGNALS - Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt. | 03-29-2012 |
| 20140028481 | EMI Reduction with Specific Coding of Counter Signals - Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt. | 01-30-2014 |
| 341098000 | Binary to Gray | 4 |
| 20090295608 | GENERATING A GRAY CODE FOR AN ODD LENGTH SEQUENCE USING A VIRTUAL SPACE - Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence. | 12-03-2009 |
| 20100134332 | ENCODING A GRAY CODE SEQUENCE FOR AN ODD LENGTH SEQUENCE - A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length “L”. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code. | 06-03-2010 |
| 20110156935 | APPARATUS AND METHOD FOR SIMPLIFYING DIGITAL-TO-ANALOG CONVERTER CIRCUITRY USING GRAY CODE - For high resolution resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row of the resistor string are fed into a multiplexer, wherein the multiplexer produces an output voltage. A method and apparatus are disclosed for implementing the reflective nature of Gray code to design a DAC such that all the switches in a column of the resistor string may be controlled with only one control signal, thereby reducing extra routing costs, surface area, and dynamic power consumed by the circuit. | 06-30-2011 |
| 20130278451 | Binary-to-Gray Converting Circuits and Gray Code Counter Including the Same - A binary-to-Gray converting circuit includes a buffer unit and a conversion unit. The buffer unit generates a data code of n bits in response to a power supply voltage and a second binary bit signal through an n | 10-24-2013 |
