| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341095000 | Byte length changed | 10 |
| 20080252497 | TECHNIQUES FOR 9B10B AND 7B8B CODING AND DECODING - A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided. | 10-16-2008 |
| 20080258945 | TECHNIQUES FOR 9B10B AND 7B8B CODING AND DECODING - A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided. | 10-23-2008 |
| 20090021404 | VARIABLE RESISTANCE LOGIC - A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new code having greater than n digits, and a variable resistance logic coupled to the translation logic and comprising greater than n semiconductor devices. A resistance associated with the variable resistance logic depends on activation statuses of the semiconductor devices. The translation logic adjusts at least some of the semiconductor devices in accordance with the new code. | 01-22-2009 |
| 20090027242 | HIGH-RATE RLL ENCODING - An unencoded m-bit data input sequence is divided into a block of n bits and a block of m-n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D | 01-29-2009 |
| 20090189794 | Scrambled block encoder - A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission. | 07-30-2009 |
| 20090267813 | Semiconductor devices, a system including semiconductor devices and methods thereof - Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced. | 10-29-2009 |
| 20110128170 | Semiconductor devices, a system including semiconductor devices and methods thereof - Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced. | 06-02-2011 |
| 20130069806 | METHOD AND APPARATUS FOR ENCODING AND DECODING STRUCTURED DATA - The present invention relates to a method and apparatus for encoding and decoding data, and more particularly, to a method and apparatus for encoding and decoding structured data. A method of encoding structured data according to the present invention includes fragmenting the structured data into fragments according to a configuration of the structured data; and encoding the fragments to generate encoded fragments using a string table including strings contained in the structured data. | 03-21-2013 |
| 20150295591 | INCREASING SPEED OF DATA COMPRESSION - A computer implemented method of performing data compression includes applying, with a computing device, a hash function to a selected part of a character string to calculate a hash value; searching, using the hash value, through entries in a bucket chain having the hash value previously registered in a hash table, and finding a longest matching character string; acquiring, an index indicating that a longest matching character string cannot be found in the search through the entries and thus the search operation is wasted; and switching the hash function to a different hash function for expanding the selected part of the character string, without reconstructing the hash table, when the index exceeds a predetermined threshold. | 10-15-2015 |
| 20160020782 | IMPROVEMENTS FOR BASE64 ENCODING AND DECODING - Base64 encoding and decoding advances are characterized. Some of the described embodiments rely on only a single bit shifting operation; some have no reliance on bit-shifting. Some access data source bytes with multi-byte reads, and use those data source bytes as indexes into an encoding lookup table. Some use a table with four quadrants, each of which contains a copy of the same 64 encoding values. Some use a negative value as both a counter and an index. Some exclude BSWAP instructions even with a little-endian processor. Some partition a data source into N partitions, which are then encoded or decoded concurrently. In some, partition length is based on expected processor performance. Unrolled loops, exemplary assembly language code and coding choices, division using MagicNumber multiplication, terminal null addition, encoding/decoding applications, and other aspects of some embodiments are also presented. | 01-21-2016 |
