| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341094000 | With error detection or correction | 31 |
| 20080258944 | DIGITAL DATA MODULATOR-DEMODULATOR - A digital data demodulator which can reduce a loss of decodable digital data, and increase capability of reproducing digital data inputted through a transmission line even when an error occurs in the transmission line. In the digital data demodulator, a specific pattern detector ( | 10-23-2008 |
| 20080266149 | Modulation Code System and Methods of Encoding and Decoding a Signal - The invention relates to a modulation code system and a corresponding modulation method. Said modulation system comprises an encoder | 10-30-2008 |
| 20080291064 | Estimation of Timing Errors in a Time-Interleaved Analog to Digital Converter System - A method for estimating a relative time difference vector in a group of digitized signals from a time interleaved analog-to-digital module having a plurality of parallel and time interleaved analog-to-digital converters. The method comprises the steps of selecting (S | 11-27-2008 |
| 20080309525 | MULTI-STAGE CODE GENERATOR AND DECODER FOR COMMUNICATION SYSTEMS - A method of encoding data for transmission from a source to a destination over a communications channel is provided. A plurality of redundant symbols are generated from an ordered set of input symbols to be transmitted. A plurality of output symbols are generated from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of symbols in the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols, and such that the ordered set of input symbols can be regenerated to a desired degree of accuracy from any predetermined number, N, of the output symbols. | 12-18-2008 |
| 20090027241 | Fast error-correcting of embedded interaction codes - A fast decoding technique for decoding a position of a bit in a pattern provided on a media surface that can generate large amounts of solution candidates quickly by switching or flipping bits and utilizing a recursion scheme. The fast decoding technique may be employed to simultaneously decode multiple dimensions of a pattern on the media surface. | 01-29-2009 |
| 20090040081 | ENCODING AND DECODING METHODS USING GENERALIZED CONCATENATED CODES (GCC) - Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level. | 02-12-2009 |
| 20090073009 | SEMICONDUCTOR MEMORY DEVICE HAVING ERROR CORRECTION FUNCTION - A semiconductor memory device configured such that the time required for its access test can be reduced comprising a memory cell array, a row decoder, a column decoder, an error correction circuit, and an output circuit. The error correction circuit performs error correction on a code word read through the bit lines selected by the column decoder from ones of memory cells located at places at which the word line selected by the row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating the error position and corrects the information bit in the detected error position to generate error corrected data. The output circuit relays to the outside the error corrected data when a normal operation mode has been designated and the error detection data when a test operation mode has been designated. | 03-19-2009 |
| 20090153379 | System and Method for Encoding a Signal Using Compressed Sensor Measurements - Described is a system and method for receiving a signal for transmission and encoding the signal into a plurality of linear projections representing the signal. The encoding includes defining a transform matrix. The transform matrix being defined by processing the signal using a macroseparation matrix, processing the signal using a microseparation matrix and processing the signal using an estimation vector. | 06-18-2009 |
| 20090174584 | TRANSMISSION DEVICE AND TRANSMISSION METHOD, INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD, AND PROGRAM - A transmission device configured to transmit a transmission bit string which is an arrangement of a unit bit string of multiple N bits includes: a conversion unit configured to convert the unit bit string into a converted bit string in accordance with a conversion table obtained by obtaining an error rate wherein a k'th bit out of the N bits is in error; obtaining an error expectancy which is an expectancy that a significant bit of the N bits in the unit bit string will err; and creating a conversion table that correlates the unit bit string and a converted bit string obtained by converting the insignificant bit of the unit bit string to a smallest error expectancy bit pattern which is a bit pattern that minimizes the error expectancy of the multiple bit patterns; and a transmission unit configured to transmit the converted bit string. | 07-09-2009 |
| 20100013683 | METHOD FOR ERROR HANDLING - In a method for error handling in transmission of a datum over a communications system, at least two data words consisting of bits are generated for the datum in accordance with a predefined coding rule, and one of the generated data words is selected taking into consideration a running digital sum formed over the corresponding data word, and the running digital sum of the selected data word is used for the formation of a first running digital sum. The selected data word is converted into a code data word, and a bit of the data word is in each case assigned a two-bit string with two different single-bit values. The code data word and the first running digital sum are transmitted. The received code data word is examined to ascertain whether an erroneous two-bit string exists, in which case the error is corrected using the first running digital sum. | 01-21-2010 |
| 20100033356 | CIRCUITS AND METHODS TO MINIMIZE NONLINEARITY ERRORS IN INTERPOLATING CIRCUITS - Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second voltage-current converter circuits, each including a first transistor and a second transistor, each having a first electrode configured to receive a signal generated by a corresponding current source, a first current source providing a signal to the first voltage-converter circuit and comprising a first error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a first current through the first current source to operate the first voltage-converter circuit in a nominal linear operating mode, and a second current source providing a signal to the second voltage-converter circuit and comprising a second error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a second current through the second current source to operate the second voltage-converter circuit in the nominal linear operating mode. | 02-11-2010 |
| 20100103001 | METHODS AND APPARATUS EMPLOYING FEC CODES WITH PERMANENT INACTIVATION OF SYMBOLS FOR ENCODING AND DECODING PROCESSES - A method of encoding data for transmission from a source to a destination over a communications channel is provided. A plurality of encoded symbols are generated from a set of input symbols including source symbols and redundant symbols, wherein the input symbols are organized such that at least one of the input symbols is not used for a first encoding process, so that it is permanently inactivated for the purposes of scheduling a decoding process. A method of decoding data is also provided, wherein encoded symbols generated from a set of input symbols are used to recover source symbols, wherein the input symbols are organized such that at least one of the input symbols is not used for a first decoding process, so that it is permanently inactivated for the purpose of scheduling the decoding process. | 04-29-2010 |
| 20100277353 | METHOD AND SYSTEM FOR COMPRESSION OF LOGICAL DATA OBJECTS FOR STORAGE - There is provided a compression system configured to compress logical data objects into one or more accommodation blocks with a predefined size, and a method of operating thereof. The compression system comprises a compression engine capable of compressing input data with the help of sequential encoding one or more input strings and a counter operatively coupled to the compression engine. The counter is configured to keep its ongoing value indicative of a number of input bytes in one or more strings successfully encoded into a given accommodation block; and, responsive to unsuccessful compression of a string into the given accommodation block, to provide the compression engine with information indicative of starting point in the input stream for encoding into the next accommodation block, thus giving rise to a “start indication”. | 11-04-2010 |
| 20110043390 | ENCODING AND DECODING METHODS USING GENERALIZED CONCATENATED CODES (GCC) - Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level. | 02-24-2011 |
| 20110050468 | THERMOMETER CODE TRANSCODING AND ENCODING METHODS AND SYSTEMS - Examples of systems and methods are provided for generating an output signal having an output code having less number of bits compared to an input signal having a thermometer code representation. The system may partition the input code bits into non-overlapping clusters. The system may generate a control signal for each of the clusters based on, at least in part, a logical OR operation over all bits in a corresponding one of the clusters. The system may determine a transition cluster comprising a 1/0 transition in the input code bits. The system may determine output code bits based on, at least in part, an input code bit pattern in the transition cluster and an identity of the transition cluster. | 03-03-2011 |
| 20110175758 | SYSTEM AND METHOD FOR REMOVING GLITCHES FROM A BIT STREAM - A bit stream is received and each bit corresponding to the bit stream is over-sampled to generate a first set of data samples. Each data sample from the first set of data samples is compared with a corresponding immediate previous data sample to generate a second set of data samples. The second set of data samples is compared with bit masks, and accordingly, some of the data samples in the first set of data samples are identified for replacement. Further, a substitute data sample is selected from the first set of data samples based on a predefined criterion and some of the data samples in the first set of data samples are replaced with the substitute data sample. | 07-21-2011 |
| 20110254714 | METHOD AND APPARATUS FOR SOFT SYMBOL DETERMINATION - A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed. | 10-20-2011 |
| 20110309958 | METHOD AND APPARATUS FOR ENCODING AND DECODING DATA - Methods and apparatuses for encoding and decoding data. The method for encoding data includes: receiving data; determining one quantizer from among a plurality of quantizers having a same quantization step size and different offset values; and transmitting an indicator and a quantized coefficient related to the determined quantizer. The method for decoding data includes: receiving an indicator and a quantized coefficient related to a quantizer; determining one de-quantizer from among a plurality of de-quantizers by using the indicator; and acquiring reconstructed data by de-quantizing the quantized coefficient by using the determined de-quantizer. | 12-22-2011 |
| 20120001778 | SYSTEM AND METHOD FOR MULTI-DIMENSIONAL ENCODING AND DECODING - A system and method for decoding multi-dimensional encoded data. A set of multi-dimensional encoded data may be received encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions. The multi-dimensional data may potentially have errors. A map may be used to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes. The unsolved component codes may be decoded using one or a plurality of tested error correction hypotheses that yields a decoding success, where each hypothesis correcting a different set of intersection bits for a different input bit. The successful hypothesis may be applied for correcting the multi-dimensional encoded data. | 01-05-2012 |
| 20120026022 | ENCODING AND DECODING SYSTEMS AND RELATED METHODS - A method of searching for candidate codewords for a telecommunications system, the method comprising receiving a sequence of constellation points, producing a received FEC vector comprised of bits from the received constellation points, comparing the received FEC vector with a plurality of candidate codewords within a Dorsch decoding process using an ordered pattern, and terminating the search when a candidate codeword from among the plurality of candidate codewords is found residing within a predetermined range of a specified distance of the received FEC vector. | 02-02-2012 |
| 20120044098 | Swap Tolerant Coding and Decoding Circuits and Methods - This invention relates to a coding circuit for generating a swap tolerant code. The coding circuit comprises a first and second input ( | 02-23-2012 |
| 20120056764 | System and Method for Preserving Neighborhoods in Codes - A system and method for preserving neighborhoods in codes are provided. A method for transmitting information includes receiving an information string to transmit, generating a first address and a second address from the information string, encoding the first address and the second address with a layered code encoder, thereby producing a codeword and transmitting the codeword. The generating is based on a linear block code. | 03-08-2012 |
| 20120119928 | SYSTEMS AND METHODS FOR PERFORMING EFFICIENT DECODING USING A HYBRID DECODER - Systems and methods for decoding data using a hybrid decoder are provided. A data signal that includes a codeword is received. A signal quality indicator for the data signal is computed. One of a plurality of decoders is selected based on the computed signal quality indicator. Each of the plurality of decoders is configured to decode information based on a different decoding technique. The codeword included in the data signal is decoded using the selected one of the plurality of decoders. | 05-17-2012 |
| 20120249346 | METHOD AND APPARATUS FOR SOFT SYMBOL DETERMINATION - A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed. | 10-04-2012 |
| 20120274487 | APPARATUS FOR ENCODING AND DECODING, DATA STORAGE APPARATUS AND METHOD FOR ENCODING AND DECODING - According to one embodiment, an apparatus for encoding and decoding includes an encoder configured to generate integrated parity data for data obtained by combining first data with second data. The encoder includes a first generator, a second generator, and a third generator. The first generator generates parity data for the first data using a first check matrix with a predetermined regularity. The second generator generates parity data for the second data using a second check matrix with a regularity that is exclusive and different from the first check matrix. The third generator generates the integrated parity data by integrating the parity data generated by the first generator with the parity data generated by the second generator. | 11-01-2012 |
| 20130120169 | Systems and Methods for Reduced Power Multi-Layer Data Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a data encoder circuit. The data encoder circuit is operable to apply an encoding algorithm to an input data set in accordance with a multi-layer code structure including a first row and a last row to yield an encoded data set. The last row of the multi-layer code structure represented in the encoded data set conforms to an identity matrix. | 05-16-2013 |
| 20130147645 | ENCODING METHODS AND SYSTEMS FOR BINARY PRODUCT CODES - A data encoding circuit and a corresponding method is provided. The data encoding circuit includes a first data formatter in communication with an encoder section. The first data formatter is configured to receive blocks of source data in serial and output parallel two dimensional source data. The encoder receives the parallel two dimensional source data and that computes a plurality of serial row parity bits and a plurality of parallel column parity bits of an error correcting code from the parallel two dimensional source data. A second data formatter communicates with the encoder section and receives the parallel column parity bits and outputs serial column parity bits. A multiplexer section multiplexes the blocks of source data, the serial row parity bits, and the serial column parity bits into an output stream including the blocks of source data encoded by the error correcting code. | 06-13-2013 |
| 20130321183 | CODER WITH SNOOP MODE - Techniques are disclosed relating to coding data in an apparatus. In one embodiment, the apparatus includes a coder circuit coupled to a data bus, where the coder circuit is configured to receive an indication that data is being transmitted over the data bus from a first circuit to a second circuit. The coder circuit is configured to perform a coding operation on the data in response to receiving the indication. In some embodiments, the coder circuit is configured to operate in a mode in which the coder circuit captures data of a data transmission via the data bus without being specified as a participant of the data transmission. When the coder circuit is not operating in the mode, the coder circuit is not configured to capture data of a data transmission without being specified as a participant of the data transmission. | 12-05-2013 |
| 20140152476 | DATA ENCODING METHODS, DATA DECODING METHODS, DATA RECONSTRUCTION METHODS, DATA ENCODING DEVICES, DATA DECODING DEVICES, AND DATA RECONSTRUCTION DEVICES - In an embodiment, a data encoding method may be provided. The data encoding method may include: inputting data to be encoded; determining a polynomial so that an evaluation of the polynomial at a sum of a first supporting point of the polynomial and a second supporting point of the polynomial corresponds to the sum of an evaluation of the polynomial at the first supporting point and an evaluation of the polynomial at the second supporting point, wherein coefficients of the polynomial are determined based on the data to be encoded; and generating a plurality of encoded data items by evaluating the polynomial at a plurality of supporting points. | 06-05-2014 |
| 20140375485 | TURBO ENCODER APPARATUS - Disclosed is a turbo encoder apparatus using an improved signal processing method in order to enhance a speed of a turbo encoder used in a channel coding technology. There are effects of reducing a time spent for performing an encoding by performing the encoding in the unit of plural bits every clock cycle and performing a turbo encoding with a structure optimized for a total signal processing processor through the assembly of input forms of encoding output bitstreams in a subsequent signal processing step for encoding through the bitstream assembling apparatus. | 12-25-2014 |
| 20150318866 | MEASUREMENT METHOD, MEASUREMENT APPARATUS AND MEASUREMENT PROGRAM - [Problem] To shorten the measurement time, while maintaining the measurement precision, for a data converter of delta-sigma system. | 11-05-2015 |
