Class / Patent application number | Description | Number of patent applications / Date published |
341081000 | To or from interleaved format | 10 |
20090015448 | DECODER - A decoder comprising a decoding element arranged to operate in a first mode for decoding a turbo encoded data stream and in a second mode for decoding a viterbi encoded data stream, wherein the decoding element is responsive to a first control signal for switching from the first mode to the second mode during decoding of a turbo code block and responsive to a second control signal for switching from the second mode to the first mode to allow continued decoding of the turbo code block. | 01-15-2009 |
20090160686 | APPARATUS OF MULTI-STAGE NETWORK FOR ITERATIVE DECODING AND METHOD THEREOF - An apparatus and method of multi-stage network for iterative network are disclosed. The apparatus has M stages, and each stage uses N multiplexers to transmit N codeword partitions simultaneously. Every starting terminal, either the output port of memories, soft-in soft-out decoders, or multiplexers, has two paths to couple with two different multiplexers at next stage. One path connects the source to the first data port of one multiplexer; the other connects the source to the second data port of another multiplexer. The two multiplexers will be controlled with the same 1-bit signal, so each source has only one valid path to next stage. The invention can guarantee that the transmission of N data blocks is free from contention. | 06-25-2009 |
20090237279 | SYSTEM AND METHOD FOR SIGNALING ON A BUS USING FORBIDDEN PATTERN FREE CODES - Embodiments of our invention describe the method for producing forbidden pattern free (FPF) codewords using an encoder-decoder (CODEC). First, the method encodes a dataword to produce a FPF codeword by mapping dataword to a Fibonacci Numeral System space. Further, the FPF codeword is transmitted via adjacent lines of a bus and decoded when received from the bus to recover the dataword to eliminate all crosstalk on the bus. | 09-24-2009 |
20090273492 | Systems and Methods for Queue Based Data Detection and Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time. | 11-05-2009 |
20090309770 | METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF CODE TYPES - Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers. | 12-17-2009 |
20090315742 | INTERLEAVER FOR SCRAMBLING AND INFORMATION WORD - Interleaver for scrambling an information word, the information word having a multitude of digits, for obtaining a permuted information word. The interleaver includes a first interleaver stage for a row-by-row arranging of the digits of the information word in a plurality of first rows and first columns, and a second interleaver stage for scrambling the digits of one of the first rows by interchanging at least two digits of the one first row in order to obtain a first scrambled row, and for replacing the one of the first rows by the first scrambled row. The first interleaver stage is configured for reading the first row, which is replaced based on the first scrambled row, in a column-by-column manner in order to obtain the permuted information word. | 12-24-2009 |
20100033355 | PRUNING METHODS FOR THE GENERATION OF S-RANDOM INTERLEAVERS, AND INTERLEAVER PERFORMING THE METHODS - The method allows to obtain, starting from an initial S-random interleaver permutation stored in memory devices and having a size N, i.e. formed of N elements, a final S-random permutation having a smaller size K02-11-2010 | |
20100207789 | EXTENDED TURBO INTERLEAVERS FOR PARALLEL TURBO DECODING - A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed. | 08-19-2010 |
20110267209 | TRELLIS ENCODER AND TRELLIS ENCODING DEVICE HAVING THE SAME - A trellis encoding device includes a plurality of trellis encoders to perform trellis-encoding of a transport stream into which a supplementary reference signal (SRS) has been inserted, and performs a memory reset in a region that precedes an SRS; and a parity compensation unit to compensate for parities of the transport stream in accordance with values stored in memories included in the trellis encoders. The plurality of trellis encoders may be implemented in diverse types. The trellis encoding device can perform a memory reset selectively using the stored value of the memory and the inverted value thereof, or selectively using the stored value of the memory and a fixed value. By properly resetting the memory in processing the transport stream into which the SRS has been inserted, DC offset can be reduced. | 11-03-2011 |
20120242518 | SUBSET TRANSFORM INTERLEAVER - Digital communications interleavers re-order the bits of a data coding block in a way that can be described by a table of indices that map the original order to the interleaved order. Conventional interleavers include index table interleavers, which store an index table ahead of operation and algorithmic Interleavers, which generate the indices during operation. | 09-27-2012 |