| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341068000 | To or from NRZ (nonreturn-to-zero) codes | 12 |
| 20110181450 | METHOD AND APPARATUS FOR LINE CODING - The present invention provides a convolutional line coding method, including: constructing a sequence set, where the length of each sequence in the sequence set is n bits; selecting a balanced sequence in the sequence set, and obtaining source data of n−1 bits corresponding to the balanced sequence; performing Hamming distance detection for an unbalanced sequence in the sequence set to obtain source data of n−1 bits corresponding to the unbalanced sequence; sorting the balanced sequence and the unbalanced sequence according to an operation difference value, and generating a code table, where the source data of n−1 bits correspond to the sequence of n bits, and the code table is designed for line coding; and at time of encoding the source data of n−1 bits, obtaining a coding result of n bits according to a mapping relation in the code table. | 07-28-2011 |
| 20130154859 | METHODS AND SYSTEMS FOR DECODING DATA - A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is encoded using a Non Return to Zero Inverted (NRZI) code and a 17 Parity Preserve/Prohibit (17PP) code, determining a 17PP modulated bit stream based upon the coded bit stream using a first selected decoding method, and generating a plurality of decisions by processing the 17PP modulated bit stream using a second selected decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in a source information. | 06-20-2013 |
| 341069000 | Return-to-zero to or from NRZ (nonreturn-to-zero) codes | 1 |
| 20110074610 | High Speed, Low Power Non-Return-To-Zero/Return-To-Zero Output Driver - A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic. | 03-31-2011 |
| 341070000 | To or from bi-phase level code (e.g., split phase code, Manchester code) | 9 |
| 20090322572 | CIRCUIT AND METHOD FOR MANCHESTER DECODING WITH AUTOMATIC LEADING PHASE DISCOVERY AND DATA STREAM CORRECTION - A method and circuit are shown for decoding a Manchester encoded data input signal, wherein preamble found, data input, and recovered clock signals are received and a phase of the data input signal stored responsive thereto. A decision time signal alternates state responsive to the recovered clock signal. A switch pulse signal asserts when the decision time signal is active and the stored phase and current phase of the data signal have the same logic value, which is stored and cleared responsive to the recovered clock signal. A data output is decoded from a decision pair of phases responsive to the recovered clock, preamble found and decision time signals. The stored and current phases of the data input signal are selected to be the decision pair when neither the switch pulse signal or stored switch pulse signal are asserted and, otherwise, the stored phase and inverted stored phase are selected. | 12-31-2009 |
| 20100045492 | Decoding Apparatus and Method - A decoding apparatus is disclosed. The decoding apparatus is applied to a data signal comprising a plurality of bits. A plurality of sampled data is generated by sampling the data signal. Each of the bits has a same cycle. The decoding apparatus comprises a calculating module and a determining module. When the calculating module sets a first interval and a second interval in the cycle of a specific bit, the calculating module generates a first count according to the sampled data in the first interval corresponding to a first logic level and generates a second count according to the sampled data in the second interval corresponding to a second logic level. The determining module determines a digital logic value of the specific bit. | 02-25-2010 |
| 20110102209 | SIGNAL ENCODING APPARATUS AND METHOD OF RADIO FREQUENCY IDENTIFICATION READER - A signal encoding apparatus and method of a radio frequency identification (RFID) reader capable of removing a high frequency component without using a digital filter, and performing Manchester encoding by using two symbols. The signal encoding apparatus of the RFID reader including an encoding unit that stores a first symbol and a second symbol; transmits the first symbol if data received after an initial state is zero (0), and returns to the initial state; delays for a given time period if the data received after the initial state is one (1); transmits the second symbol if data received after the delayed given time period is zero (0), and returns to the initial state; and transmits the first symbol if the data received after the delayed given time period is one (1), and stands by. | 05-05-2011 |
| 20120007754 | METHOD AND APPARATUS FOR DECODING TRANSMITTED/RECEIVED DATA - The present invention discloses a transmitted/received data decoding method and apparatus, which achieve effects of decoding performance improvement and synchronous detection. The decoding method includes setting a coded edge pattern, and filtering a received data by using the set coded edge pattern as a window; respectively computing absolute values of filtered values filtered by using the coded edge pattern windows; detecting a maximum absolute value from the computed absolute values; determining a sign (+/−) for the detected maximum absolute value; outputting an intermediate bit value of the corresponding original data as a resultant decoded value according to the determined sign and a window type (i.e. coded edge patter) with the selected maximum absolute value. | 01-12-2012 |
| 20130027228 | DECODER CIRCUIT FOR DOWN-SAMPLING A DIFFERENTIAL MANCHESTER ENCODING - Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence. | 01-31-2013 |
| 20130076543 | Decoding Method for Biphase-Encoded Data - A decoding method for biphase-encoded data is provided. The decoding method includes detecting falling-edge transitions in the biphase-encoded data to decode according to a time difference (Δt) between each two adjacent falling-edge transitions and the logic value of previous bit. When Δt is 1 bit period and previous bit is logic 1, it's determined that present bit is logic 1. When Δt is 1 bit period and previous bit is logic 0, it's determined that present bit is logic 0. When Δt is 1.5 bit periods and previous bit is logic 1, it's determined that present and next bits are both logic 0. When Δt is 1.5 bit periods and previous bit is logic 0, it's determined that present bit is logic 1. When Δt is 2 bit periods and previous bit is logic 1, it's determined that present and next bits are logic 0 and 1 respectively. | 03-28-2013 |
| 20150009050 | DIFFERENTIAL DECODER - In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal. | 01-08-2015 |
| 20150123824 | Decoding a Manchester Code Without a PLL for Short Data Sequences - In a decoding device for a Manchester-encoded signal, at least one moving data average and/or one moving clock average is/are formed relative to mutually differing average times using moving-type averaging units, and from these moving average values, binary output signals are made available as data signal and/or clock signal with the aid of comparators. | 05-07-2015 |
| 20160065238 | Decoding a Manchester Code Without a PLL for Short Data Sequences - In a decoding device for a Manchester-encoded signal, at least one moving data average and/or one moving clock average is/are formed relative to mutually differing average times using moving-type averaging units, and from these moving average values, binary output signals are made available as data signal and/or clock signal with the aid of comparators. | 03-03-2016 |
