| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341058000 | To or from minimum d.c. level codes | 13 |
| 20090045989 | CODING APPARATUS, DECODING APPARATUS, AMPLITUDE ADJUSTMENT APPARATUS, RECORDED INFORMATION READER, SIGNAL PROCESSING APPARATUS AND STORAGE SYSTEM - A general purpose of the present invention is to improve a DC-free property with a further reduced circuit scale while satisfying a run-length limit. An RLL/DC-free coding unit coding includes a first RLL coding unit, a first signal processing unit, a second RLL coding unit, and a DC component removal coding unit. The first RLL coding unit generates a first coded sequence by subjecting a digital signal sequence outputted from a scrambler to run-length limited coding. The first signal processing unit performs a predetermined signal processing on the digital signal sequence without changing the number of a plurality of bits contained in the digital signal sequence outputted from the scrambler | 02-19-2009 |
| 20090146850 | TRANSMITTING/RECEIVING METHODS AND SYSTEMS FOR DC BALANCE ENCODED DATA INCLUDING SIMULTANEOUS SWITCHING NOISE REDUCING PREAMBLES - DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data. | 06-11-2009 |
| 20100026533 | Data Bus Inversion Apparatus, Systems, and Methods - Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. | 02-04-2010 |
| 20100060493 | MULTI-CHANNEL SAMPLING SYSTEM AND METHOD - An apparatus and method for sampling a plurality of digital video signals to generate an interleaved digital video signal is disclosed. The apparatus includes: a first analog-to-digital converter (ADC), coupled to an analog input signal, for converting the analog input signal to a first digital output signal according to a sampling clock signal; a second ADC, coupled to the analog input signal, for converting the analog input signal to a second digital output signal according to the sampling clock signal; a reference clock generator, for generating a reference clock; a random signal generator, for outputting control values in a random sequence; and a clock controller, coupled to the reference clock generator and the random signal generator, for modifying the reference clock signal according to the control values to generate the sampling clock signal to the first ADC and the second ADC. | 03-11-2010 |
| 20100231425 | SYSTEMS AND METHODS FOR CONSTRUCTING HIGH-RATE CONSTRAINED CODES - A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes. | 09-16-2010 |
| 20100259426 | TRANSMITTING/RECEIVING METHODS AND SYSTEMS WITH SIMULTANEOUS SWITCHING NOISE REDUCING PREAMBLES - DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data. | 10-14-2010 |
| 20110043388 | ENCODING AND DECODING TO REDUCE SWITCHING OF FLASH MEMORY TRANSISTORS - Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating transformed data that has a predictable ratio of 1's to 0's. The transformed data is stored to flash memory. The transformed data is illustratively generate by either applying an “exclusive or” function to the user data or by converting the user data into a number having a greater number of bits. | 02-24-2011 |
| 20110156934 | METHOD AND APPARATUS FOR PARALLEL DATA INTERFACING USING COMBINED CODING AND RECORDING MEDIUM THEREFOR - A semiconductor device may include a coding lookup table unit including a plurality of coding lookup tables each of which is selected by a respectively selection signal, and a selection unit configured to receive one of N-bit parallel data and extract respective encoded data corresponding to the selection signal and to which the N-bit parallel data is mapped from the coding lookup table unit, and encoded data and extract respective N-bit parallel data corresponding to the selection signal and to which the encoded data is mapped from the coding lookup table unit, wherein N is 2 or an integer greater than 2, and wherein the coding lookup tables respectively store a plurality of coded data patterns that respectively correspond to patterns of the N-bit parallel data and are random temporally and spatially. | 06-30-2011 |
| 20120056762 | Data Bus Inversion Apparatus, Systems, and Methods - Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. | 03-08-2012 |
| 20140035765 | METHOD AND APPARATUS FOR PARALLEL DATA INTERFACING USING COMBINED CODING AND RECORDING MEDIUM THEREFOR - A semiconductor device may include a coding lookup table unit including a plurality of coding lookup tables each of which is selected by a respectively selection signal, and a selection unit configured to receive one of N-bit parallel data and extract respective encoded data corresponding to the selection signal and to which the N-bit parallel data is mapped from the coding lookup table unit, and encoded data and extract respective N-bit parallel data corresponding to the selection signal and to which the encoded data is mapped from the coding lookup table unit, wherein N is 2 or an integer greater than 2, and wherein the coding lookup tables respectively store a plurality of coded data patterns that respectively correspond to patterns of the N-bit parallel data and are random temporally and spatially. | 02-06-2014 |
| 20140077976 | MINIMUM ENERGY CODING METHOD AND APPARATUS FOR PERFORMING DIRECT CURRENT (DC) BALANCING IN BODY AREA NETWORK OR LOW POWER NETWORK - A minimum energy coding method and apparatus that includes obtaining groups of bits from a bitstream and finding a mapping rule between the groups of bits and codewords that is chosen to maintain a DC balance. For example, the bitstream may be a bitstream corresponding to a biosignal. | 03-20-2014 |
| 20140313062 | DATA BUS INVERSION APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. | 10-23-2014 |
| 20160019179 | SYSTEMS AND METHODS FOR TRANSITION-MINIMIZED DATA BUS INVERSION - Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus. | 01-21-2016 |
