| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 341055000 | Substituting specified bit combinations for other prescribed bit combinations | 28 |
| 20080198045 | Transmission of a Digital Message Interspersed Throughout a Compressed Information Signal - A method is disclosed that enables the transmission of a digital message along with a corresponding media information signal, such as audio or video. A telecommunications device that is processing the information signal from its user, such as a speech signal, encodes the information signal by using a model-based compression coder. One such device is a telecommunications endpoint. Then, based on an evaluation of the perceptual significance of each encoded bit, or on some other meaningful characteristic of the signal, the endpoint's processor: (i) determines which encoded bits can be overwritten; and (ii) intersperses the digital message bits throughout the encoded signal in place of the overwritten bits. The endpoint then transmits those digital message bits as part of the encoded information signal. In this way, no additional bits are appended to the packet to be transmitted, thereby addressing the issue of compatibility with existing protocols and firewalls. | 08-21-2008 |
| 20080291063 | Two-bit Tri-Level Forced Transition Encoding - An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are grouped and are converted by an encoding circuit into two new consecutive data bits of the same duration as the original bits. The new encoded bits in each group will necessarily transition between two of three possible data states, and specifically will transition between ‘−1’ and ‘0’ logic states, or ‘+1’ and ‘0’ logic states. Pursuant to this encoding scheme, no more than two consecutive encoded bits will ever be of the same logic state, which prevents any particular data state from predominating and causing DC creep. | 11-27-2008 |
| 20080309523 | APPARATUS AND METHOD OF GENERATING DBI SIGNAL IN SEMICONDUCTOR MEMORY APPARATUS - An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and outputs a detection signal according to a detection result, and a DBI detection unit that outputs a DBI signal according to a difference in charge sharing level using the detection signal. Therefore, it is possible to minimize current consumption. Further, since there is no effect due to resistance skew of a transistor, an error in DBI signal generation and an error in data transfer accordingly can be prevented. Therefore, it is possible to improve the reliability of a system to which a semiconductor memory apparatus is applied. | 12-18-2008 |
| 20080316070 | Encoding of Data Words Using Three or More Level Levels - A data processing circuit comprises an encoder circuit for encoding a data word, wherein each digit may have any one of three or more digit values. The data word is encoded so that digit counts in the data word satisfy predetermined criteria (the digit counts are counts of the numbers of the digits in the encoded data word that assume respective digit values). The encoder defines at least two digit maps, each digit map defining assignments of each of the available digit values to a respective different output digit value. The encoder selects at least two groups of digits within the input data word. Each group is associated with a respective one of the digit maps, the groups being selected so that when each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values occur in the data word will satisfy predetermined criteria. A data signal is generated that represents the input data word by information that identifies the selected groups and an output data word obtained by mapping the digits of each group in the input data word according to the digit map for that group. | 12-25-2008 |
| 20090015444 | DATA COMPRESSION FOR COMMUNICATION BETWEEN TWO OR MORE COMPONENTS IN A SYSTEM - Briefly, within a computer or digital data processing system, embodiments describe a method, article and apparatus for compressing data is described, which may be used for communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system, and/or for communicating between two or more computers or digital data processing systems via an interconnection medium such as a network. | 01-15-2009 |
| 20090015445 | FIFO RADIX CODER FOR ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS - Embodiments described herein may include example embodiments of a method, article and/or apparatus for coding data which may be used for communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system, and/or for communication between computing platforms via a network or other interconnection medium. | 01-15-2009 |
| 20090174582 | Code Conversion Device, Code Conversion Method Used For The Same And Program Thereof - Provided is a code conversion device that is capable of converting codes even if an input code sequence is invalid, and is able to reduce the amount of processing. When a first code sequence is input, the code conversion device generates a decoded signal by decoding the codes of normal frames of the first code sequence at Step S | 07-09-2009 |
| 20090195420 | FIFO RADIX CODER FOR ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS - A method for decoding includes receiving a message at a decoding device, where the message includes a code corresponding to a sequence of data symbols. Based on the code, a first data symbol of the sequence of data symbols is determined. The first data symbol is determined based at least in part on a first radix used to generate the code. Based on the code, a second data symbol of the sequence of data symbols is also determined. The second data symbol is determined based at least in part on a second radix and at least in part on the first data symbol. | 08-06-2009 |
| 20090219179 | Single ended pseudo differential interconnection circuit and single ended pseudo differential signaling method - A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals. | 09-03-2009 |
| 20090256732 | FAST COMPRESSION METHOD FOR SCIENTIFIC DATA - A method and system allows for fast compression and decompressing of data using existing repetitive interleaved patterns within scientific data (floating point, integer, and image). An advantage of the method and system is that it is so fast that it can be used to save time due to a lower amount of data transferred/stored in scenarios like network transfer, disk or memory storage, cache storage or any other real-time applications where time plays a crucial role. | 10-15-2009 |
| 20100013678 | METHOD AND APPARATUS FOR DATA DECOMPRESSION IN THE PRESENCE OF MEMORY HIERARCHIES - A method for decompressing a stream of a compressed data packet includes determining whether first data of a data-dictionary for a first decompression copy operation is located in a history buffer on a remote memory or a local memory, and when it is determined that the first data is located in the remote memory, stalling the first decompression copy operation, performing a second decompression operation using second data that is located in the history buffer on the local memory and fetching the first data from the remote memory to the history buffer on the local memory. The method further includes performing the first decompression operation using the first data in the history buffer on the local memory. | 01-21-2010 |
| 20100141486 | DATA ENCODING AND DECODING METHODS AND COMPUTER READABLE MEDIUM THEREOF - A data encoding method is provided. The data has several bytes, and each byte has n bits. The data encoding method includes the following steps. First, a specific value is defined. Next, the data is divided into one or several data blocks each having m bytes, wherein m≦2 | 06-10-2010 |
| 20100149002 | METHOD FOR CONVERTING VOLTAGE IDENTIFICATION CODE AND COMPUTER SYSTEM - The invention relates to a method for converting a voltage identification code includes the steps as follows. A special binary code range is obtained, and N special voltage identification codes corresponding to a special command are converted to N special binary codes under a converting relation, and the N special binary codes are used as the special binary code range. A first voltage identification code is converted to a corresponding first binary code under the converting relation. In addition, the first binary code and a first preset value are used to compute to obtain a second binary code, and the second binary code is not in the special binary code range. | 06-17-2010 |
| 20100214138 | Balanced Data Bus Inversion - A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used. | 08-26-2010 |
| 20100219991 | New Generation Data Compression Methods - Methods or sub-component method step/s necessary for lossless data compressions of input binary (or adaptable for even N-ary) data file, or for compression/representation of sequential list of positive integers (or offsetted to all be positive integers >0, which may be a sequential list of variable length binary base positive integer digit numbers or even N-ary base positive integer digit numbers) are described, providing many magnitudes orders improvements over existing state-of-art best available methods such as Rice-Coulomb encodings/RunLength based/LZW encodings . . . etc. | 09-02-2010 |
| 20100283639 | TRANSFORM-BASED CODING/DECODING, WITH ADAPTIVE WINDOWS - The present invention provides coding/decoding a digital signal, in particular using a transform with overlap employing weighting windows. In the invention, two consecutive and equal-size blocks of samples of the signal may be weighted by respective different successive windows. These two windows may be chosen independently of each other according to a criterion specific to the characteristics of the signal (entropy, data rate/distortion, etc.) that are determined for each of the two blocks. | 11-11-2010 |
| 20110095920 | ENCODER AND DECODER USING ARITHMETIC STAGE TO COMPRESS CODE SPACE THAT IS NOT FULLY UTILIZED - An encoder/decoder architecture including an arithmetic encoder that encodes the MSB portions of a Factorial Pulse Coder output, and that encodes an output of a first-level source encoder, e.g., MDCT. Sub-parts (e.g., frequency bands) of portions (e.g., frames) of the signal are sorted in increasing order based on a measure related to signal energy (e.g., signal energy itself). In a system that overlays Arithmetic Encoding on Factorial Pulse coding, the result is bits re-allocated to bands with higher signal energy content, yielding higher signal quality and higher bit utilization efficiency. | 04-28-2011 |
| 20110109484 | INFORMATION PROCESSING APPARATUS, AND SIGNAL PROCESSING METHOD - Provided is an information processing apparatus including a distributor that distributes input data in units of M bits and generates N M-bit bit sequences, an encoder that converts each of the N bit sequences distributed by the distributor into a binary symbol sequence of K symbols and generates N binary symbol sequences, a signal generator that generates N transmission signals Sj synchronized with a specific symbol clock and having, as an amplitude value, each symbol value included in the N binary symbol sequences, a signal delay unit that delays, with regard to j, the transmission signals Sj generated by the signal generator by a (j−1)/N-symbol period and generates delay signals Rj, a signal addition unit that adds the delay signals Rj generated by the signal delay unit and generates an added signal, and a signal transmitter that transmits the added signal generated by the signal addition unit. | 05-12-2011 |
| 20110115654 | DATA ENCODING PROCESS, DATA DECODING PROCESS, COMPUTER-READABLE RECORDING MEDIUM STORING DATA ENCODING PROGRAM, AND COMPUTER-READABLE RECORDING MEDIUM STORING DATA DECODING PROGRAM - In a data encoding process: data is encoded by using unit bit series obtained from an encoding bit series; the encoding bit series is searched for a first bit series identical to a portion of the encoded data; the portion is substituted with a second bit series which includes a leading code indicating a leading position of a substitution range and position information indicating the position of the first bit series in the encoding bit series. In a data decoding process: the position information is detected from the substitution range in received data after the leading code is detected in the data; a substitution bit series is extracted from the position in the encoding bit series indicated by the position information; and the data in the substitution range is substituted with the substitution bit series so as to restore the encoded data. | 05-19-2011 |
| 20110128168 | UNICODE-COMPATIBLE ENTROPY CODING - A character data set is compressed with a compression algorithm module of a computer system to generate one or more streams of encoded values. The compression module is configured to compress the character data set with an entropy encoder to generate one or more streams of encoded values with UTF-8 or UTF-16. A code points mapper assigns the encoded values to code points in a Unicode format. A UTF encoder encodes the streams of assigned encoded values. | 06-02-2011 |
| 20110156933 | GENERATING A JITTERED DIGITAL SIGNAL USING A SERIALIZER DEVICE - A serializer device is used for generation, from a parallel digital signal, of a clock signal or a serial binary data signal having a pre-determined amount of jitter. A binary number having consecutive groups of ones and zeroes, when serialized by the serializer device, produces a clock signal. By varying the number of ones and zeroes on the binary number, a pre-determined amount of jitter can be generated. Use of sigma-delta modulation in combination with a phase-locked loop circuitry allows one to obtain a smoothly varying jitter of the output signal. | 06-30-2011 |
| 20120139763 | DECODING ENCODED DATA - A method for decoding encoded data. The method includes receiving data encoded by replacing each of a plurality of characters with bit strings. The method also includes recording, on the basis of definition information, at least one of the characters as corresponding to each of the bit lengths, and generating decode information based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. The method also includes, in response to receiving a particular bit length, generating character information in which the characters are sorted in the bit length order by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths. | 06-07-2012 |
| 20120169519 | METHOD FOR CODING AND AN APPARATUS - A method comprising receiving a syntax element to be encoded as a code word of a set of code words, determining a mapping between the syntax element and the code word on the basis of a hierarchy level in a tree structure, using the mapping to obtain the code word, and updating the mapping is disclosed. | 07-05-2012 |
| 20120229310 | Using Bus Inversion to Reduce Simultaneous Signal Switching - A method includes receiving a first plurality of parallel data; generating a first plurality of encoded data, with each of the first plurality of encoded data same as a respective one of the first plurality of parallel data; and transmitting the first plurality of encoded data simultaneously to a plurality of parallel bus lines, with each of the first plurality of encoded data transmitted by a respective one of the plurality of parallel bus lines. The method further includes receiving a second plurality of parallel data; generating a second plurality of encoded data, with each of the second plurality of encoded data inverted from a respective one of the second plurality of parallel data; and transmitting the second plurality of encoded data simultaneously to the plurality of parallel bus lines, with each of the second plurality of encoded data transmitted by a respective one of the plurality of parallel bus lines. | 09-13-2012 |
| 20130314259 | DATA PROCESSING APPARATUS THAT ENABLES IMPORT/EXPORT OF SETTING VALUE, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM STORING CONTROL PROGRAM THEREFOR - A data processing apparatus that is capable of reducing the garbling of characters caused by the difference among the character codes when setting data are transferred to another apparatus by the import-export function. A storage unit stores setting data for the data processing apparatus. A receiving unit receives an instruction for exporting the setting data stored in the storage unit. A converting unit converts Unicode data included in the setting data into character code data of language, which is set to the data processing apparatus. An export unit exports the character code data converted by the converting unit and the Unicode data. | 11-28-2013 |
| 20140070966 | METHODS AND SYSTEMS FOR COMPRESSING AND DECOMPRESSING DATA - The present invention relates to data compression using compression dictionary. A compression method according to the invention comprises obtaining an initial compression dictionary and a separate secondary dictionary SD; determining at least one subpart of the secondary dictionary that correlates with a block of data DB to compress; updating the initial compression dictionary by inserting the determined at least one subpart therein, to obtain an updated compression dictionary used for compressing the block of data; and compressing the block of data using one or more references to entries of the obtained updated compression dictionary. | 03-13-2014 |
| 20140184430 | HIERARCHICAL ENTROPY ENCODING AND DECODING - A particular implementation receives geometry data of a 3D mesh, and represents the geometry data with an octree. The particular implementation partitions the octree into three parts, wherein the symbols corresponding to the middle part of the octree are hierarchical entropy encoded. To partition the octree into three parts, different thresholds are used. Depending on whether a symbol associated with a node is an S1 symbol, the child node of the node is included in the middle part or the upper part of the octree. In hierarchical entropy encoding, a non-S1 symbol is first encoded as a pre-determined symbol ‘X’ using symbol set S2={S1, ‘X’} and the non-S1 symbol itself is then encoded using symbol set S0 (S2⊂S0), and an S1 symbol is encoded using symbol set S2. Another implementation defines corresponding hierarchical entropy decoding. A further implementation reconstructs the octree and restores the geometry data of a 3D mesh from the octree representation. | 07-03-2014 |
| 20150116136 | Method and Apparatus for Regular Expression Processing with Parallel Bit Streams - One embodiment of the present invention is a method for increasing the speed of a computer in identifying occurrences of strings in a character stream that match a string pattern involving repetitions of characters of a particular character class. The method uses a parallel bit stream processing module of the computer, which processing module includes a processor equipped with parallel processing instructions, to form a plurality of parallel property bit streams Pj. | 04-30-2015 |
