| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 331172000 | WITH SYNCHRONIZING, TRIGGERING OR PULSING CIRCUITS | 7 |
| 20080252391 | Multi-phase interleaved oscillator - An oscillator for synchronizing and controlling a multi-phase, interleaved power supply system that has a plurality of power sources. The oscillator includes a first oscillator, having a pulse generator and a timing capacitor, and a second oscillator, having a pulse generator and timing capacitor, that are electrically coupled to one or more first power supplies and one or more second power supplies, respectively. The pulse generator of the first oscillator is electrically coupled to the second timing capacitor and the pulse generator of the second oscillator is electrically coupled to the first timing capacitor. Each of the pulse generators is structured and arranged to provide a synchronizing pulse to the other oscillator's timing capacitor when the voltage on its own timing capacitor is midway between a pre-determined maximum voltage threshold and a pre-determined minimum voltage threshold. | 10-16-2008 |
| 20080266010 | Semiconductor device and driving method thereof - A low-power-consumption semiconductor device and a driving method thereof where a clock signal generation is controlled. A transmission and reception control circuit to control signal communication with an outside; a ring oscillator control circuit to detect an edge in a receiving signal and control a ring oscillator; a clock generation circuit to generate a clock signal based on the ring oscillator; and a logic circuit to operate based on a clock signal are included. During signal communication between the transmission and reception control circuit and the outside, the ring oscillator operates and a clock signal is output from the clock generation circuit when the ring oscillator control circuit detects an edge in a receiving signal, and the ring oscillator stops and output of the clock signal from the clock generation circuit stops when transmission of a reply signal from the transmission and reception control circuit to the outside is terminated. | 10-30-2008 |
| 331173000 | Triggering or pulsing (e.g., burst generators) | 5 |
| 20080278251 | NOISE REMOVAL CIRCUIT - A noise removal circuit. The noise removal circuit comprises a crystal oscillator and a level decision module. The crystal oscillator generates an oscillating signal and an output clock signal. The level decision module detects the signal level of the oscillating signal and outputs the output clock signal when the signal level of the oscillating signal exceeds a first reference level. | 11-13-2008 |
| 20100264999 | OSCILLATION CIRCUIT, DRIVING CIRCUIT THEREOF, AND DRIVING METHOD THEREOF - An oscillation circuit, a driving circuit thereof, and a driving method thereof are provided. The driving circuit generates a second enable signal according to an output signal of an oscillator and a first enable signal. The second enable signal is transmitted to the oscillator. When a wave number of the output signal is smaller than a predetermined value during a predetermined period, the driving circuit adjusts a voltage level of the second enable signal. A voltage level of the first enable signal is equal to an enable voltage level. Through variations in voltage levels of the second enable signal, the oscillator is triggered to oscillate. | 10-21-2010 |
| 20130241662 | INTEGRATED CIRCUIT DEVICE HAVING AN INJECTION-LOCKED OSCILLATOR - A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up. | 09-19-2013 |
| 20140028411 | BUFFER INPUT IMPEDANCE COMPENSATION IN A REFERENCE CLOCK SIGNAL BUFFER - A system for managing a reference clock signal includes an XO; a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO; and a first IC coupled to the signal buffer. The first IC includes an XO input buffer configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit configured to be in an enabled, operational state when the XO input buffer is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism configured to switch the XO input buffer and the impedance equivalence circuit between the enabled state and the disabled state. | 01-30-2014 |
| 331174000 | Self-quenched | 1 |
| 20140240054 | OSCILLATION STOP DETECTION CIRCUIT AND ELECTRONIC DEVICE - Provided is an oscillation stop detection circuit having low current consumption, which is capable of detecting stop of oscillation regardless of whether an input signal stops at High or Low and thereby accurately measuring an oscillation stop detection period. The oscillation stop detection circuit includes: a pulse generation circuit for outputting a one-shot pulse in synchronization with an oscillation signal input from an input terminal; a capacitor including one terminal connected to a first power supply terminal and another terminal connected to an output terminal; a constant current circuit connected between the first power supply terminal and the another terminal of the capacitor; and a switch circuit connected between an output terminal of the pulse generation circuit and the another terminal of the capacitor, for connecting the another terminal of the capacitor to a second power supply terminal based on the one-shot pulse. | 08-28-2014 |
