| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 331047000 | Oscillator used to vary amplitude or frequency of another oscillator | 11 |
| 20100085123 | INJECTION-LOCKED CLOCK MULTIPLIER - Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, on injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one. | 04-08-2010 |
| 20100090770 | MULTIPLYING OSCILLATOR AND WIRELESS APPARATUS IN WHICH THE SAME IS INSTALLED - An object of the invention is to provide a multiplying oscillator capable of generating a high frequency signal by small circuit scale and power consumption in an oscillator for generating a signal with a frequency of a microwave band or more, and a local oscillator using this multiplying oscillator. A multiplying oscillator of the invention obtains a frequency signal four times or more a fundamental wave by adding a frequency adjusting unit | 04-15-2010 |
| 20100231307 | METHOD AND SYSTEM FOR DRIFT REDUCTION IN A LOW POWER OSCILLATOR (LPO) UTILIZED IN A WIRELESS COMMUNICATION DEVICE - A radio circuit may be driven by a high frequency oscillator such as a crystal oscillator that may have sleep and wake time intervals. The sleep time interval length may be adjusted. A low frequency oscillator or low power oscillator (LPO) that may experience frequency drift may regulate the sleep and/or wake time intervals. The frequency drift may be detected based on two or more LPO calibrations and/or one or more clock adjustments. The LPO frequency drift may be detected based on an LPO frequency sampled after a first LPO calibration and a corresponding LPO clock adjustment, a second LPO frequency sampled after a second LPO calibration and a time interval between the two frequency samples. The LPO may be calibrated based on the HFCXO output. Sleep time intervals may be adjusted by adding and/or subtracting a time interval to an expected time to wake the radio circuit. | 09-16-2010 |
| 20110037524 | OSCILLATOR AMPLIFIER WITH INPUT CLOCK DETECTION AND METHOD THEREFOR - An oscillator circuit has a crystal oscillator amplifier having only two clock input terminals, one being an input terminal and the other being an output terminal. The input terminal allows a user of the integrated circuit to choose between connecting a first clock signal generated from a crystal or a second clock signal generated by a non-crystal source to the input terminal. Control circuitry has a capacitor coupled in parallel with a transistor. Both are coupled in series with a resistive device at an output of the control circuitry to provide a control signal. Clock generation circuitry coupled to the crystal oscillator amplifier provides an oscillating output signal in response to an enable signal. In one form a comparator circuit provides the oscillating output signal. The control signal is used to ensure that inputs to the comparator circuit repeatedly cross each other over time. | 02-17-2011 |
| 20110063038 | ULTRA-COMPACT PLL WITH WIDE TUNING RANGE AND LOW NOISE - A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible. | 03-17-2011 |
| 20120161883 | COUPLED RING OSCILLATOR - A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator. | 06-28-2012 |
| 20120286881 | OSCILLATOR ARCHITECTURE HAVING FAST RESPONSE TIME WITH LOW CURRENT CONSUMPTION AND METHOD FOR OPERATING THE OSCILLATOR ARCHITECTURE - An oscillator architecture and a method for powering up/down the oscillator architecture are described. In one embodiment, an oscillator architecture includes a reference generator configured to generate reference signals and an in-phase/quadrature (IQ) oscillator configured to generate oscillation signals based on the reference signals. The reference generator includes a distributed start-up circuitry that includes multiple start-up circuits. The IQ oscillator includes at least one turbo comparator having a low power functional mode and a turbo functional mode. Other embodiments are also described. | 11-15-2012 |
| 20130222069 | Systems and Methods of Low Power Clocking for Sleep Mode Radios - Systems and methods of low power clocking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator. | 08-29-2013 |
| 20140266474 | SYSTEM AND METHOD FOR IMPROVED MEMS OSCILLATOR STARTUP - A MEMS resonator system comprises a MEMS resonator, kick start circuitry, feedback circuitry, an oscillator, and a switch. The MEMS resonator system is configured to provide a pulsed kick-start signal having a frequency and period such that energy delivered to the MEMS resonator is optimized in a short period of time, resulting is reduced oscillator startup time. The MEMS resonator system is configured to switch out the kick-start signal when the MEMS resonator oscillation has been achieved, and switch in feedback circuitry to maintain the MEMS resonator in a state of oscillation. | 09-18-2014 |
| 20160072514 | DIGITALLY CONTROLLED OSCILLATOR - In some embodiments, a digitally controlled oscillator includes a first oscillator a second oscillator and a switch. The second oscillator is selectively enabled in response to a controlled signal. The switch is coupled between the first oscillator and the second oscillator and is selectively conducted in response to the controlled signal, so that an oscillator signal is provided by the first oscillator when the switch is not conducted, and provided by the first oscillator and the second oscillator when the switch is conducted. | 03-10-2016 |
| 20160103466 | CLOCK SIGNAL GENERATING CIRCUIT - A clock signal generating circuit includes: an oscillator having a trimming function of arbitrarily adjusting an oscillation frequency of a first clock signal generated by the oscillator depending on trimming data; and a trimming data modulation part configured to dynamically change a reference trimming data for adjusting the oscillation frequency of the first clock signal to generate modulation trimming data, and output the modulation trimming data, as the trimming data, to the oscillator. | 04-14-2016 |
