| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 331001000 | AFC with logic elements | 72 |
| 20080204154 | Method and Enhanced Phase Locked Loop Circuits for Implementing Effective Testing - A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution. | 08-28-2008 |
| 20080246546 | Phase-Locked-Loop Circuit Having a Pre-Calibration Function and Method of Pre-Calibrating the Same - A phase-locked loop (PLL) integrated circuit includes an oscillation control voltage generating circuit therein. The oscillation control voltage generating circuit is configured to pre-scale an output current of a charge pump therein to a first level in response to disposing the PLL integrated circuit into a pre-calibration mode of operation. The oscillation control voltage generating circuit may be responsive to an input signal (e.g., SIN) and a feedback signal (e.g., SFEED), and the magnitude of the first level of the charge pump current during the pre-calibration mode of operation may be independent of any phase difference between the input signal and the feedback signal. | 10-09-2008 |
| 20080278248 | Pll Circuit - A PLL circuit is disclosed that comprises a controlling unit that switches at a predetermined timing to enable/disable the phase difference signal supplied from the phase comparator to the low pass filter; and a resistor element that is disposed between a predetermined potential and a signal line for supplying the phase difference signal from the phase comparator to the low pass filter, when the phase difference signal is enabled, the oscillation circuit performing oscillation operation based on the voltage signal corresponding to the phase difference signal, when the phase difference signal is disabled, the low pass filter being supplied with the predetermined potential through the resistor element to allow the oscillation circuit to perform oscillation operation based on the voltage signal generated depending on the supplied predetermined potential. | 11-13-2008 |
| 20090039969 | Voltage-controlled oscillator circuit and phase locked loop circuit using the same - To set a best oscillation state of a voltage-controlled oscillator (VCO) circuit, it is necessary to evaluate variability of manufactured ICs to specify set values based on the variability. Provided is an oscillator including: a terminal receiving a first signal; a VCO coupled to the terminal, the VCO oscillating to generate a second signal and to change a frequency of the second signal in response to an amplitude of the first signal, and revealing gain-slope characteristics in the frequency of the second signal versus the amplitude of the first signal; and a control circuit coupled to the VCO to alter the gain-slope characteristics in response to the amplitude of the first signal, the VCO having so-called self regulating characteristics in which the VCO is locked up based on the variability of the manufactured ICs without depending on external control. | 02-12-2009 |
| 20090102570 | PHASE LOCKED LOOP CIRCUIT AND WIRELESS COMMUNICATION SYSTEM - In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider on a rising edge of the reference signal and then calculates a phase difference between the reference signal and the PLL frequency-divided signal on the next rising edge of the reference signal in the same manner. From information on the two calculated phase differences, the TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals, the reference signal or the PLL frequency-divided signal, has a higher frequency and which has a lower frequency. Therefore, for each oscillation frequency band, the frequency comparison is completed in one cycle of the reference signal, allowing an oscillation frequency band selection circuit to detect an optimum oscillation frequency band corresponding to a predetermined PLL output frequency in a short time. | 04-23-2009 |
| 20090108946 | SWITCH, NEGATIVE RESISTANCE CELL, AND DIFFERENTIAL VOLTAGE CONTROLLED OSCILLATOR USING THE SAME - The present invention relates to a switch, a negative resistance cell, and a differential voltage controlled oscillator using the same. The present invention includes a first signal line provided in a first direction, a second signal line provided in parallel with the first signal line, and first to fourth gate electrodes, first to third source electrodes, and first to fourth drain electrodes formed between the first signal line and the second signal line, and provides a switch having electrodes in the order of the first gate electrode, the first drain electrode, the second gate electrode, the first source electrode, the third gate electrode, the second drain electrode, the fourth gate electrode, the second source electrode, the fifth gate electrode, the third drain electrode, the sixth gate electrode, the third source electrode, the seventh gate electrode, the fourth drain electrode, and the eighth gate electrode. According to the present invention, a differential voltage controlled oscillator for RF oscillation operation in the broadband area is realized by minimizing generation of parasitic components. | 04-30-2009 |
| 20090115538 | Oscillator Circuit and Method for Influencing, Controlling, or Regulating the Frequency of an Oscillator - An oscillator circuit according to the invention comprises an oscillator with a toggle circuit having an output and an inverting input, whereby the output is connected to the inverting input via a feedback resistor, the inverting input is connected, for example, to the ground, via a first oscillator capacitor, and also connected, for example, to the ground, via a second oscillator capacitor and via a control resistor whose value can be adjusted or electrically controlled, so that the frequency of the oscillator can be varied by increasing or decreasing the value of the control resistor. In order to control the value of the control resistor, preferably a modulated 1-bit signal is used that is integrated by an integrator. Preferably, the oscillator is an integral part of a closed-loop control circuit in which the frequency of the oscillator forms the actual value and a predefined target frequency forms the target value. | 05-07-2009 |
| 20090160566 | LOW VOLTAGE LOGEN - Low voltage LOGEN. LOGEN is a local oscillator generator. Two separately implemented dividers allow for relatively lower power dissipation while supporting multiple modes of operation within the communication device. Each of these two or more dividers has different phase noise characteristics. These at least two separately implemented dividers also allows for the supporting of at least two modes of operational within an apparatus. In certain applications (e.g., wireless applications), there is a need for relatively low phase noise characteristics therein, and the use of these at least two separately implemented dividers allows for the appropriate implementation of the relatively higher grade dividers in those areas that can benefit more there from. | 06-25-2009 |
| 20090174492 | PHASE-LOCKED LOOP WITH SELF-CORRECTING PHASE-TO-DIGITAL TRANSFER FUNCTION - A phase-locked loop includes a phase-to-digital converter portion as well as a novel correction portion. The phase-to-digital converter (PDC) portion outputs a stream of first phase error words. The novel correction portion receives the first phase error words and generates a stream of second phase error words that is supplied to a loop filter. The PDC portion has a phase-to-digital transfer function that exhibits certain imperfections. In a first example, the correction portion determines an average difference between pairs of first phase error words, and uses this average difference to normalize the first phase error words to correct for changes in PDC portion transfer function slope due to changes in delay element propagation delay. In a second example, the correction portion corrects for gain mismatches in PDC portion transfer function. In a third example, the correction portion corrects for offset mismatches in PDC portion transfer function. | 07-09-2009 |
| 20090184773 | Hybrid Pll Combining Fractional-N & Integer-N Modes of Differing Bandwidths - A single-loop PLL that operates in a narrower-bandwidth, integer-N mode during phase lock and in a wider-bandwidth, fractional-N mode during transient. This hybrid PLL simultaneously achieves the fast-locking advantage of the fractional-N PLL and design simplicity of the integer-N PLL. The frequency division mode switching facilitates a digital protocol to execute bandwidth switching, which increases the degree of design freedom for the bandwidth switching. | 07-23-2009 |
| 20090243736 | Phase locked loop circuit and integrated circuit for the same - The present invention provides a phase locked loop circuit including: a voltage controlled oscillator; a variable frequency-dividing circuit; a phase comparing circuit for comparing a phase of the frequency-dividing signal a charge pump circuit; a loop filter; a voltage supplying circuit; a frequency measuring circuit; and a voltage measuring circuit. | 10-01-2009 |
| 20090251226 | LOCK DETECTION CIRCUIT FOR PHASE LOCKED LOOP - A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal. | 10-08-2009 |
| 20100045391 | FREQUENCY LOCKING STRUCTURE APPLIED TO PHASE-LOCKED LOOPS - A frequency locking structure applied to phase-locked loops (PLL) utilizes a common factor to reduce the difference between an output signal of oscillation and an input signal of reference for the jitter reduction of the input signal of reference. Moreover, a count value of clock signal is an input of a greatest-common-factor calculator to acquire an adaptive value and a feedback adaptive value for the common factor of a divider. Such a frequency locking structure both prevents the PLL from being in error about outputting frequency and dynamically adjusts the common factors for different purposes. | 02-25-2010 |
| 20100225406 | SELF-CALIBRATING OSCILLATOR - A self-calibrating oscillator that increases the output frequency accuracy without using a charge pump includes an oscillation circuit, a pulse counter, a charging circuit, a reset circuit, a calibration circuit, and a timing control unit. The pulse counter counts a pulse signal having frequency f | 09-09-2010 |
| 20100295624 | BROADBAND FREQUENCY SYNTHESIZER FOR SUPPRESSING PARASITIC LOW FREQUENCY TRANSMISSIONS - The broadband frequency synthesizer ( | 11-25-2010 |
| 20100308927 | METHODS AND APPARATUS FOR TUNING DEVICES HAVING MECHANICAL RESONATORS - Methods and apparatus for tuning devices having mechanical resonators are described. In one implementation, a mechanical resonator and a phase shifter are configured in a feedback loop, so that the phase shifter shifts the phase of the resonator output signal. The amount of phase shift induced by the phase shifter may be variable. In another implementation, an LC tuning subcircuit is coupled to a mechanical resonator. In some implementations, the LC tuning subcircuit has a variable capacitance. One or more of the apparatus described herein may be implemented as part, or all, of a microelectromechanical system (MEMS). | 12-09-2010 |
| 20100321122 | SYSTEM AND METHOD FOR REDUCING HOLDOVER DURATION - A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of: timing information; frequency information; phase information; and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of: timing information; frequency information; phase information and combinations thereof, wherein the second signal is used for disciplining the LO. The LO error corrector is configured to: if the second signal is unavailable to discipline the LO, discipline the LO using a source that is less accurate than the second signal. Upon the second signal becoming at least temporarily available, the LO corrector determines an offset error of the LO relative to the second signal. If the second signal becomes unavailable before the device uses the second signal to discipline the LO on an ongoing basis, the LO corrector corrects the offset error of the LO relative to the second signal based information obtained during the second signal's temporary availability and disciplines the LO using a source that is less accurate than the second signal until the second signal becomes at least temporarily available at a subsequent time. | 12-23-2010 |
| 20110063039 | Synchronous oscillator, clock recovery apparatus, clock distribution circuit, and multi-mode injection circuit - Disclosed herein is a synchronous oscillator including at least one injection circuit having an injection signal input terminal, an internal clock signal input terminal, and a clock output terminal, and at least one delay circuit cascaded to the injection circuit. | 03-17-2011 |
| 20110074514 | FREQUENCY MEASUREMENT CIRCUIT AND PLL SYNTHESIZER PROVIDED THEREWITH - A frequency measurement circuit includes: a first counter that counts a number of edges of a clock signal; a counter latch circuit that stores a first count value of the first counter in response to a reference edge corresponding to a reference clock; a first delay circuit that includes a plurality of first unit delay circuits coupled in series and receives the clock signal; a plurality of first delay latch circuits that latch a respective output among the plurality of first unit delay circuits; a first edge detection circuit that detects the edge in the first delay circuit based on the outputs of the plurality of first delay latch circuits; and a first calculator that calculates a cycle or a frequency of the clock signal based on the first count value between two reference edges and position information corresponding to a edge detected between the two reference edges. | 03-31-2011 |
| 20110115570 | CLOCK GENERATOR - This invention discloses a clock generator capable of automatically adjusting output clock when process, voltage, or temperature variation occurred. The clock generator comprises: a current generator, for generating a first current and a second current according to a bias signal; an oscillator, coupled to the current generator, for generating a clock signal according to the first current; a frequency detector, coupled to the oscillator, for generating a control signal according to the clock signal and a reference signal; and a bias voltage adjuster, coupled to the current generator and the frequency detector, for adjusting the bias signal according to the control signal; wherein, when the signal frequency of the clock signal changes, the bias signal corresponds to the bias voltage adjuster, to adjust the first current and the second current. | 05-19-2011 |
| 20110140791 | ELECTRONIC CIRCUIT FREQUENCY GENERATION - An oscillation signal with a selectable frequency is generated with a phase locked loop ( | 06-16-2011 |
| 20110169582 | Spread Spectrum Clock Generators and Electronic Devices Including the Same - Spread spectrum clock generators and electronic devices including the same are provided. A spread spectrum clock generator may include an oscillation circuit that is configured to receive a first spread spectrum clock signal and to output an average frequency signal corresponding to an average frequency of the first spread spectrum clock signal. The spread spectrum clock generator may also include a phase lock loop that is configured to receive the average frequency signal and to generate a second spread spectrum clock signal. The spread spectrum clock generator may further include a control circuit that is configured to receive the first and second spread spectrum clock signals and to output a phase lock loop control signal to control the phase lock loop such that an average frequency of the second spread spectrum clock signal approaches the average frequency of the first spread spectrum clock signal. | 07-14-2011 |
| 20110234327 | LOCAL OSCILLATOR AND PHASE ADJUSTING METHOD FOR THE SAME - According to one embodiment, a local oscillator includes: an adder that adds an oscillator integer phase and an oscillator fraction phase and outputs the addition value as first phase information; a delayer that outputs an addition output of a frequency command word at one clock before and second phase information as estimated oscillator phase data; a correcting unit that outputs an addition of compensation information to the first phase information as the second phase information when |the first phase information−the estimated oscillator phase data|>|the first phase information+the compensation information−the estimated oscillator phase data| is satisfied and otherwise outputs the first phase information as the second phase information. | 09-29-2011 |
| 20120075028 | LC Oscillator - An oscillator including a capacitive element and an inductive element for generating an output signal having a predetermined frequency, the capacitive element comprising two or more capacitive arrays, each array having one or more capacitors that are switchably connectable in parallel with the inductive element so as to control the frequency of the output signal, and at least one of those arrays being connected to only part of the inductive element such that, when a capacitor in said one array is connected to that part, the resulting change in the frequency of the output signal is smaller than it would have been if the capacitor had been connected to the whole of the inductive element. | 03-29-2012 |
| 20120139650 | CHARGE PUMP AND PHASE DETECTION APPARATUS, PHASE-LOCKED LOOP AND DELAY-LOCKED LOOP USING THE SAME - A charge pump includes a first current source, a second current source, a first switch, a second switch, a third switch, a fourth switch, a reset switch, an inverse reset switch and a capacitance. The first and third switches have first terminals coupled to the first current source. The second and fourth switches have first terminals coupled to the second current source. The first, second and reset switches have second terminals coupled to a first terminal of the inverse reset switch. The reset switch has a first terminal coupled to second terminals of the third and fourth switches. The first and second switches are respectively controlled by first and second control signals, the third and fourth switches are respectively controlled by inverse signals of the first and second control signals, and the inverse reset switch is controlled by the inverse reset signal. | 06-07-2012 |
| 20120154064 | METHOD AND APPARATUS FOR MULTI-POINT CALIBRATION FOR SYNTHESIZING VARYING FREQUENCY SIGNALS - A fast settling frequency synthesizer is disclosed. The particular capacitor to frequency relationship in the band of operation is first determined. The calculation can be performed by determining the capacitor to frequency relationship at two points and calculating the slope. Once these parameters are known, then, for any change in frequency due to a channel hop, the appropriate capacitor value can be determined. | 06-21-2012 |
| 20120229222 | WRISTWATCH WITH ATOMIC OSCILLATOR - A wristwatch, which comprises an atomic oscillator comprising a system for detecting the beat frequencies obtained by the Raman effect. | 09-13-2012 |
| 20120319786 | AUTOCONFIGURABLE PHASE-LOCKED LOOP WHICH AUTOMATICALLY MAINTAINS A CONSTANT DAMPING FACTOR AND ADJUSTS THE LOOP BANDWIDTH TO A CONSTANT RATIO OF THE REFERENCE FREQUENCY - A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal. | 12-20-2012 |
| 20130194047 | CLOCK DISTRIBUTOR AND ELECTRONIC DEVICE - A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part. | 08-01-2013 |
| 20140049329 | DIVIDER-LESS PHASE LOCKED LOOP (PLL) - One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulse | 02-20-2014 |
| 20140139294 | ALKALI METAL CELL, ATOMIC OSCILLATOR, AND ALKALI METAL CELL FABRICATING METHOD - An alkali metal cell is disclosed, including a substrate in which is formed an opening which penetrates from one face to the other face thereof; a first transparent substrate bonded to the other face of the substrate; and a second transparent substrate bonded to the one face of the substrate, wherein an alkali metal is sealed into a space surrounded by the first transparent substrate and the second transparent substrate in the opening of the substrate, wherein, in the substrate and the second transparent substrate, the space is enclosed by a bonding between a first bonding metal layer formed by a first bonding metal and a second bonding metal layer formed by a second bonding metal, and wherein the second bonding metal layer has a bonding temperature higher than that of the first bonding metal layer. | 05-22-2014 |
| 20140159824 | Orthogonally referenced integrated ensemble for navigation and timing - An orthogonally referenced integrated ensemble for navigation and timing includes a dual-polyhedral oscillator array, including an outer sensing array of oscillators and an inner clock array of oscillators situated inside the outer sensing array. The outer sensing array includes a first pair of sensing oscillators situated along a first axis of the outer sensing array, a second pair of sensing oscillators situated along a second axis of the outer sensing array, and a third pair of sensing oscillators situated along a third axis of the outer sensing array. The inner clock array of oscillators includes a first pair of clock oscillators situated along a first axis of the inner clock array, a second pair of clock oscillators situated along a second axis of the inner clock array, and a third pair of clock oscillators situated along a third axis of the inner clock array. | 06-12-2014 |
| 20140266478 | LOW POWER OSCILLATOR WITH NEGATIVE RESISTANCE BOOSTING - Representative implementations of devices and techniques provide increased negative resistance to an oscillator circuit. A capacitance divider and/or a feedback loop may be employed to increase the negative resistance of the oscillator circuit at the same current consumption and with the same load capacitance. Further, a constant bias circuit may be employed to conserve and/or reduce the current consumption of the oscillator circuit. | 09-18-2014 |
| 20150372681 | SYSTEMS AND METHODS FOR CLOCK SYNCHRONIZATION IN A DATA ACQUISITION SYSTEM - A system may include a sampling circuit, a temperature calibration system, a phase detector, a virtual phase-locked loop, and a sample rate converter. The sampling circuit may be configured to generate a series of digitally-sampled data at a sampling frequency provided by a local clock. The temperature calibration system may be configured to determine a temperature-based timing compensation with respect to the local clock. The phase detector may be configured to estimate an error of the local clock in view of the reference clock. The virtual phase-locked loop may be configured to generate a virtual clock based on the temperature-based timing compensation and the error. The sample rate converter may be configured to generate a corrected series of digitally-sampled data in response to the virtual clock by interpolating the series of digitally-sampled data to correct for the error. | 12-24-2015 |
| 20150381191 | VARIABLE DELAY COMPONENT RING OSCILLATOR WITH PHASE SHIFTING SELECT SWITCH - A circuit includes a ring oscillator component and a phase selecting component. The ring oscillator component outputs a clock signal having a clock frequency, f | 12-31-2015 |
| 20160065220 | CMOS OSCILLATOR HAVING STABLE FREQUENCY WITH PROCESS, TEMPERATURE, AND VOLTAGE VARIATION - A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage. | 03-03-2016 |
| 20160182066 | AUTO FREQUENCY CONTROL CIRCUIT AND RECEIVER | 06-23-2016 |
| 20080218282 | Hybrid Stochastic Gradient Based Digitally Controlled Oscillator Gain KDCO Estimation - A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The adaptation algorithm determines a true stochastic gradient between a forcing function and its corresponding system measure to estimate the system parameters being adapted. A momentum term is generated and injected into the adaptation algorithm in order to stabilize the algorithm by adding inertia against any large transient variations in the input data. In the case of adaptation of DCO gain K | 09-11-2008 |
| 20080231381 | Method and system for gennerating noise in a frequency synthesizer - A method and system for generating noise in a frequency synthesizer are provided. The method includes generating a noise portion of an input signal within the frequency synthesizer and appending the noise portion to a control portion of the input signal. | 09-25-2008 |
| 20080266004 | Phase-locked loop and method for operation an electromechanical system - A phase-locked loop for controlling an electromechanical component comprises a digitally controlled oscillator ( | 10-30-2008 |
| 20080284530 | PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT - A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs. | 11-20-2008 |
| 20080284531 | FRACTIONAL-N SYNTHESIZED CHIRP GENERATOR - A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time. | 11-20-2008 |
| 20080297263 | Filter-based lock-in circuits for PLL and fast system startup - All embodiments of the present invention basically include an upper transistor and a lower transistor connected in series between a power supply and ground. The upper transistor and the lower transistor have a shared source (or drain) terminal which becomes a single bidirectional node. They further comprise a sensing gate and a logic gate. The sensing inverter has a function of sensing a voltage at the single bidirectional node and comparing it with an input transition voltage since an input terminal of the sensing inverter is connected to the single bidirectional node. An initial voltage at the single bidirectional node of the filter-based lock-in circuit is almost the same as the input transition voltage of the sensing inverter, where the input transition voltage is an input voltage which causes an output voltage to be V | 12-04-2008 |
| 20080309420 | FRACTIONAL DIVIDER - A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate. | 12-18-2008 |
| 20080309421 | PHASE LOCKED LOOP WITH TWO-STEP CONTROL - A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (f | 12-18-2008 |
| 20090002083 | Oscillation Circuit, Power Supply Circuit, Display Device, and Electronic Apparatus - An oscillation circuit, power supply circuit, display device using same, and electronic apparatus which can be built in a display panel without causing an increase of cost and do not need any adjustment work, each having a pulse generation portion | 01-01-2009 |
| 20090051450 | CLOCK GENERATION CIRCUIT AND CLOCK GENERATION CONTROL CIRCUIT - According to a preferred embodiment, a clock signal generation circuit includes an oscillating circuit configured to output a clock signal having a clock frequency corresponding to a control signal, a counter configured to generate a count value by counting a pulse number of the clock signal outputted from the oscillating circuit during a predetermined time period, a subtracting circuit configured to produce differential data by subtracting the count value from a preset value previously set based on a predetermined clock frequency, a control signal correcting circuit configured to generate a correcting control signal by correcting a value of the control signal based on the differential data, and a digital-analog converter circuit configured to convert the correcting control signal into an analog correcting control signal and output the converted analog correcting control signal to the oscillating circuit. This clock signal generation circuit can prevent increasing of the circuit size or the system size due to a resistor, a capacitor element, etc., used in a PLL (Phase Locked Loop) without using a central processing unit. | 02-26-2009 |
| 20090079508 | PLL CIRCUIT - Disclosed herein is a phase lock loop (PLL) circuit capable of executing digital control of an oscillation circuit thereof by using a dividing ratio represented by a digital value obtained by dividing an oscillation frequency by a reference frequency. The PLL circuit includes a phase comparator for comparing the digital value obtained by converting the dividing ratio with a digital value representing each cumulative addition value of a clock count expressed in a decimal-point format representing the oscillation signal in each period of a reference signal, a loop-gain control section configured to control the loop gain of the PLL circuit, and an output converging section configured to converge an output by the phase comparator. | 03-26-2009 |
| 20090085677 | Locked Loop System - This disclosure relates to a phase locked loop and a frequency locked loop. | 04-02-2009 |
| 20090085678 | METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A DIGITALLY CONTROLLED OSCILLATOR - Aspects of a method and system for digitally controlling a VCO are provided. In this regard, a phase difference between two signals may be determined, represented digitally, and utilized to adjust the output frequency of a LOGEN. In this regard, the output frequency may be adjusted by controlling one or more switching elements coupled to one or more reactances, which may comprise a plurality of capacitors coupled in parallel, within the LOGEN. The phase difference may be determined by digitally multiplying the two signals, and the resulting product may be delta-sigma modulated. The two signals may be generated via one or more accumulators, which may be controlled, at least in part, by a digital control word. The control word may be retrieved from a look-up table. The accumulators may be clocked by a frequency divided version of the LOGEN output. | 04-02-2009 |
| 20090085679 | DUAL PATH PHASE LOCKED LOOP (PLL) WITH DIGITALLY PROGRAMMABLE DAMPING - In a method and apparatus for controlling damping and bandwidth in a phase locked loop (PLL), a loop filter is configured to have a dual path for charge pump current. A 3 dB bandwidth of the PLL is controlled by adjusting gain of a proportional current path. An integral current path includes a gating circuit to digitally control an amount of time an integral charge pump current received is passed through as an effective integral charge pump current. A resistor and capacitor (RC) circuit filters the proportional and effective integral charge pump currents, thereby providing a filtered input to a voltage controlled oscillator. Damping and hence peaking of the PLL is precisely controlled by sampling one of every p samples of the integral charge pump current to provide the effective integral charge pump current, p being an integer. | 04-02-2009 |
| 20090096537 | Digital-Controlled Oscillator for Eliminating Frequency Discontinuities AND ALL-DIGITAL PHASE-LOCKED LOOP USING THE SAME - A digital-controlled oscillator (DCO) is utilized in an all-digital phase-locked loop for eliminating frequency discontinuities. The DCO includes a tank module and a negative gm cell. The tank module comprises a plurality of cells, at least a portion of the cells comprising a first tracking set and a second tracking set for respectively handling an odd bit or an even bit. The odd bit and the even bit are related to an integer signal, a fractional signal or a combination thereof, the fractional signal is indicated by a primary voltage inputted to the DCO. With the DCO, frequency discontinuities and undesired spurs are eliminated. | 04-16-2009 |
| 20090096538 | ALL-DIGITAL PHASE-LOCKED LOOP, LOOP BANDWIDTH CALIBRATION METHOD, AND LOOP GAIN CALIBRATION METHOD FOR THE SAME - For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner. | 04-16-2009 |
| 20090096539 | Error Protection Method, TDC module, CTDC Module, All-Digital Phase-Locked Loop, and Calibration Method thereof - An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well. | 04-16-2009 |
| 20090096540 | LOGICAL LEVEL CONVERTER AND PHASE LOCKED LOOP USING THE SAME - A logical level converter generates an output signal by which a logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal. | 04-16-2009 |
| 20090102569 | PHASE ADJUSTMENT IN PHASE-LOCKED LOOPS USING MULTIPLE OSCILLATOR SIGNALS - Phase-locked loop (PLL) logic comprises an oscillator that produces a first oscillator signal and phase detect logic that determines a phase difference between the first oscillator signal and a second oscillator signal. After the second oscillator signal is replaced by a third oscillator signal, the phase detect logic determines another phase difference between the first oscillator signal and the third oscillator signal. The PLL removes the phase difference from the another phase difference to produce an intermediate signal. The oscillator adjusts the first oscillator signal using the intermediate signal. | 04-23-2009 |
| 20090108945 | FREQUENCY SYNTHESIZER - A frequency synthesizer switches the frequency at a high rate, is of low power consumption, and has a high signal-to-noise ratio. CMOS quadrature VCOs | 04-30-2009 |
| 20090134946 | Oscillation frequency control circuit - Provided is an oscillation frequency control circuit, which corrects its own frequency so that it can hold an oscillation frequency stably even when it does not have an input of a highly stable reference signal but makes a self-run. The oscillation frequency control circuit comprises a voltage-controlled oscillator, a frequency divider, a phase comparator, a loop filter, a detecting circuit for detecting an external reference signal, a PWM circuit for generating pulses, when pulse generating information inputs, to output the pulses to the loop filter, a memory for storing the pulse generating information corresponding to voltage information, a switch for turning ON/OFF the connection between the phase comparator and the loop filter, and a CPU for turning ON the switch, if the level of the external reference signal detected by the detecting circuit is within a proper range, but OFF the switch, if the level is outside of the proper range, thereby to output the pulse generating information stored in the memory, to the PWM circuit. | 05-28-2009 |
| 20090146747 | NOVEL METHOD OF FREQUENCY SYNTHESIS FOR FAST SWITCHING - A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL). | 06-11-2009 |
| 20090160564 | ENHANCED ALL DIGITAL PHASE-LOCKED LOOP AND OSCILLATION SIGNAL GENERATION METHOD THEREOF - An All Digital PLL (ADPLL) and oscillation signal generation method using the ADPLL is provided for generating a spur-free oscillation signal by improving the frequency resolution of the ADPLL. An all digital phase-locked loop of the present invention includes a digitally controlled oscillator for generating an oscillation signal having a frequency corresponding to an inputted control signal, a re-timer for retiming a reference clock based on the oscillation signal, a feedback circuit for accumulating a number of clocks of the oscillation signal within a time period and generating a phase information of the oscillation signal in synchronization with the retimed reference clock, a sigma-delta modulator for sigma-delta modulating a frequency command signal into a modulation signal having a less number of bits than a number of bits of the frequency command signal, a reference phase accumulator for accumulating phases corresponding to the modulation signal, a phase difference detector for generating a phase difference information between an output signal of the reference phase accumulator and the phase information, and a digital loop filter for filtering the phase difference information to generate the control signal. | 06-25-2009 |
| 20090160565 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator | 06-25-2009 |
| 20090174490 | PHASE LOCKED LOOP WITH ADAPTIVE FILTER FOR DCO SYNCHRONIZATION - A digital phase locked loop has a digital controlled oscillator, a feedback loop coupled to the output of said digital controlled oscillator, a phase detector for comparing a feedback signal from said feedback loop with a reference signal to produce a phase error signal, and a low pass filter for filtering the phase error signal for controlling said digital controlled oscillator. A bandwidth calculation unit calculates the required filter bandwidth based on the phase error. The bandwidth calculation unit then controls the bandwidth of said low pass filter, which is thus adaptively adjusted in accordance with the phase error. | 07-09-2009 |
| 20090174491 | Mixed-Mode PLL - A mixed-mode PLL is disclosed. The mixed-mode PLL comprises an analog phase correction path and a digital frequency correction path. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. | 07-09-2009 |
| 20090212876 | OSCILLATOR CONTROLLING APPARATUS - An oscillation controlling apparatus has a digitally-controlled oscillator configured to output an oscillating signal with an oscillation frequency according to an oscillator adjustment signal, and include a variable current source which supplies operation current based on an operation current control signal, a phase difference calculating unit configured to calculate a phase difference between the oscillating signal and a reference signal to output a phase difference signal, a filter configured to smooth a difference between a phase instruction signal setting the oscillation frequency of the digitally-controlled oscillator and the phase difference signal to output the oscillator adjustment signal, and a controlling unit configured to obtain the oscillator adjustment signal, output the operation current control signal so as to vary a value of the operation current, extract the value of the operation current at which the oscillator adjustment signal becomes the maximum value, and output the operation current control signal so that the operation current supplied by the variable current source becomes the extracted value. | 08-27-2009 |
| 20090231050 | DIGITAL FRACTIONAL-N PHASE LOCK LOOP AND METHOD THEREOF - A method for reducing a phase noise in a digital fractional-N phase lock loop (PLL) is disclosed. The method comprises: quantifying a time difference between a reference clock and a feedback clock into a time difference signal; generating a residual error signal according to the time difference signal and an instantaneous error signal; filtering the residual error signal to generate a control code; controlling an oscillator using the control code to generate an output clock; receiving a fractional number between 0 and 1 to generate the instantaneous error signal; and dividing down the output clock by a divisor value according to the fractional number. | 09-17-2009 |
| 20090243735 | FREQUENCY DIVERSE DISCRETE-TIME PHASE-LOCK DEVICE AND APPARATUS - A discrete-time phase lock loop (DTPLL) includes an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC. The DTPLL also includes a digital signal processor (DSP). The DSP includes a loop controller state machine; a phase detector; a counter, operative to receive clock signals from the oscillator and to provide a count value to the phase detector; a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and a loop filter operative to provide a control effort value based on an output from the phase detector. Based on the phase error value, an output of the oscillator is changed to reduce the phase error to a steady state value. | 10-01-2009 |
| 20090251225 | Fractional And Integer PLL Architectures - A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied. | 10-08-2009 |
| 20090256642 | LOCKED-LOOP CIRCUIT - A locked loop circuit, comprising: an input, for receiving an input signal; controllable modification circuitry for generating a signal; an output for the generated signal; a feedback loop for the generated signal; a comparator for comparing the input signal and a signal from the feedback loop, and for producing a comparison signal; circuitry for controlling the modification circuitry on the basis of the comparison signal; and dither circuitry, for adjusting the comparison signal by applying a dither value, where the dither value is non-zero at all times. | 10-15-2009 |
| 20090278618 | System and method for cycle slip prevention in a frequency synthesizer - An improved method of cycle slip prevention in a frequency synthesizer is achieved by determining phase error between a divided VCO and reference, determining whether a phase error of a full cycle slip has occurred and in which direction and altering the phase of the VCO divided signal in the amount and direction to reduce the phase error to less than one reference cycle. The result is an improved transfer function of the PFD, proportional to the phase error in the region −2*pi to 2*pi, and fixed close to maximum when the phase error exceeds the above interval. This invention is achieved with the addition of digital circuitry to monitor and control the PFD and the VCO divider, and does not require additional analog charge pump circuitry. | 11-12-2009 |
| 20090289730 | DIGITAL PHASE DETECTOR AND PHASE-LOCKED LOOP - A digital phase detector is provided that can be easily implemented in gate array or FPGA, to accurately quantize a phase difference of two clocks and convert to a digital value without using delay elements. The digital phase detector includes: a multiplier for, when two clocks have frequencies close to an integer ratio, receiving a first clock and multiplying by M/N; F/F for latching a second clock by an output clock of the multiplier; a differential circuit for differentiating an output of the F/F; a counter for receiving the output clock of the multiplier; a latch circuit for holding an output of the counter according to an output of the differential circuit; a first adder for adding an output of the latch circuit; a second adder for subtracting an output of the first adder from a fixed value; and an accumulator for sequentially integrating an output of the second adder. | 11-26-2009 |
| 20090302958 | DIGITALLY CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP CIRCUIT USING THE DIGITALLY CONTROLLED OSCILLATOR - A digitally controlled oscillator includes a differential inductor including a positive terminal which outputs a positive-phase oscillation signal, a negative terminal which outputs a negative-phase oscillation signal, and a center tap, and including a first contact point in an arbitrary position between the positive terminal and the center tap, and a second contact point in a position corresponding to the first contact point between the negative terminal and the center tap, a first variable capacitor bank connected between the positive terminal and the negative terminal and including a plurality of first variable capacitors which switch capacitance between two values according to a first digital control code, and a second variable capacitor bank connected between the first contact point and the second contact point and including a plurality of second variable capacitors which switch capacitance between two values according to a second digital control code. | 12-10-2009 |
| 20100019855 | SYSTEMS AND METHODS USING PROGRAMMABLE FIXED FREQUENCY DIGITALLY CONTROLLED OSCILLATORS FOR MULTIRATE LOW JITTER FREQUENCY SYNTHESIS - The disclosure provides systems and methods for programmable fixed frequency digitally controlled oscillators for multirate low jitter frequency synthesis. The present invention utilizes a digital control element, such as a complex programmable logic device (CPLD) or field programmable gate array (FPGA), to monitor the frequency offset of a DCO with respect to one or more timing module (TM) references. The frequency offset is measured by aligning the phase of a DCO feedback divider to the phase of a reference divider, and then counting the number of pulses in the DCO between the falling edges of the feedback to determine a frequency error. Falling edge detection is used to determine a sign of the error. The digital control element then calculates a frequency correction based on a linear scaling factor to send a new control word to the DCO to reduce the frequency error. | 01-28-2010 |
| 20100033257 | PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT - A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs. | 02-11-2010 |
| 20100039182 | ADAPTIVE NOISE CANCELLATION FOR FRACTIONAL-N PHASE LOCKED LOOP - An embodiment of the invention is a circuit for adaptive phase noise cancellation for a fractional-N PLL. A preferred embodiment employs a split loop filter architecture. Two loop filter halves separately drive half-sized parallel varactors in a voltage controlled oscillator (VCO) and also drive a differential-input lowpass frequency selective circuit, e.g., a differential-input integrator in a least mean squared (LMS) feedback loop. The output of the differential-input lowpass frequency selective circuit controls the gain matching of a phase noise cancellation path to minimize phase noise arising from quantization error associated with the sequence of divider modulus values in the fractional-N PLL. The two varactor capacitances add together in the VCO tank, so the VCO frequency depends on the common-mode loop filter voltage and is relatively insensitive to differential-mode voltage. In contrast, the differential integrator operates on the differential-mode voltage from the two loop filter halves but attenuates their common-mode voltage. | 02-18-2010 |
| 20100039183 | DIGITAL FAST-LOCKING FREQUENCY SYNTHESIZER - A digital PLL frequency synthesizer characterized by fast-locking and low-jitters is presented. The PLL comprises a phase detector, a controllable oscillator, a loop filter having an automatically-adjusted loop gain, a feedback phase integration circuit, and a reference phase integration circuit. Fast-locking is achieved by dynamically adjusting forward-path gain and integral-path gain according to the output of the phase detector and the output of the integral-path during phase tracking. A skew-compensated counter circuit is proposed, which incorporates an asynchronous counter, a data register and a sample phase generator and features high-speed and low-power operation. | 02-18-2010 |
| 20100060368 | ACTIVE YIG OSCILLATOR DRIVING DEVICE AND DRIVING METHOD THEREOF - An active YIG oscillator driving device is comprised of: an YIG oscillator including a main coil, an FM coil, a frequency generator operating to generate an output frequency in response to a magnetic field generated from the FM coil; a phase locker setting the output frequency to a target frequency by controlling an amount of current provided into the FM coil and adjusting the output frequency; and a main coil controller regulating the amount of current provided into the main coil, if the output frequency varies out of a controllable range by the FM coil, and adjusting the output frequency. A time for setting the output frequency of the YIG oscillator is shortened to improve the stability of the output frequency thereof against environmental conditions. | 03-11-2010 |
| 20100066456 | CLOCK REPRODUCING APPARATUS - A clock reproducing apparatus includes a clock reproducing circuit having: a gated oscillator having an oscillating circuit of two routes; and a frequency control circuit for comparing a phase of an output of the gated oscillator with a phase of a reference clock, and supplying a phase control signal to the gated oscillator based on the comparison result so as to set a delay time, input data is input to a reset input terminal of the gated oscillator, and different route of the two routes of the oscillating circuit operates depending on a case where the input data is “H” and a case where the input data is “L”. | 03-18-2010 |
| 20100102894 | DIGITALLY CONTROLLED OSCILLATOR WITH IMPROVED DIGITAL FREQUENCY CALIBRATION - Techniques for calibrating digitally controlled oscillators (DCOS) are disclosed. In one aspect of the disclosure, an initial set of control codes for operating the DCO with a coarse frequency tuning bank with multiple overlapping coarse frequency tuning segments (LTBs) and one fine main frequency tuning bank (MTB) is determined. A range of output frequencies produced from the initial set is identified. Instances of overlap are identified in the frequency range between consecutive LTB segments. An offset in the MTB is added that corresponds to the overlap instance between consecutive LTBs to establish a revised set. The revised control codes are utilized to tune the DCO over the desired frequency range. | 04-29-2010 |
| 20100117747 | SYSTEMS AND METHODS WITH REDUCED REFERENCE SPURS USING A CRYSTAL OSCILLATOR FOR BROADBAND COMMUNICATIONS - Systems and methods are provided. In this regard, a representative system incorporates a crystal oscillator circuit and a digital automatic level control circuit. The digital automatic level control circuit is operative to: convert an oscillation amplitude of the crystal oscillator circuit to a proportional DC voltage; convert the DC voltage to a corresponding digital code representation; and adjust bias current and oscillator loop gain such that a desired oscillation amplitude is set. | 05-13-2010 |
| 20100171560 | System and method for detecting FRO locking - The detection of locking of a free running oscillator (FRO) is disclosed, including taking periodic samples of the FRO output, storing each new sample in a sample storage medium, each time a new sample is stored searching the stored samples for at least one repeating pattern, counting consecutive sampling instances in which a repeating pattern is found, and indicating when the count reaches a preselected threshold number. | 07-08-2010 |
| 20100188158 | OPTIMAL DITHERING OF A DIGITALLY CONTROLLED OSCILLATOR WITH CLOCK DITHERING FOR GAIN AND BANDWIDTH CONTROL - A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL. | 07-29-2010 |
| 20100219894 | PHASE SHIFT PHASE LOCKED LOOP - A phase shift phase locked loop (PSPLL) are described. The phase shift PLL includes a PLL and a phase adjusting circuit coupled to the inputs of the PLL. The phase adjusting circuit has a first input, a first output, a second input, a third input, and a second output. The first output and the second output are coupled to a first input and a second input of the PLL, respectively. The second input of the phase adjusting circuit receives a feedback signal and the third input of the phase adjusting circuit receives a control signal. The phase adjusting circuit receives a reference signal and sends a first output signal and a second output signal based on the reference signal to the PLL to adjust a phase of an output signal of the PLL in an increment less than a time period of the output signal of the PLL. | 09-02-2010 |
| 20100231310 | MIXED-MODE PLL - A mixed-mode PLL is disclosed. The mixed-mode PLL comprises a digital sigma-delta modulator, a low pass filter, and a digital controlled oscillator. The digital sigma-delta modulator receives a fractional bit signal. The low pass filter is coupled to the digital sigma-delta modulator. The low pass filter receives an output signal of the digital sigma-delta modulator and converts the output signal to an analog control signal. The digital controlled oscillator comprises a varactor dynamically coupled to the low pass filter and receiving the analog control signal. | 09-16-2010 |
| 20100244971 | TIME-TO-DIGITAL CONVERTER (TDC) WITH IMPROVED RESOLUTION - A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths. | 09-30-2010 |
| 20100264993 | PLL WITH LOOP BANDWIDTH CALIBRATION CIRCUIT - A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU. | 10-21-2010 |
| 20100289590 | Self-trim and self-test of on-chip values - A self-trim circuit provides a technique to trim a CUT (circuit under trim) using a LSB offset to determine the best digital value to trim the CUT. The self-trim circuit is also used to self-test the digital and analog portions of the self-trim circuitry, whereby the existence of a digital stuck at fault condition is detected. A state machine controls a digital stack to couple digital trim data to the CUT and read the output of a comparator circuit that signifies when a proper digital trim value has been used. Thereafter the proper digital trim value is stored into a nonvolatile memory. | 11-18-2010 |
| 20100301952 | Method For The Production Of High Amplitude RF Voltages With Control Of The Phase Angle Between Outputs - A method of producing high frequency high amplitude AC voltages with control of the phase angle between outputs from a plurality of generators having individual DC current controlled variable inductors which method comprises controlling the timing of the circuit to allow inputs at the same frequency to have their phase angle preserved. All the outputs are phase locked and synchronised to a common external timed signal and programmed to the same output frequency. | 12-02-2010 |
| 20100301953 | PHASE LOCK LOOP WITH A MULTIPHASE OSCILLATOR - A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase resolution. | 12-02-2010 |
| 20100308926 | METHOD AND APPARATUS FOR INTEGRATING A FLL LOOP FILTER IN POLAR TRANSMITTERS - The invention relates to a method and apparatus for integrating the various circuit components controlling a voltage-controlled oscillator (“VCO”) on an integrated circuit formed on a semiconductor device. In one embodiment, the integrated circuit includes a first digital-to-analog converter (“DAC”) for receiving and converting a digital representation of the frequency modulation for the VCO to an analog form. A filter removes any conversion error from the first analog signal. A second DAC receives and converts a digital representation of the center frequency for the VCO to a second analog signal. The first and second analog signals are combined at an adder and the resulting signal is used by a bridge circuit which controls the VCO. | 12-09-2010 |
| 20100327984 | PHASE LOCKED LOOP CIRCUITS AND GAIN CALIBRATION METHODS THEREOF - Phase locked loop circuits are provided, in which a phase locked loop module includes a voltage controlled oscillator to generate an oscillation signal with an output frequency according to a control voltage, and a gain calibration module triggers the phase locked loop module to induce a frequency variation characterized by a delta function in the output frequency and calculates a gain of the voltage controlled oscillator according to a phase error caused by the frequency variation in the output frequency. | 12-30-2010 |
| 20110057738 | Digitally Controlled Oscillators - The problems of large oscillator signal frequency change per bit, small runtime tuning bandwidth, and large wiring layout (and therefore large integrated circuit (IC) layout) in digitally-controlled oscillators are addressed by using an array of addressable tuning units, storing a data bit with respect to each tuning unit, and based on the data bit and an address bit, adjusting the output of each tuning unit. | 03-10-2011 |
| 20110115569 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLK | 05-19-2011 |
| 20110156824 | PHASE LOCKED LOOP CIRCUIT AND COMMUNICATION DEVICE - There is provided a phase locked loop circuit which includes a frequency divider, a phase comparator, a filter, and an output signal oscillator. The frequency divides a feedback signal by a specific ratio and the feedback signal is used for synchronizing a phase of a reference signal and a phase of an output signal. The phase comparator compares the phases of the reference signal, the output signal, and the feedback signal and adjusts a gain of an analog signal used for generating the output signal in accordance with increase or decrease of the ratio. The filter filters the analog signal to pass signals in a specific frequency band, the gain of the analog signal having been adjusted by the phase comparator and the output signal oscillator outputs the output signal on the basis of the analog signal. | 06-30-2011 |
| 20110193639 | Pure-Silicon Digital Oscillator - A pure-silicon digital oscillator includes a baseband generator for generating a standard baseband, and a clock pulse monitoring and modulating circuit for performing a frequency calibration to the standard baseband to produce a calibrated baseband, while storing an error value produced during the calibration into a data storage device, such that a frequency generator can generate an output frequency according to a numerical value of the calibrated baseband. After the output frequency is processed by a digital signal processing to form a digital output frequency to be inputted into a square wave generator, the square wave generator outputs a higher digital frequency according to the numerical value of the digital output frequency, and the higher digital frequency is provided for a digital power supply control device to drive currents and modulate voltages. | 08-11-2011 |
| 20110193640 | SEMICONDUCTOR DEVICE - This invention provides a semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A temperature sensor detects the ambient temperature of the high speed OCO and a voltage sensor detects the operating voltage of the high speed OCO. The power supply module includes a BGR and generates the reference voltage, reference current, and operating voltage of the high speed OCO, based on a primary reference voltage which is output by the BGR. A flash memory stores a table specifying trimming codes for the reference voltage and reference current, related to an ambient temperature and an operating voltage of the high speed OCO. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to the detected ambient temperature and operating voltage. | 08-11-2011 |
| 20110234326 | DIGITALLY CONTROLLED OSCILLATOR AND OSCILLATION METHOD FOR THE SAME - According to an embodiment, a digitally controlled oscillator outputs an oscillation signal having an oscillation frequency according to an oscillator tuning word. The digitally controlled oscillator includes a control unit and an oscillator. The control unit divides the oscillator tuning word of N bits into upper (N−A) (A≧1 and N>A) bits and lower A bits, converts the upper (N−A) bits into a first code to perform Binary control of (N−A) bits and converts the lower A bits into a second code to perform Unary control of (2̂(A+1)−2) bits, and outputs the conversion results, and the oscillator outputs oscillation signals having oscillation frequencies according to the first and second codes output from the control unit. | 09-29-2011 |
| 20110254635 | Oscillating circuit - An oscillating circuit including a digital sigma-delta modulator and a controlled oscillator is disclosed. The digital sigma-delta modulator receives a fractional bit signal to generate a control signal. The controlled oscillator includes a varactor dynamically coupled to receive the control signal. | 10-20-2011 |
| 20120299663 | SEMICONDUCTOR DEVICE HAVING ON-CHIP OSCILLATOR FOR PRODUCING CLOCK SIGNAL - A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage. | 11-29-2012 |
| 20130120073 | FREQUENCY DIVIDER AND PLL CIRCUIT - A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration. | 05-16-2013 |
| 20130187722 | OSCILLATOR AUTO-TRIMMING METHOD AND SEMICONDUCTOR DEVICE USING THE METHOD - An oscillator auto-trimming method is provided. The oscillator auto-trimming method includes receiving, by a subtractor, a first count result and second count result to output a difference between the first count result and the second count result as an offset frequency, receiving, by a divider, the offset frequency to output a divided signal corresponding to a result of dividing the offset frequency by a reference offset frequency output from a micro control unit, and receiving, by the micro control unit, the divided signal and determine whether to change an oscillator frequency. | 07-25-2013 |
| 20130222074 | OSCILLATION FREQUENCY REGULATING CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND OSCILLATION FREQUENCY REGULATION METHOD - There is provided an oscillation frequency regulating circuit including: a measuring section that performs measurement based on an oscillation frequency of an oscillation circuit; a comparator section that compares a measurement value measured by the measuring section against a set comparison value over a set comparison duration; a setting section that sets a comparison value selected from a plurality of comparison values of different magnitudes and that sets in the comparator section the comparison duration according to the magnitude of the selected comparison value; and a regulation section that, based on the comparison result of the comparator section, regulates the oscillation frequency of the oscillation circuit such that the oscillation frequency that is measured by the measuring section becomes a target oscillation frequency. | 08-29-2013 |
| 20130234800 | CALIBRATION DEVICE FOR OSCILLATOR AND METHOD THEREOF - A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator. | 09-12-2013 |
| 20130265114 | METHOD AND APPARATUS FOR MEASURING/COMPENSATING MISMATCHES IN DIGITALLY-CONTROLLED OSCILLATOR - A method for measuring mismatches in a digitally-controlled oscillator (DCO) includes: in a first settling phase, controlling a first capacitor array of the DCO to have a first capacitive value consistently, and controlling a second capacitor array of the DCO in a closed loop to make a frequency of the DCO locked to a target value; in a second settling phase, controlling the first capacitor array to consistently have a second capacitive value different from the first capacitive value, and controlling the second capacitor array in the closed loop to make the frequency of the DCO locked to the target value; and deriving an estimation from a difference value between a first characteristic value and a second characteristic value, wherein the first and second characteristic values are derived from the digital control word; and estimating the mismatches according to at least the estimation value. | 10-10-2013 |
| 20130293315 | High-Linearity Phase Frequency Detector - A phase frequency detector realizes a highly linear conversion from noise-shaped ΣΔ modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL. | 11-07-2013 |
| 20140085016 | LOCK DETECTER AND CLOCK GENERATOR HAVING THE SAME - A lock detector and a clock generator including the same are disclosed. A lock detector includes a counter unit which counts a non-matching section of a first signal and a second signal to provide a count value, the first signal and the second signal being comparison result signals obtained by comparing a phase of a reference signal with a phase of a comparison signal, and a lock detection unit which outputs a lock detection signal based on a result of comparing the count value with the reference value. Accordingly, a lock state of the phase-locked loop can be detected rapidly and exactly. | 03-27-2014 |
| 20140191815 | INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION - A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal. The frequency-control circuit also includes a frequency divider that is configured to apply a correction voltage to a feedback of the output frequency signal, the correction voltage being a function of a pulling signal having one or more unwanted frequency components. The frequency-control circuit also includes a loop filter configured to filter the output detection signal including the correction voltage and generate a control voltage signal. The frequency-control circuit also includes a voltage-controlled oscillator configured to receive the control voltage signal and generate an output frequency signal. | 07-10-2014 |
| 20150048894 | DELAY LINE RING OSCILLATION APPARATUS - The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal. The two gates logical circuit performs a logical operating on the clock enable signal, the specific mode signal and the delayed clock output signal for generating a mode selecting signal. The buffer generates a feedback signal according to the mode selecting signal and a control signal. The clock input buffer decides whether to transport the input clock signal to an output end of the clock input buffer or not according to the feedback signal. The delay lock loop circuit generates the delayed clock output signal. A frequency of the feedback signal is adjusted according to the control signal. | 02-19-2015 |
| 20150326233 | APPARATUS AND METHODS FOR TUNING A VOLTAGE CONTROLLED OSCILLATOR - Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval. | 11-12-2015 |
| 20150365093 | AFLL WITH INCREASED TIMING MARGIN - In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced. | 12-17-2015 |
