| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 331025000 | Signal or phase comparator | 63 |
| 20080246545 | DIGITAL PHASE AND FREQUENCY DETECTOR - Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles. | 10-09-2008 |
| 20080252385 | Highly Sensitive Force/Mass Detection Method and Device Using Phase Synchronization Circuit - There are provided a highly sensitive force/mass detection method and device using a phase-locked loop, in which a phase noise of the mechanical element can be reduced using the phase-locked loop, by synchronizing a vibration signal of a mechanical element to an oscillation signal from a local oscillator which has a low phase noise and a high purity property. In the highly sensitive force/mass detection device using the phase-locked loop, an oscillation circuit of a mechanical vibrator | 10-16-2008 |
| 20080266000 | Digital Frequency Multiplier Circuit - A digital frequency multiplier circuit is disclosed. The digital frequency multiplier circuit includes a digitally controlled oscillator (DCO), a phase detector and a control circuit. The DCO generates an internal feedback signal. The phase detector detects a phase difference between the internal feedback signal and an external reference clock signal. Coupled between the phase detector and the DCO, the control circuit adjusts the DCO to align the internal feedback signal with the external reference clock signal after a phase difference between the internal feedback signal and the external reference clock signal has been detected. The control circuit also locks a modulation frequency of the DCO and monitors the state of the digital frequency multiplier circuit in order to maintain the lock. | 10-30-2008 |
| 20080266001 | DUAL REFERENCE PHASE TRACKING PHASE-LOCKED LOOP - A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is configured to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector is further configured with a feedback loop to adjust any tracking error and provide a tracking output signal. The phase detector system maintains both a high tracking bandwidth and a bounded jitter amplification based as a result of the dual reference signal. The high tracking bandwidth and the bounded jitter amplification are independent of an applied loop gain. | 10-30-2008 |
| 20080266002 | FREQUENCY SYNTHESIZER - A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divided signal. The low pass filter is coupled to the harmonic locked phase/frequency detector. The voltage controlled oscillator is coupled to the low pass filter and provides an output signal. The frequency divider is coupled between the voltage controlled oscillator and the harmonic locked phase/frequency detector. Frequency of the divided signal is a harmonic frequency of the reference signal. | 10-30-2008 |
| 20090045880 | Digital Controlled Oscillator - A digital controlled oscillator including a programmable current source, a first variable capacitor and a second variable capacitor. A comparator compares the voltage across the variable capacitors with a reference voltage level and generates a DCO output clock signal. A switching means alternately switches the variable capacitors to either charge from a programmable current source or discharge in response to an output signal of the comparator. A clock divider divides the DCO output clock signal by a factor N substantially greater than 1. A frequency monitor receives the divided clock signal, determines the time difference of successive clock periods of the divided clock signal and generates a feedback signal to adapt the frequency of the DCO output clock signal. | 02-19-2009 |
| 20090096536 | Arrangement for Phase Synchronization According to the Master/Slave Principle - An apparatus for the phase synchronization of several devices, wherein one device is the master device and the other devices are slave devices, with a phase synchronization unit for every device, each of which has: a first controlled oscillator for producing a master reference signal, a first phase detector which, in order to control the first oscillator, compares the phase of a first comparison signal derived from the master reference signal with the phase of a second comparison signal derived from an auxiliary reference signal if the device is itself the master device and a second phase detector which, in order to control the first oscillator, compares the phase of a third comparison signal derived from the master reference signal with the phase of a reference signal coming from the phase synchronization unit of the master device if the device is not itself the master device but a slave device. | 04-16-2009 |
| 20090115535 | PWM CONTROL CIRCUIT AND MOTOR EQUIPPED WITH THE SAME - The PWM control circuit is provided. The PWM control circuit includes: a PWM control signal generator that generates a PWM period signal defining a period of a PWM signal and a PWM resolution signal specifying a resolution in one period of the PWM period signal; and a PWM unit that generates the PWM signal based on the PWM period signal and the PWM resolution signal, wherein the PWM control signal generator changes a frequency of the PWM resolution signal while keeping a frequency of the PWM period signal unchanged. | 05-07-2009 |
| 20090121795 | SYNTHESIZER - A synthesizer that has a phase detector | 05-14-2009 |
| 20090140818 | PHASE-LOCKED LOOP CIRCUIT AND DATA REPRODUCTION APPARATUS - This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit | 06-04-2009 |
| 20090201094 | PHASE COMPARISON CIRCUIT AND PLL SYNTHESIZER USING THE SAME - The phase comparison circuit according to an embodiment of the present invention comprises a fractional frequency divider | 08-13-2009 |
| 20090273402 | PHASE-LOCKED LOOP - The present invention concerns a phase-locked loop comprising:
| 11-05-2009 |
| 20090309665 | Low phase noise PLL synthesizer - A low phase noise PLL synthesizer is described in which an initial tuning mechanism uses a conventional divider loop to lock a VCO to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase noise mixer loop. The local oscillator signal for the mixer is derived from the same low phase noise source as the phase comparison frequency. | 12-17-2009 |
| 20090322432 | FREQUENCY SYNTHESIZER - A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divided signal. The low pass filter is coupled to the harmonic locked phase/frequency detector. The voltage controlled oscillator is coupled to the low pass filter and provides an output signal. The frequency divider is coupled between the voltage controlled oscillator and the harmonic locked phase/frequency detector. Frequency of the divided signal is a harmonic frequency of the reference signal. | 12-31-2009 |
| 20100073094 | Techniques For Generating Fractional Clock Signals - A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals. | 03-25-2010 |
| 20100085121 | Auto Trimming Oscillator - An auto trimming oscillator includes a Successive Approximation Register (SAR), a frequency detector and an n-bit comparator. The SAR is used to iteratively trim the oscillator output clock frequency based on a difference between a reference clock frequency and the oscillator output clock frequency. The oscillator is trimmed to deliver a clock frequency which is a closest match to the reference clock frequency. | 04-08-2010 |
| 20100097150 | PLL CIRCUIT - A technique for suppressing quantization noise generated due to digitizing an analog circuit in a PLL circuit is provided. The PLL circuit comprises: a digital phase frequency detector which detects (compares) phases and frequencies of a reference signal and a frequency-divided signal and converts the same to a digital value; a digital loop filter which eliminates high-frequency noise components from an output of the digital phase frequency comparator; a digital-analog converter which converts a digital value of an output of the digital loop filter to an analog value; an analog filter which eliminates a high-frequency noise component from an output of the digital-analog converter; a voltage controlled oscillator whose frequency is controlled based on an output of the analog filter; and a frequency divider which divides the frequency of the voltage controlled oscillator and outputs the frequency-divided signal. | 04-22-2010 |
| 20100097151 | PHASE NOISE CORRECTION DEVICE AND ITS METHOD - A phase noise correction device having a function for accurately detecting a phase noise component and capable of reducing a load on a reception device is provided. A phase noise correction device for correcting a phase noise generated in a local oscillator includes: a division section that divides a signal generated in the local oscillator; a reference signal generation section that generates a signal of the same frequency as that of the divided signal; a phase difference detection section that detects a phase difference between the divided signal and the generated reference signal; and a phase noise correction section that gives a phase rotation to a baseband signal in the direction that cancels the phase noise according to the detected phase difference as a phase noise component. | 04-22-2010 |
| 20100109786 | POWER SUPPLY VOLTAGE OUTPUT CIRCUIT - a power supply voltage output circuit includes: a power supply voltage generation unit generating a power supply voltage to be supplied into a ring oscillator; a reference clock oscillator oscillating a reference clock with respect to a clock oscillated by the ring oscillator; a phase difference detection unit detecting a phase difference between the clock from the ring oscillator and the reference clock from the reference clock oscillator; a filter unit smoothing an output of the phase difference detection unit; and a PWM signal generation unit generating a PWM signal based on an output of the filter unit such that the phase difference approaches zero. | 05-06-2010 |
| 20100207694 | PLL CIRCUIT AND OSCILLATOR DEVICE - A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal, wherein a drive capability of the oscillator part is controlled in accordance with the control signal. | 08-19-2010 |
| 20100237953 | DIGITAL PHASE DETECTOR, AND DIGITAL PHASE LOCKED LOOP INCLUDING THE SAME - A digital phase detector includes a quantization unit that quantizes a frequency of a reference signal to generate reference delay information and reference integer phase information, and quantizes a frequency of an oscillation signal to generate oscillation delay information and oscillation integer phase information. A first conversion unit converts the frequency of the reference signal into reference frequency information based upon the reference delay information and the reference integer phase information. A second conversion unit converts the frequency of the oscillation signal into oscillation frequency information based upon the oscillation delay information and the oscillation integer phase information. A calculation unit converts the reference frequency information and the oscillation frequency information into first and second phase information, respectively, and outputs a digital phase difference between the first phase information and the second phase information. | 09-23-2010 |
| 20100301950 | Clock regeneration apparatus and electric equipment - Disclosed herein is a clock regeneration apparatus, including: an oscillator including n (an integer of two or more) gating groups connected in cascade connection to each other forming an oscillation loop, the gating groups being controlled to gate an internal clock signal with first to nth gating signals different from one another, respectively, the oscillator outputting a clock signal at least from the nth one of the gating groups; an edge detection section adapted to detect an edge of a reception data signal; a phase decision section adapted to decide a phase of the clock signal for each edge of the reception data signal and output a result of the decision as a phase decision signal; and a gating signal generation section adapted to generate the first to nth gating signals and output the gating signals to first to nth ones of the gating groups, respectively. | 12-02-2010 |
| 20100321119 | PHASE LOCK LOOP CIRCUIT - A phase lock loop (PLL) circuit is provided. A voltage controlled oscillator (VCO) generates an output clock signal based on a control voltage. A controller provides a first digital control word, a second digital control word and a loop factor. A frequency modifier is coupled to the output clock signal, controlled by the controller to divide the output clock signal by the loop factor to generate a feedback frequency. A charge pump is controlled by the up signal and down signal to generate a charge pump current, comprising a first digital to analog converter (DAC) to generate a first current based on the first digital control word when the up signal is asserted. A second DAC generates a second current based on a second digital control word when the down signal is asserted. The controller defines a first relationship between the first digital control word and the loop factor, and the controller defines a second relationship between the second digital control word and the loop factor. | 12-23-2010 |
| 20100321120 | FRACTIONAL-N FREQUENCY SYNTHESIZER AND METHOD THEREOF - The present relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof. The fractional-N frequency synthesizer includes a reference oscillator that generates a reference frequency signal; a sigma-delta modulator that generates a desired decimal value based on the reference frequency signal; a divider that divides a voltage controlled oscillation frequency signal; first to M phase/frequency detectors that detect a difference in phase and frequency between the reference frequency signal and the divided voltage controlled oscillation frequency signal; first to M charge pumps that are connected to each of the phase/frequency detectors in series and charges or pumps charge amount according to output signals from each of the phase/frequency detectors; a loop filter that controls the amount of supplied current based on output signals from the charge pumps to filter low-pass frequency components; and a voltage controlled oscillator that is oscillated in response to the output signal from the loop filter and generates voltage controlled oscillation frequency signals. | 12-23-2010 |
| 20110001567 | SYSTEM AND METHOD FOR BUILT IN SELF TEST FOR TIMING MODULE HOLDOVER - Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator. The method further includes testing the selected mathematical model using a sampled version of the correction signal such that the selected mathematical model can be used without the need for a testing duration that is in addition to a period of time used for the training. | 01-06-2011 |
| 20110043289 | Apparatus and method for controlling the output phase of a VCO - A method and apparatus controlling the output phase of a VCO (Voltage Controlled Oscillator). The apparatus has a phase locked loop | 02-24-2011 |
| 20110050351 | OSCILLATOR WITH REDUCED PHASE NOISE CHARACTERISTICS - One well known problem associated with voltage controlled oscillators or VCOs is phase noise, and it is desirable to reduce phase noise in order to improve VCO performance. Here, a VCO is provided where gain elements are provided that reduce phase noise. These gain elements are generally comprised of oscillator tanks. | 03-03-2011 |
| 20110140790 | FREQUENCY SYNTHESIZERS - A frequency synthesizer includes a fractional N phase locked loop (PLL), a sigma delta modulator, a phase adjustor and an adjust signal generator. The fractional N PLL generates an output signal according to an adjusted reference signal. A frequency of the output signal is a multiple of a frequency of a reference signal. The fractional N PLL includes a crystal oscillator generating the reference signal and a divider frequency dividing the output signal according to the multiple to generate a feedback signal. The sigma delta modulator generates a control signal to adjust the multiple accordingly. The phase adjustor adjusts a phase of the reference signal according to an adjust signal to generate the adjusted reference signal. The adjust signal generator generates the adjust signal according to an accumulation result of the sigma delta modulator. | 06-16-2011 |
| 20110169578 | SIGNAL PROCESSING USING TIMING COMPARISON - A signal processing module with a timing comparator such as a time to digital converter is provided. The module may be part of a phase locked loop with a fractional frequency divider that acts to produce a divided down signal modulated with jitter in its timing. The timing comparator comprises an error cancellation stage ( | 07-14-2011 |
| 20110254634 | HIGH ACCURACY OSCILLATOR AND AN AUTO-TRIMMING METHOD THEREOF - A high-accuracy oscillator obtains initial control bits to generate an initial signal and generates adjacent control bits to generate an adjusted signal from the oscillator based on the adjacent control bits. Characteristics of the initial signal and the adjacent signal are compared to a preset value to determine which of the initial signal and the adjusted signal is closer to a target signal. The closer of the initial signal and the adjusted signal to the target signal is output from the oscillator. | 10-20-2011 |
| 20120025918 | APPARATUS AND METHOD FOR CALIBRATING TIMING MISMATCH OF EDGE ROTATOR OPERATING ON MULTIPLE PHASES OF OSCILLATOR - An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples. | 02-02-2012 |
| 20120038426 | PLL FREQUENCY SYNTHESIZER, WIRELESS COMMUNICATION APPARATUS AND PLL FREQUENCY SYNTHESIZER CONTROLLING METHOD - There is provided a PLL frequency synthesizer including a phase comparing unit, a current pulse signal generating unit, an converting unit which converts the current pulse signal from the current pulse signal generating unit into a voltage signal, an outputting unit which outputs a signal of an oscillation frequency matching the voltage signal from the converting unit, a divider which divides an output from the outputting unit by a division ratio matching a division ratio control signal to output as the division signal, a division ratio control signal generating unit which generates the division ratio control signal based on division ratio data for fractional-N, and the phase error compensation signal generating unit which generates at least two items of phase error compensation data from the division ratio data, and generates the phase error compensation signal utilizing the at least two generated items of phase error compensation data at different timings. | 02-16-2012 |
| 20120081185 | TIME-TO-DIGITAL CONVERTER (TDC) WITH IMPROVED RESOLUTION - A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths. | 04-05-2012 |
| 20120154057 | OSCILLATION CIRCUIT OF SEMICONDUCTOR APPARATUS - An oscillation circuit of a semiconductor apparatus includes a first level regulation unit configured to regulate an output voltage at an output node according to a difference between a reference voltage and the output voltage, and a second level regulation unit coupled between a power supply voltage terminal and a source voltage terminal. | 06-21-2012 |
| 20120212296 | SIGNAL GENERATING CIRCUIT AND SIGNAL GENERATING METHOD - A signal generating circuit includes: an operating circuit arranged to generate a first control signal according to a reference clock signal and a feedback oscillating signal; a controllable oscillator arranged to generate an output oscillating signal according to the first control signal and a second control signal; a feedback circuit arranged to generate the feedback oscillating signal according to the output oscillating signal and a third control signal; a control circuit arranged to generate the second control signal and the third control signal according to an input signal; and a calibrating circuit arranged to calibrate the control circuit to adjust the second control signal by detecting a phase difference between the reference clock signal and the feedback oscillating signal. | 08-23-2012 |
| 20120218049 | PLL - A PLL includes: a charge-pump equalizer which has a plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds and outputs the charge currents generated by the charge pumps; a replica circuit, having ideal characteristics of a loop filter and a voltage controlled oscillator, which input a digital value having phase difference of the phase-difference signals, and generates a replica output according to the ideal characteristics; and a coefficient generating circuit which smoothes correlation values of the difference signals and the phase-difference signals to generate charge pump coefficients, and negatively feeds back the same to the plurality of charge pumps. The charge pumps generate the charge currents each having current values corresponding to the charge pump coefficients. | 08-30-2012 |
| 20120256692 | OSCILLATOR - An oscillator includes: a substrate; a reference oscillation circuit including a first MEMS oscillator disposed above the substrate, the reference oscillation circuit outputting a first oscillation signal; at least one voltage-controlled oscillation circuit including a second MEMS oscillator disposed above the substrate, the oscillation frequency of the at least one voltage-controlled oscillation circuit being controlled based on a control signal, the at least one voltage-controlled oscillation circuit outputting a second oscillation signal; a frequency division circuit dividing the frequency of the second oscillation signal and outputting a frequency division signal; and a phase-comparison circuit outputting the control signal based on a phase difference between the frequency division signal and the first oscillation signal, wherein the first MEMS oscillator and the second MEMS oscillator each have a first electrode and a second electrode, the second electrode has a movable part disposed so as to face the first electrode. | 10-11-2012 |
| 20130069729 | Phase Locked Loop Circuitry Having Switched Resistor Loop Filter Circuitry, and Methods of Operating Same - Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry. | 03-21-2013 |
| 20130088300 | ACCUMULATOR-TYPE FRACTIONAL N-PLL SYNTHESIZER AND CONTROL METHOD THEREOF - There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer ( | 04-11-2013 |
| 20130162356 | METHODS AND APPARATUS FOR OSCILLATOR FREQUENCY CALIBRATION - In one general aspect, an apparatus can include a phase frequency detector configured to produce a plurality of indicators of relative differences between a frequency of a target oscillator signal and a frequency of a reference oscillator signal. The apparatus can also include a pulse generator configured to produce a plurality of pulses based on the plurality of indicators. The plurality of pulses can include a first portion configured to trigger an increase in the frequency of the target oscillator signal and the plurality of pulses including a second portion configured to trigger a decrease in the frequency of the target oscillator signal. | 06-27-2013 |
| 20130169369 | METHODS AND APPARATUS FOR SELF-TRIM CALIBRATION OF AN OSCILLATOR - In one general aspect, an apparatus can include a reference oscillator counter circuit configured to produce a reference oscillator count value based on a reference oscillator signal, and a target oscillator counter circuit configured to produce a target oscillator count value based on a target oscillator signal where the target oscillator signal has a frequency targeted for calibration against a frequency of the reference oscillator signal. The apparatus can include a difference circuit configured to calculate a difference between the reference oscillator counter value and the target oscillator counter value, and a summation circuit configured to define a trim code based on only a portion of bit values from the difference. | 07-04-2013 |
| 20130222067 | PHASE-LOCKED LOOP - A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal. | 08-29-2013 |
| 20140055203 | Circuit for Measuring the Resonant Frequency of Nanoresonators - The present disclosure relates to nanoresonator oscillators or NEMS (nanoelectromechanical system) oscillators. A circuit for measuring the oscillation frequency of a resonator is provided, comprising a first phase-locked feedback loop locking the frequency of a controlled oscillator at the resonant frequency of the resonator, this first loop comprising a first phase comparator. Furthermore, a second feedback loop is provided which searches for and stores the loop phase shift introduced by the resonator and its amplification circuit when they are locked at resonance by the first loop. The first and the second loops operate during a calibration phase. A third self-oscillation loop is set up during an operation phase. It directly links the output of the controllable phase shifter to the input of the resonator. The phase shifter receives the phase-shift control stored by the second loop. | 02-27-2014 |
| 20140191812 | INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION - A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal. The frequency-control circuit also includes a current source applied to the output detection signal to form a correction voltage that is a function of a pulling signal having one or more unwanted frequency components. The frequency-control circuit also includes a loop filter configured to filter the output detection signal including the correction voltage and generate a control voltage signal. The frequency-control circuit also includes a voltage-controlled oscillator configured to receive the control voltage signal and generate an output frequency signal. | 07-10-2014 |
| 20140232474 | Enhanced Numerical Controlled Oscillator - A numerical controlled oscillator generating an output signal with a digital clock signal having a variable frequency is disclosed. The numerical oscillator is controlled by a programmable numerical value being subject to a transfer function and comprises a comparator configured to compare an output of the transfer function with a duty cycle register to generate the output signal. | 08-21-2014 |
| 20140320216 | OSCILLATOR CIRCUIT - An oscillator circuit includes: a switched-capacitor filter filtering a voltage at a common node between a current generating unit and a frequency-controlled resistor so as to generate a filtered voltage; an amplifier generating a control voltage based on the filtered voltage and a voltage at a common node between the current generating unit and a reference resistor; a voltage-controlled oscillator generating an oscillation signal based on the control voltage; and a control signal generating unit generating, based on the oscillation signal, a control input having a frequency proportional to that of the oscillation signal. The frequency-controlled resistor has a resistance variable according to the control input. | 10-30-2014 |
| 20150008985 | OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT - An oscillator comprising: an oscillator circuit element having a substrate terminal group and a capacitance section provided on an element substrate, the substrate terminal group comprising at least three substrate terminals including a first substrate terminal and a second substrate terminal, the capacitance section being connected between the first and second substrate terminals; a mount part including an external terminal group comprised of at least one external terminal and mounting thereon the oscillator circuit element; a plurality of inductance lines which are formed among the at least three substrate terminals by conductor wirings which connect between the at least three substrate terminals of the substrate terminal group and the at least one external terminal; and a switch circuit provided on the element substrate to control a connection state of the plurality of inductance lines. | 01-08-2015 |
| 20150028957 | PLL DEVICE - A PLL device includes a variable frequency oscillator and a frequency divider section. The variable frequency oscillator varies an oscillation frequency in response to a control signal including information on a phase difference between a reference signal and a frequency division signal and oscillates an output signal obtained by multiplying a frequency of the reference signal. The frequency divider section frequency-divides the output signal to generate the frequency division signal. An injection locked frequency divider is arranged in the frequency divider section, the control signal is input to the injection locked frequency divider, and the operation frequency of the injection locked frequency divider is controlled by the control signal. | 01-29-2015 |
| 20150061779 | DIGITALLY CONTROLLED OSCILLATOR AND ELECTRONIC DEVICE INCLUDING THE SAME - Provided are a digitally controlled oscillator and an electronic device including the digitally controlled oscillator. The digitally controlled oscillator includes a digital control unit and a power control oscillation unit. The digital control unit compensates for a difference between a feedback signal of an output power and a reference power set based on an input digital control signal and outputting an output power. The power control oscillation unit receives a signal related to the output power, and generates an output clock having an oscillation frequency in response to the signal related to the output power. | 03-05-2015 |
| 20150061780 | OSCILLATOR CIRCUIT, A SEMICONDUCTOR DEVICE AND AN APPARATUS - An oscillator circuit for providing an output clock signal is described. The oscillator circuit comprising a voltage reference, a first current source, first capacitor, first capacitor switch, second current source, second capacitor, second capacitor switch, first comparator, second comparator and flip-flop. The first comparator comprises a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in a first half-phase of the output clock signal to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and in the zeroing phase in the second half-phase. The second comparator comprises a second chopper-stabilized comparator switchable between a respective compare phase and a respective zeroing phase in dependence on the output clock signal and arranged to operate in its compare phase in the second half-phase to obtain a second comparator output from comparing the second capacitor voltage to the reference voltage and in its zeroing phase in the first half-phase. | 03-05-2015 |
| 20150061781 | ELECTRONIC CIRCUIT AND CONTROL METHOD - An electronic circuit, includes: a first oscillator configured to generate a reference signal; a plurality of phase synchronization circuits, each including a second oscillator configured to generate an output signal having a frequency corresponding to an input, and a phase comparator configured to input, to the second oscillator, a signal corresponding to a phase difference between the output signal generated by the second oscillator and the reference signal generated by the first oscillator; and a controller configured to control relative phases of the reference signals input to the phase synchronization circuits from the first oscillator, based on the signals input to the corresponding second oscillators from the phase comparators in the phase synchronization circuits. | 03-05-2015 |
| 20150137895 | QUADRATURE-BASED INJECTION LOCKING OF RING OSCILLATORS - Technologies are generally described for quadrature-based injection-locking of ring oscillators. In some examples, an external signal may be injected into a ring oscillator. Phase signals may be measured from within the ring oscillator and used to determine a mean quadrature error (MQE) that characterizes the difference in frequency between the external signal and the ring oscillator's natural frequency. A control signal may then be generated from the MQE and used to adjust the ring oscillator natural frequency to reduce the difference between the ring oscillator natural frequency and the external signal. | 05-21-2015 |
| 20150326231 | TUNABLE FREQUENCY-TO-VOLTAGE CONTROLLED OSCILLATION - A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a frequency-to-voltage (F2V) converter. The F2V converter, for example, includes a frequency target control input for selecting an operational frequency and in response generates a frequency control signal using a DAC (digital-to-analog converter). The example F2V converter is arranged using a split capacitor DAC to provide a linear voltage response over a range of trim codes. The clock generator is arranged to generate the converter clock signal in response to the frequency control signal. | 11-12-2015 |
| 20150333760 | INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO DETERMINE SETTINGS FOR AN INJECTION-LOCKED OSCILLATOR - Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes. | 11-19-2015 |
| 20150341040 | Clock Generator and Switch-capacitor Circuit Comprising the Same - The invention provides a clock generator and a switch-capacitor circuit comprising the same, and pertains to the technical field of integrated circuit (IC) design. The clock generator comprises a non-overlapping clock signal generating module and a ring oscillator, a frequency detecting module, a comparator module and a programmable biasing signal generating module for forming a feedback circuit, wherein a biasing signal generated by the programmable biasing signal generating module is fed back and input to the ring oscillator so as to adjust the frequency of the third clock signal output by the ring oscillator, until the frequency of the third clock signal is compared as being substantially equal to the frequency of a standard clock signal in the comparator module. Moreover, the biasing signal can be fed back and input to the non-overlapping clock signal generating module so as to reduce the offset of the two phase clock time interval τ. The time interval τ between two phase clocks of the multiple phase non-overlapping clock signal output by the clock generator is stable and has a high accuracy, and the switch-capacitor circuit using the clock generator exhibits an excellent performance. | 11-26-2015 |
| 20160013802 | FREQUENCY CORRECTION SYSTEM AND CORRECTING METHOD THEREOF | 01-14-2016 |
| 20160164460 | OSCILLATOR REGULATION CIRCUITRY AND METHOD - Oscillator regulation circuitry is provided for regulating a frequency of an output signal generated by an oscillator. Oscillator regulation circuitry has frequency sensing circuitry for sensing the frequency of the output signal and generating a first signal depending on the frequency, and control circuitry which generates the oscillator control signal based on the comparison between the first signal and a non-oscillating reference signal. The frequency sensing circuitry includes at least one switched capacitor. This approach provides improved noise reduction, less sensitivity to process, temperature and voltage variations, and a more linear scaling of the frequency with the reference signal, compared to previous techniques. | 06-09-2016 |
| 20160164531 | METHODS AND DEVICES FOR ERROR CORRECTION OF A SIGNAL USING DELTA SIGMA MODULATION - A method for correcting long-term phase drift of a crystal oscillator in a numerically-controlled oscillator is described. The method includes determining the phase error in an oscillator signal in comparison with an external time base; delta-sigma modulating the phase error to generate a delta-sigma error bitstream; conditionally adding or subtracting an error correction step size from a phase increment value in each clock cycle based on the delta-sigma error bitstream, to create a modulated phase increment value; and adding the modulated phase increment value to a phase accumulator to generate an error-corrected output digital signal. The delta-sigma-based error correction method avoids the use of multipliers. The same delta-sigma error signal can be used in multiple numerically-controlled oscillators configured to different output frequency if driven by the same reference oscillator. | 06-09-2016 |
| 20160191067 | OSCILLATOR WITH FREQUENCY CONTROL LOOP - Circuitry for providing an oscillating output signal. The circuitry comprises a transconductance circuit having a first input, a second input, and an output. The circuitry further comprises an oscillator circuit coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit. Also included are circuitry for providing a first voltage to the first input of the transconductance circuit and a frequency controlled circuit for providing a second voltage to the second input the transconductance circuit. The second voltage is response to a frequency of operation of the frequency controlled circuit, and the frequency of operation of the frequency controlled circuit is responsive to feedback from the output of the oscillator circuit. | 06-30-2016 |
| 20160197581 | DIGITALLY CONTROLLED OSCILLATOR DEVICE AND HIGH FREQUENCY SIGNAL PROCESSING DEVICE | 07-07-2016 |
| 331027000 | Plural active element (e.g., triodes) | 2 |
| 20110012684 | LOCAL OSCILLATOR - Equal numbers of variable capacitance elements, capacitance values of which are separately controlled according to a logic value of a corresponding bit of a delay control signal that is in a one-to-one relation with an oscillation frequency, are connected in parallel among differential outputs of all delay circuits excluding a differential non-inverting delay circuit at the end, which extracts a frequency signal to the outside. Bits of the delay control signal are connected in a one-to-one relation to the equal numbers of variable capacitance elements arranged on output sides of all the delay circuits, in a relation in which delay control signals continuous in terms of frequency are not connected to the equal number of variable capacitance elements arranged on an output side of one of the delay circuits. | 01-20-2011 |
| 20120242415 | PLL CIRCUIT AND CONTROL METHOD THEREOF - A PLL circuit has a voltage control oscillator, a rough-adjusting loop part and a fine-adjusting loop part. The rough-adjusting loop part configured to perform a rough adjustment to the frequency of the oscillating signal based on a frequency-setting signal. The fine-adjusting loop part performs a fine adjustment to the frequency of the oscillating signal after the rough adjustment by the rough-adjusting loop part. The fine-adjusting loop part includes a phase comparator configured to detect a phase difference between the frequency-divided signal obtained by frequency-dividing the oscillating signal at the frequency divider and the reference signal while a switched state of each of the first switching parts at a moment of the completion of the rough adjustment at the rough-adjusting loop part remains unchanged. | 09-27-2012 |
| 331029000 | Electromechanical | 1 |
| 20140104006 | PASSIVE AND ACTIVE SUPPRESSION OF VIBRATION INDUCED PHASE NOISE IN OSCILLATORS - An oscillator system having: an UHF oscillator, such as a SAW oscillator, for producing a signal having a controllable frequency; a passive vibration, suppressor mechanically coupled to the UHF oscillator for suppressing vibrations above a predetermined bandwidth BW1 on the UHF oscillator; and an active vibration suppressor. The active vibration suppressor includes an accelerometer for sensing vibrations within a predetermined bandwidth BW2 on the UHF oscillator; and an HF or VHF oscillator, such as a crystal oscillator, producing a signal having a frequency controlled by the accelerometer. A control loop having a bandwidth changeable with sensed vibration level is fed the oscillator and the UHF oscillator for controlling the frequency of the signal produced by the SAW oscillator is accordance with a difference between the signal produced the HF or VHF oscillator and the signal produced by the UHF oscillator, the control loop having a bandwidth BW3; where BW1| 04-17-2014 | |
