| Entries |
| Document | Title | Date |
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| 20080258823 | SELF-COMPENSATING VOLTAGE-CONTROLLED OSCILLATOR - In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverter stages coupled to form a loop, each differential inverter stage having including a switched capacitor circuit configured to control a signal delay through the differential inverter stage responsive to a control circuit, whereby an output frequency for the VCO is inherently compensated against changes in semiconductor process variations and thermal variations. | 10-23-2008 |
| 20080278246 | MEMORY CONTROLLER - A memory controller includes a ring oscillator to generate and to output at least one oscillation clock, an oscillation counter to count the output oscillation clocks, a sampler to receive the reference clock so as to sample a number of the counted oscillation clocks during a period of the reference clock, and a phase value output unit to output the sampled number of oscillation clocks as a phase value of the reference clock. Thereby, the memory controller can detect the phase value using only two periods of the reference clock, and reduce the initial operation time of a system. | 11-13-2008 |
| 20080290954 | Fractional-N phase locked loop - An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal. The fractional frequency divider incrementally selects among all the outputs of the multi-phased VCO according to either a forward phase shifting operation or a backward phase shifting operation to generate a true fractional division factor. | 11-27-2008 |
| 20080315961 | Quality of Phase Lock and Loss of Lock Detector - A system, apparatus and method for providing phase lock conditions detection such as a quality of phase lock and loss of lock detection. A phase locked loop (PLL) circuit may comprise an oscillator for providing an output frequency, as well as a detector for detecting the output frequency of the oscillator, comparing the output frequency with a reference signal and outputting a first and second signals as a function of the comparison. The PLL circuit may further include an amplifying circuit for receiving the first and second signals, monitoring a deviation of the first and second signals from a predetermined threshold, and generating a third signal as a function of the deviation. The PLL circuit may further comprise a comparison circuit for receiving the third signal, comparing the third signal to a window threshold, and generating a fourth signal as a function of the comparison. The window threshold may be a function of apriori knowledge of at least one loop variable, wherein the window threshold is set based on a predetermined loop variable. An alarm circuit may receive the fourth signal and provide an alarm. | 12-25-2008 |
| 20090002080 | FREQUENCY DIVIDER AND PHASE LOCKED LOOP USING THE SAME - The invention relates to a frequency divider operated digitally and capable of satisfying the Zigbee standard, and a phase locked loop system using the same. The frequency divider includes a plurality of latches in a ring structure with an output of a latter end latch is connected to an input of a former end latch. The frequency divider also includes an input end connected in common to clock ends of the latches, receiving a signal to be divided, and a plurality of output ends connected to the output ends of the latches, outputting divided signals of different phases. The phase locked loop system of the invention has a dividing means dividing an output frequency by 1/P and 1/P+0.5 using the frequency divider, thereby generating the Zigbee channel frequencies at a 5 MHz spacing. | 01-01-2009 |
| 20090072913 | Method and system of jitter compensation - The present invention relates to sigma-delta modulators, ΣΔ modulators, and phase locked loops. Especially, it relates to jitter compensation in ΣΔ-controlled fractional-N frequency synthesizers. Jitter compensation is introduced by means of a variable delay line. | 03-19-2009 |
| 20090085673 | METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH DDFS FEEDBACK PATH - Aspects of a method and system for signal generation via a PLL with a DDFS feedback path are provided. In this regard, a phase difference between a reference signal and a feedback signal may be utilized to control a VCO, wherein the feedback signal is generated by a DDFS. Voltage, current and/or power levels of the generated feedback signal may be limited to a determined range of values. Moreover, the feedback signal may be based on an output of the VCO and a digital control word input to the DDFS. The digital control word may be programmatically controlled by, for example, a processor. Additionally, the control word may be determined based on a desired frequency of the generated feedback signal and a desired output frequency of the VCO. Accordingly, the DDFS may be clocked by the output of the VCO, or by a divided down version of the VCO output. | 04-02-2009 |
| 20090085674 | METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH DIGITAL PHASE DETECTION - Aspects of a method and system for signal generation via a PLL with a digital feedback path are provided. In this regard, an output of a VCO may clock an accumulator to generate a digital feedback signal for phase comparison with a digital reference signal, wherein a value of a digital control word is added to a value stored in said accumulator on each cycle of said VCO output. The phase comparison may be performed by multiplying the feedback signal and the reference signal. Accordingly, a control voltage of the VCO may be determined based on a product of the multiplication. The value of the control word may be programmatically controlled and may be determined based on a frequency of the VCO output and/or of the reference signal. In this regard, the value of the control word may be retrieved from a look-up table. | 04-02-2009 |
| 20090085675 | METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH UNDERSAMPLED FEEDBACK - Aspects of a method and system for signal generation via a PLL with undersampled feedback are provided. In this regard, the output of a VCO may clock a DDFS to generate a sampling frequency, and the output of the VCO may be undersampled at the sampling frequency to generate a feedback signal for controlling the VCO. Additionally, a control word for controlling the DDFS may be generated, and may be based on a phase difference between the feedback signal and a reference signal. The sampling frequency may be determined such that an aliasing product of the undersampling occurs at a frequency of the reference signal. Also, the feedback signal may be filtered to select a desired aliasing product from a plurality of aliasing products. The output of the VCO may be frequency divided before clocking the DDFS, and a divisor of the division may be programmatically controlled. | 04-02-2009 |
| 20090085676 | Oscillator - An oscillator of the present invention includes a constant current circuit in which a constant current generated in the constant current circuit varies positively with an on threshold voltage of a transistor included in the constant circuit; and an oscillating circuit in which the oscillating frequency of a clock signal generated in the oscillating circuit varies positively with the constant current supplied from the constant current circuit, and the oscillating frequency of the clock signal generated in the oscillating circuit varies negatively with an on threshold voltage of a transistor included in the oscillating circuit. | 04-02-2009 |
| 20090184771 | Systems and Methods for Reducing Flicker Noise in an Oscillator - Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide LC tank circuits having an inductance and a capacitance. In addition, the circuits include a flicker noise reducing switch that is operable to selectively incorporate the capacitance such that an output of the circuit operates at a frequency based on a combination of the inductance and the capacitance. | 07-23-2009 |
| 20090243731 | Apparatus With Clock Generation Function, Method For Setting Reference Frequency, And Method For Adjusting Reference Frequency - An apparatus includes an oscillator, a memory for storing data of a first frequency and of a first voltage, a first controller for causing the oscillator to generate a clock having a required frequency by applying a voltage on the basis of the data of the first frequency and of the first voltage, a second controller for causing the oscillator to generate a clock having a second frequency by applying a second voltage at predetermined timing, an output section for outputting data of the clock of the second frequency to a frequency counter, a writing section for updating the data of the first voltage to data of the second voltage and the data of the first frequency to data of the second frequency when a difference between the second frequency and a third frequency is within a predetermine range. | 10-01-2009 |
| 20090243732 | SDOC with FPHA & FPXC: System Design On Chip with Field Programmable Hybrid Array of FPAA, FPGA, FPLA, FPMA, FPRA, FPTA and Frequency Programmable Xtaless ClockChip with Trimless/Trimfree Self-Adaptive Bandgap Reference Xtaless ClockChip - The Field Programmable Hybrid Array (FPHA) and Frequency Programmable Xtaless Clock (FPXC) are for high-speed and high frequency System-Design-On-Chip(SDOC). The FPXC adopts the Self-Adaptive Process & Temperature Compensation Bandgap Reference Generator, the Gain-Boost Amplitude Control LC VCO and inverter type flash memory. The FPHA adopts the two-way flash switch and inverter type flash memory Look-Up-Table(LUT). The FPXC adopts the inverter type flash memory as the Non-Volatile Memory(NVM) to keep the setup data in the field frequency programming. The flash technology of FPHA and FPXC are compatible that the FPHA has the FPXC capability. The PLLess CDR(PLL free Clock Data Recovery) is based on the FPXC capability for the SerDes high frequency application. The PLLess CDR and pipeline ADC are for the analog front high frequency application. With the SDOC on FPHA, the Automobile Infotainment Center(MIC) is reduced to be Mobile Infotainment Center(MIC). The ( | 10-01-2009 |
| 20090267697 | Frequency synthesizer using a phase-locked loop and single side band mixer - A frequency synthesizer is built using a phase locked loop incorporating a single side band mixer in the input. The single side band mixer is preferably realized with digital logic and FETs, and the resulting frequency synthesizer simultaneously improves control over the frequency resolution, noise floor and operating frequency range. | 10-29-2009 |
| 20090295490 | DDS CIRCUIT AND ELECTRONIC DEVICE HAVING THE SAME - A circuit includes a DDS unit deriving a sine wave from a tuning word using a frequency of a reference clock, a first frequency divider dividing the frequency of the reference clock, a second frequency divider dividing a frequency of the sine wave output by the DDS unit, and a mixer mixing the sine wave of a divided frequency with the reference clock of a divided frequency to thus produce the sine wave of a mixed frequency. | 12-03-2009 |
| 20100045388 | Accuracy on-chip clock generator for multi-clock driven single chip solution - A mixed-signal chip is described. The mixed-signal chip comprises a first portion of analog circuit and second portion of digital circuit, an on-chip precision oscillator residing on the first analog portion, the precision oscillator has a precision frequency; a first on-chip non-precision tunable oscillator from a first clock domain residing on the first analog portion, the first non-precision tunable oscillator has a first adjustable frequency; a noise detector for detecting a first noise in the first clock domain; a frequency adjusting register for storing a first desired frequency value of the first on-chip non-precision tunable oscillator, wherein the first desired frequency value is determined based on the first detected noise; a control circuit for adjusting the adjustable frequency of the first non-precision tunable oscillator to the first desired frequency value by using the precision frequency of the on-chip precision oscillator as a reference. | 02-25-2010 |
| 20100052797 | Direct digital synthesizer for reference frequency generation - A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency f | 03-04-2010 |
| 20100097149 | Methods, Algorithms, Circuits, and Systems for Determining a Reference Clock Frequency and/or Locking a Loop Oscillator - Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies. | 04-22-2010 |
| 20100117742 | Circuit with multiphase oscillator - In an embodiment, a circuit is provided comprising a multi-phase oscillator configured to output a plurality of output signals having the same frequency and different phase offsets. A feedback value is generated based on at least two of said output signals. A reference value is generated based on a reference clock and a predetermined value. The reference value and the feedback value are combined. | 05-13-2010 |
| 20100117743 | Circuit with noise shaper - In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping. | 05-13-2010 |
| 20100214028 | OSCILLATOR CONTROL APPARATUS - An oscillator control apparatus has a digitally-controlled oscillator which outputs an oscillation signal having an oscillation frequency in response to an oscillator adjusting signal, a counter which counts the oscillation signal and outputs a count in response to a reference signal in synchronism with the oscillation signal, a time-to-digital converter which calculates a phase difference between the oscillation signal and the reference signal, an adder which adds the count and the phase difference and outputs the added value as first phase information, a corrector which corrects the first phase information in response to a phase control signal for setting an oscillation frequency of the digitally-controlled oscillator when a time difference between a rising-up timing of the oscillation signal and a rising-up timing of the reference signal is less than a predetermined time, and outputs second phase information, and a filter for smoothing a difference between the phase control signal and the second phase information, to output the oscillator adjusting signal. | 08-26-2010 |
| 20100214029 | Integrated circuit frequency generator - An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles. | 08-26-2010 |
| 20100231306 | POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY - A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides. | 09-16-2010 |
| 20100253437 | METHOD AND SYSTEM FOR USING A MEMS STRUCTURE AS A TIMING SOURCE - A system and method is disclosed that provides a technique for generating an accurate time base for MEMS sensors and actuators which has a vibrating MEMS structure. The accurate clock is generated from the MEMS oscillations and converted to the usable range by means of a frequency translation circuit. | 10-07-2010 |
| 20100295621 | FREQUENCY GENERATOR AND METHOD OF FREQUENCY GENERATION WITH MULTIPLE SAMPLING PHASE DETECTORS - A device includes: a plurality of sampling phase detectors, each receiving a sampling signal and a VCO output signal and in response thereto outputting a beat signal representing a frequency and phase difference between the VCO output signal and the sampling signal; a frequency/phase detector receiving a reference signal and a combined beat signal produced by combining the beat signals, and in response thereto producing an error signal representing a phase difference between the reference signal and the combined beat signal; a loop integrator receiving the error signal and in response thereto producing the VCO control signal; a power detector detecting a power level of the combined beat signal; and at least one offset voltage generator adjusting a value of a bias voltage in response to the detected power level of the combined beat signal, and applying the adjusted bias voltage to one of the sampling phase detectors. | 11-25-2010 |
| 20100315172 | Spread spectrum clock generator and semiconductor device - A spread spectrum clock generator includes a voltage-controlled oscillator generating an operation clock, a feedback control unit, a modulated pulse generation unit generating a pulse signal obtained by performing a delta-sigma modulation on a component fluctuating a frequency of the operation clock, a level set unit setting an amplitude of the pulse signal, an adder adding a voltage generated by the feedback control unit and the pulse signal whose amplitude is set by the level set unit, and a low pass filter filtering a signal outputted from the adder and generating a control voltage applied to the voltage-controlled oscillator. The feedback control unit compares a phase of the operation clock with a phase of a reference clock, and based on results of the comparison, generates a voltage used as a reference to oscillate the voltage-controlled oscillator. | 12-16-2010 |
| 20100321118 | SYSTEM AND METHOD FOR SELECTING OPTIMUM LOCAL OSCILLATOR DISCIPLINE SOURCE - A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input configured to receive a respective second signal having timing information, frequency information, phase information or combinations thereof. The prioritizer is configured to determine an accuracy of at least one second signal of the at least two second signals in relation to a second signal assigned to be a most accurate of the at least two second signals. The prioritizer is also configured to order the at least two second signals from most accurate to least accurate. The LO is disciplined to correct an offset error of the LO relative to a most accurate second signal that is available to the device, based on the order of the at least two second signals. | 12-23-2010 |
| 20110084768 | Dual reference oscillator phase-lock loop - A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error. | 04-14-2011 |
| 20110140789 | ON-THE-FLY FREQUENCY SWITCHING WHILE MAINTAINING PHASE AND FREQUENCY LOCK - A difference between a reference clock and feedback clock is detected to generate a difference signal that is filtered to generate a voltage controlled oscillator control signal and produce an oscillation signal having an oscillation frequency. A first frequency dividing circuit divides the oscillation signal by a selected one of a number of first frequency divisors to generate an output signal at a selected frequency. A second frequency dividing circuit divides the output signal by a selected one of a number of second frequency divisors to generate the feedback clock. The frequency divisors are selected by a frequency selection signal. The first frequency dividing circuit samples the frequency selection signal at the rate of the oscillation signal divided by a least common multiple of the plurality of first frequency divisors. The second frequency dividing circuit samples the sampled frequency selection signal at the rate of the feedback clock. | 06-16-2011 |
| 20110148530 | Oscillator with capacitance array - An oscillator is provided which comprises an array of capacitances. At least some capacitances in the array have different capacitance values. | 06-23-2011 |
| 20110148531 | OSCILLATORS HAVING ARBITRARY FREQUENCIES AND RELATED SYSTEMS AND METHODS - Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal. | 06-23-2011 |
| 20110156820 | METHOD OF ESTABLISHING AN OSCILLATOR CLOCK SIGNAL - A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate. | 06-30-2011 |
| 20110163817 | RESONATOR AND OSCILLATOR USING SAME - There is provided with a resonator which can correct the resonance frequency of a vibrator in a wide range and with a high accuracy and also provided with an oscillator using the resonator. In the resonator configured by the vibrator | 07-07-2011 |
| 20110169577 | SYSTEM AND METHOD FOR BUILT IN SELF TEST FOR TIMING MODULE HOLDOVER - Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator. The method further includes testing the selected mathematical model using a sampled version of the correction signal such that the selected mathematical model can be used without the need for a testing duration that is in addition to a period of time used for the training. | 07-14-2011 |
| 20110181366 | OSCILLATORS HAVING ARBITRARY FREQUENCIES AND RELATED SYSTEMS AND METHODS - Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal. | 07-28-2011 |
| 20110241784 | Self-Calibrating Relaxation Oscillator Based Clock Source - A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners. | 10-06-2011 |
| 20110241785 | Reference signal oscillator - A rubidium oscillator or a cesium oscillator is used as a high stability oscillator, and an OCXO being a metastable oscillator which is inferior in a long-term frequency stability compared with the above oscillators but has a high short-term frequency stability is used as a backup. There is prepared a table in which an elapsed time since an occurrence of an abnormality in the high stability oscillator and weighting (use ratio) of use of the both oscillators is corresponded, and by using this table, after the high stability oscillator recovers, an oscillation frequency of the metastable oscillator is used by 100% initially, but thereafter the weighting (use ratio) of use of the metastable oscillator is made smaller and the use ratio of the high stability oscillator is made larger in stages. | 10-06-2011 |
| 20120056682 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OSCILLATION FREQUENCY CALIBRATION METHOD - A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature. | 03-08-2012 |
| 20120062326 | Self-Calibrating Relaxation Oscillator Based Clock Cycle - A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners. | 03-15-2012 |
| 20120133443 | SYSTEM AND METHOD FOR SELECTING OPTIMUM LOCAL OSCILLATOR DISCIPLINE SOURCE - A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input configured to receive a respective second signal having timing information, frequency information, phase information or combinations thereof. The prioritizer is configured to determine an accuracy of at least one second signal of the at least two second signals in relation to a second signal assigned to be a most accurate of the at least two second signals. The prioritizer is also configured to order the at least two second signals from most accurate to least accurate. The LO is disciplined to correct an offset error of the LO relative to a most accurate second signal that is available to the device, based on the order of the at least two second signals. | 05-31-2012 |
| 20120200361 | SYSTEM AND METHOD FOR REDUCING HOLDOVER DURATION - A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The second signal is used for disciplining the LO. The LO error corrector is capable of disciplining the LO using a source that is less accurate than a preferred second signal, if the preferred second signal is unavailable to discipline the LO. | 08-09-2012 |
| 20120200362 | METHOD AND SYSTEM FOR USING A MEMS STRUCTURE AS A TIMING SOURCE - A system and method is disclosed that provides a technique for generating an accurate time base for MEMS sensors and actuators which has a vibrating MEMS structure. The accurate clock is generated from the MEMS oscillations and converted to the usable range by means of a frequency translation circuit. | 08-09-2012 |
| 20120268215 | CIRCUIT ARRANGEMENT FOR GENERATION OF RADIO FREQUENCY OUTPUT SIGNALS WHICH FORM A BROADBAND FREQUENCY RAMP - A circuit arrangement for generation of radio frequency output signals which form a broadband frequency ramp, with a reference oscillator, a phase detector, a loop filter, a VC oscillator for generating the output signals, a frequency divider, a step-down mixer and a local oscillator for generating a local oscillator signal. The reference oscillator, the phase detector, the loop filter, the VC oscillator, the frequency divider and the step-down mixer belong to a phase-locking loop. The frequency divider and the step-down mixer are in the feedback path of the phase-locking loop. The step-down mixer mixes the output signals and the local oscillator signal. The frequency of the output signal is adjustable by varying the division ratio of the frequency divider. Characteristics of the output signal are improved using the adjustable frequency of the local oscillator signal. | 10-25-2012 |
| 20120293269 | INTEGRATED CIRCUIT FREQUENCY GENERATOR - An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles. | 11-22-2012 |
| 20130169368 | Method and Apparatus of a Resonant Oscillator Separately Driving Two Independent Functions - Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function. | 07-04-2013 |
| 20130257547 | SEMICONDUCTOR DEVICE AND VARIATION INFORMATION OBTAINING PROGRAM - A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information. | 10-03-2013 |
| 20130271228 | MICRO-ELECTRO-MECHANICAL-SYSTEM (MEMS) DRIVER - In an example, a driver for a micro-electro-mechanical-system (MEMS) device can include a first input configured to receive a first command signal including an oscillatory command signal, a second input configured to receive a second command signal including a bias command signal, and an amplifier configured to receive a high voltage supply, to provide, to the MEMS device, a closed-loop output signal responsive to both the first command signal and the second command signal in a first state, and to provide an open loop output signal configured to substantially span a voltage range of the high voltage supply in a second state. | 10-17-2013 |
| 20130342277 | High-Frequency Signal Generator with Low Phase Noise - A high-frequency oscillator comprises a reference-frequency generator and a high-frequency generator. The reference-frequency generator generates a variable reference frequency and supplies it to the high-frequency generator. The high-frequency generator comprises a phase-locked loop and generates a high-frequency signal from the variable reference frequency. The phase-locked loop comprises at least one first mixer, a second mixer and several switches. The first mixer, the second mixer and the switches are connected in series. The mixers are connected into the phase-locked loop individually in a selective manner by means of the switches. | 12-26-2013 |
| 20140085013 | OSCILLATORS HAVING ARBITRARY FREQUENCIES AND RELATED SYSTEMS AND METHODS - Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal. | 03-27-2014 |
| 20140091865 | OSCILLATION CIRCUIT, ELECTRONIC APPARATUS, AND MOVING OBJECT - An oscillation circuit is connected to a resonator element (crystal resonator) and oscillates a resonator element to output an oscillation signal. The oscillation circuit includes an amplification element (inverter), and a set of variable capacitive elements having at least two variable capacitive elements, which are connected to an oscillation loop from an output to an input of the amplification element and the capacitance values thereof are controlled with potential differences between reference voltages and a variable control voltage. In each variable capacitive element of a set of variable capacitive elements, the common control voltage is applied to one terminal, and the reference voltage which differs between the variable capacitive elements is input to the other terminal. | 04-03-2014 |
| 20140176245 | OSCILLATOR AND SELF-CALIBRATION METHOD THEREOF - An oscillator and a self-calibration method thereof are provided. The oscillator includes: an oscillation unit for generating an oscillation signal; a converting unit for converting frequency of the oscillation signal into a voltage signal; a comparison unit for comparing the voltage signal with a first voltage corresponding to a higher frequency and a second voltage corresponding to a lower frequency, and outputting a comparison result signal; an adjusting unit for storing a calibration value, adjusting the calibration value based on the comparison result signal and outputting a calibration signal corresponding to the adjusted calibration value; and a calibration unit for calibrating the frequency of the oscillation signal based on the calibration signal. Self-calibration for the frequency of the oscillation signal may be achieved, which may ensure the stability of the frequency of the oscillation signal. | 06-26-2014 |
| 20140191811 | INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION - A calibration circuit includes a combinational gate configured to receive a voltage-controlled oscillator (VCO) output signal and a selected reference signal to detect a phase difference between the VCO output signal and the selected reference signal and generate an output binary signal, in which the VCO output signal has one or more unwanted frequency components. The calibration circuit also includes a loop filter configured to filter the output binary signal and generate a filtered calibration signal. The calibration circuit also includes an analog-to-digital converter configured to convert the filtered calibration signal from the analog domain to the digital domain and generate a converted calibration signal. The calibration circuit also includes a processor configured to compute the converted calibration signal and determine components of a baseband signal that cancels the one or more unwanted frequency components of the VCO output signal. | 07-10-2014 |
| 20140292418 | OSCILLATION DEVICE - An oscillation device corrects a setting value of an output frequency based on a detection result of an ambient temperature of a crystal unit. The oscillation device includes: an oscillation circuit; a temperature detection portion that detects the ambient temperature and outputs a digital value corresponding to the temperature detection value; an accumulator that accumulates the digital value; a rounding processing portion that performs rounding for the digital value accumulated in the accumulator; a digital filter that receives the digital value obtained from the rounding processing portion and obtains a step response gradually increasing from “0” and converging to a step value; and a correction value obtaining portion that obtains a frequency correction value of the oscillation frequency of the oscillation circuit caused by a difference between the ambient temperature and a reference temperature, wherein the setting value of the output frequency is corrected based on the frequency correction value. | 10-02-2014 |
| 20140320215 | Oscillator - An oscillator, comprising: a pair of transistors to which source terminals are interconnected and to which drain and gate terminals are coupled by a positive feedback loop comprising an oscillator tank, wherein the source terminals of the transistors are connected to a current source configured to control physical parameters of the oscillator. | 10-30-2014 |
| 20140354364 | OSCILLATOR WITH STARTUP CIRCUITRY - An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation. | 12-04-2014 |
| 20140361840 | CRYSTAL-LESS CLOCK GENERATOR AND OPERATION METHOD THEREOF - A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal. | 12-11-2014 |
| 20140361841 | SIGNAL GENERATION CIRCUIT, SIGNAL GENERATION APPARATUS, METHOD FOR MANUFACTURING SIGNAL GENERATION APPARATUS, ELECTRONIC APPARATUS, AND MOVING OBJECT - A signal generation circuit including a phase locked loop circuit that uses an oscillation section as a reference signal source and a switching section capable of switching a state in which a periodic signal from the oscillation section is outputted to a state in which a signal from the phase locked loop circuit is outputted. | 12-11-2014 |
| 20140368282 | FREQUENCY GENERATION DEVICE - A frequency generation device is provided. The frequency generation device includes a voltage generation unit configured to receive an input signal having an input frequency and to generate a feedback voltage based on the input signal, wherein the feedback voltage is proportional to the input frequency; and a feedback unit connected to the voltage generation unit and a reference voltage source, wherein the feedback unit is configured to receive a reference voltage from the reference voltage source and the feedback voltage from the voltage generation unit, so as to generate a feedback signal having a feedback frequency. | 12-18-2014 |
| 20150028956 | SEMICONDUCTOR DEVICE - The disclosed invention is intended to adjust the driving power of an oscillation circuit to be optimal with a simple circuit configuration. A chip includes an oscillation circuit, an amplifier, an effective value measuring circuit, and a control unit. The oscillation circuit includes an inverting amplifier and a resistor coupled in parallel to the inverting amplifier. The oscillation circuit in which the inverting amplifier is coupled to a crystal oscillator outside the chip generates an oscillation circuit by driving the crystal oscillator. The effective value measuring circuit measures an effective value of an oscillation signal produced by the oscillation circuit. The control unit controls the gain of the inverting amplifier so that the effective value will be equal to a target voltage. | 01-29-2015 |
| 20150042407 | METHOD FOR DETECTING FREQUENCY OFFSET OF OSCILLATOR AND ASSOCIATED CIRCUIT - A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing signal according to the oscillation signal; performing frequency division upon the self-mixing signal to obtain a down-converted self-mixing signal; obtaining a down-converted self-mixing frequency corresponding to a maximum power in a specific frequency range of the down-converted self-mixing signal; and computing a frequency offset of the oscillation frequency according to at least the oscillation frequency and the down-converted self-mixing frequency. A related circuit is also disclosed. | 02-12-2015 |
| 20150054589 | RADIATION-HARD PRECISION VOLTAGE REFERENCE - According to one aspect, embodiments herein provide a PVR comprising a resonator having an oscillation frequency, the resonator comprising at least one proof-mass, a mechanical reference, at least one drive plate located adjacent a first side of the at least one proof-mass, and at least one sense plate located adjacent a second side of the at least one proof-mass, a voltage source coupled to the drive and sense plates, a reference oscillator configured to provide a reference signal having a reference frequency to the voltage source; and an output, wherein the voltage source is configured to provide a bias voltage signal to the at least one drive and at least one sense plates of the resonator to drive the oscillation frequency of the resonator to match the reference frequency, and wherein the bias voltage signal is also provided to the output of the PVR as a voltage reference signal. | 02-26-2015 |
| 20150077189 | OSCILLATOR - An oscillator includes a voltage controlled oscillator, a PLL circuit, a crystal unit and an oscillator circuit configured to generate a clock, a digital control circuit, and a clock switching unit. The digital control circuit is configured to set an oscillation parameter of the oscillator circuit, and a parameter of the PLL circuit. The clock switching unit is configured to supply an output signal of the voltage controlled oscillator to the digital control circuit as a clock signal so as to cause the digital control circuit to operate using the clock signal when powered on, and configured to supply an output signal of the oscillator circuit to the digital control circuit as a clock signal after the digital control circuit sets the oscillation parameter of the oscillator circuit. An initial voltage is supplied to the voltage controlled oscillator as a control voltage when the oscillator is powered on. | 03-19-2015 |
| 20150097627 | Clock Generation System - A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock. | 04-09-2015 |
| 20150130544 | METHOD AND APPARATUS TO CALIBRATE FREQUENCY SYNTHESIZER - Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal indicative a timing difference between a reference clock signal and a feedback clock signal. The feedback clock signal is generated based on an oscillating signal from an oscillator. The oscillator includes a first tuning circuit and a second tuning circuit to tune a frequency of the oscillating signal. The loop filter is configured to filter out a portion of frequency components from the first signal to generate a second signal for tuning the first tuning circuit of the oscillator. The controller is configured to tune the second tuning circuit based on the first signal and the second signal. | 05-14-2015 |
| 20150349789 | OSCILLATOR CIRCUIT AND CONFIGURATION METHOD THEREOF - The present disclosure provides an oscillator circuit. The oscillator circuit includes a signal selecting unit, a control voltage generating unit, a reference voltage generating unit, an output adjusting unit, and a frequency-dividing unit. The signal selecting unit is configured to select a reference signal or a frequency-divided signal as an input signal. The control voltage generating unit is configured to generate a control voltage based on the input signal. The reference voltage generating unit is configured to generate a reference voltage. The output adjusting unit is configured to generate an output signal based on the control voltage and the reference voltage. The frequency-dividing unit is configured to divide the frequency of the output signal and generate the frequency-divided signal. | 12-03-2015 |
| 20150365096 | ANTI PROCESS VARIATION SELF-ADJUSTABLE ON-CHIP OSCILLATOR - An anti process variation self-adjustable on-chip oscillator has been disclosed according to the present invention. The on-chip oscillator includes the following components integrated on a same chip: a reference oscillation unit for producing reference pulse; an oscillation unit to be adjusted for producing output pulse; and a self-adjustable logic control unit for receiving the reference pulse and output pulse, and for transmitting a corresponding adjustment signal to the oscillation unit to be adjusted based on the received reference pulse and output pulse to control the oscillation unit to be adjusted to perform the frequency adjustment to the output pulse. The reference pulse required for adjusting the frequency can be generated by the reference oscillation unit integrated on-chip, so that self-adjustment can be achieved on-chip, decrease the cost of the chip compared with off-chip adjustment. | 12-17-2015 |
| 20160112054 | DEVICE FOR GENERATING FREQUENCY-STABLE SIGNALS WITH SWITCHABLE INJECTION-LOCKED OSCILLATOR - A device for generating at least one frequency-stable periodical signal, including: a generator configured to generate at least one first periodical signal with frequency spectrum that includes at least two lines at different frequencies f | 04-21-2016 |
| 20160118991 | Oscillator Device - An oscillator device comprises an oscillation circuit configured to generate and provide an oscillating signal. A first biasing circuit is configured to derive a bias current signal in accordance with a control signal and apply the bias current signal to the oscillation circuit to control the amplitude level of the oscillating signal. A reference generating circuit is configured to generate a reference voltage signal and comprises a second biasing circuit configured to derive a reference bias current signal in accordance with the control signal. A comparison circuit is configured to determine an error signal by comparing a voltage signal at an output of the first biasing circuit with the reference voltage signal observed at an output of the second biasing circuit. A controller is configured to determine the control signal related to the error signal and provide the control signal to the first biasing circuit and the second biasing circuit. | 04-28-2016 |
| 20160191061 | UNIVERSAL OSCILLATOR - The disclosure provides a universal oscillator. The oscillator includes an amplifier array. The amplifier array includes one or more amplifiers. A control logic unit is coupled to the amplifier array and activates the one or more amplifiers. A self-clock generating circuit is coupled to the control logic unit and generates a fixed clock. A counter receives the fixed clock from the self-clock generating circuit and provides a controlled clock to the control logic unit. | 06-30-2016 |
