Class / Patent application number | Description | Number of patent applications / Date published |
331017000 | Particular error voltage control (e.g., intergrating network) | 74 |
20080211588 | Phase Error Cancellation - A noise cancellation signal is generated for a fractional-N phase-locked loop ( | 09-04-2008 |
20080218276 | MEANS TO CONTROL PLL PHASE SLEW RATE - A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin. | 09-11-2008 |
20080218277 | Apparatus and method for operating a phase-locked loop circuit - An apparatus and method for operating a phase-locked loop circuit are disclosed. The phase locked loop circuit includes a plurality of resistive elements and a plurality of capacitive elements that are distributed in a charge pump, a loop filter and a voltage controlled oscillator. The plurality of resistive elements have a plurality of resistances that vary in proportion to each other. The plurality of capacitive elements have a plurality of capacitive elements that vary in proportion to each other. A damping factor of the phase-locked loop circuit is maintained substantially constant by the plurality of resistive elements and the plurality of capacitive elements. | 09-11-2008 |
20080218278 | MEANS TO CONTROL PLL PHASE SLEW RATE - A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin. | 09-11-2008 |
20080231375 | METHOD AND SYSTEM FOR USING A FREQUENCY LOCKED LOOP LOGEN IN OSCILLATOR SYSTEMS - Aspects of a method and system for using a frequency locked loop LOGEN in oscillator systems may include generating an oscillating signal via one or more circuits comprising a feedback loop. The generation may be controlled by enabling or disabling the feedback loop, based on the generated oscillating signal. The one or more circuits may comprise a frequency-locked loop (FLL) that may enable the generation of the oscillating signal. The frequency-locked loop may comprise a voltage-controlled oscillator. The feedback loop may be disabled when an estimated frequency difference between a reference signal and a feedback signal may be less than or equal to a specified threshold. The feedback loop may be enabled when an estimated frequency difference between a reference signal and a feedback signal may be greater than a particular threshold. | 09-25-2008 |
20080258822 | OSCILLATOR CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A stable frequency is outputted by an oscillator circuit including a constant current circuit which is electrically connected between a first terminal and a second terminal, a voltage controlled oscillator circuit in which an oscillation frequency fluctuates in accordance with a potential difference between power supply voltage terminals, an n-channel transistor, a p-channel transistor in which a gate-source voltage is set to be constant by the constant current circuit, and a capacitor, in which a source electrode of the p-channel transistor is electrically connected to the first terminal, a drain electrode of the p-channel transistor is electrically connected a drain electrode and a gate electrode of the n-channel transistor, a source electrode of the n-channel transistor is electrically connected to the second terminal, and a gate electrode of the n-channel transistor is electrically connected to the second terminal through the capacitor. | 10-23-2008 |
20080278245 | Wireless communication semiconductor integrated circuit device and mobile communication system - An RF IC in which a PLL circuit including a loop filter is incorporated into a semiconductor chip is achieved without increasing power consumption or chip size. The RF IC includes a VCO capable of switching oscillation frequency bands, a variable frequency divider, a phase comparator, and a loop filter, which are contained in the PLL loop. A discrimination circuit discriminates a lead or lag in a phase of an output signal from the variable frequency divider against a reference signal and an automatic band selecting circuit generates a signal for switching the frequency bands of the VCO based on output from the discrimination circuit. While switching the frequency bands of the VCO by means of bisection algorithm, the RF IC detects an optimum frequency band, and adds offset to it to determine a final usable frequency band. | 11-13-2008 |
20080284527 | PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME - A phase locked loop can reduce a locking time, thereby efficiently reducing power in a locking operation. The phase locked loop includes a phase detector, a control voltage generator, a voltage controlled oscillator and a start-up driver. The phase detector detects a phase difference between a reference clock and a feedback clock to generate a detection signal corresponding to the detected phase difference. The control voltage generator generates a control voltage having a voltage level corresponding to the detection signal. The voltage controlled oscillator generates an internal clock having a frequency corresponding to a voltage level of the control voltage. The start-up driver drives a control voltage terminal to a predefined start-up level in response to a start-up level multiplex signal corresponding to a frequency of the reference clock prior to activation of the voltage controlled oscillator. | 11-20-2008 |
20080303599 | SEMICONDUCTOR DEVICE - There is provided a PLL circuit | 12-11-2008 |
20080315958 | PHASE-LOCKED LOOP CIRCUIT, PHASE-LOCKED LOOP CONTROL APPARATUS, AND PHASE-LOCKED LOOP CONTROL METHOD - According to one embodiment, a phase-locked loop circuit comprises a phase difference detection unit which detects a phase error between a reproduced binary data and extracted clock and generates phase error pulse signals each having an amplitude corresponding to the phase error, a phase sifter sensitivity adjusting unit which generates a first adjustment pulse signal produced by adjusting the phase error pulse signal, and a loop filter unit which generates a pulse train signal for feedback control to generate the extracted clock from the first adjustment signal, wherein the phase shifter sensitivity adjusting unit comprises a first pulse doubler unit which generates an expanded pulse signal which doubles a time width of the phase error pulse signal, and a first amplifying unit which amplifies the amplitude of the expanded pulse signal and generates the first adjustment pulse signal. | 12-25-2008 |
20080315959 | Low Power All Digital PLL Architecture - A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals. | 12-25-2008 |
20080315960 | Digital Phase Locked Loop with Gear Shifting - An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha-α) and an integral loop gain control having a programmable loop gain coefficient (rho-ρ). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged | 12-25-2008 |
20090033428 | VOLTAGE CONTROLLED OSCILLATOR - An integrated circuit is provided. The integrated circuit comprises a voltage controlled oscillator and a first compensation capacitor. The voltage controlled oscillator generates an oscillation signal. The first compensation capacitor, coupled in parallel to the voltage controlled oscillator, receives a control voltage to generate a negative temperature coefficient capacitance to compensate for frequency drift of the oscillation signal. The control voltage is temperature dependent. | 02-05-2009 |
20090033429 | Phase locked loop for stably operating in a matter that is insensitive to variation in process, voltage and temperature and method of operating the same - A phase locked loop for stably operating in a matter that is insensitive to variation in PVT and a method of operating the same. The PLL according to the present invention includes a PFD, a charge pump circuit, a loop filter, a VCO, and a peak voltage detector. The PFD compares a phase or frequency of a reference signal with a phase or frequency of an output signal and outputs an up signal or a down signal based on the comparison result. The charge pump circuit generates a pumping current in response to the up signal or the down signal and increases or decreases the pumping current in response to a detection signal. The loop filter outputs control voltage according to the pumping current. The VCO outputs the output signal having a frequency determined based on the control voltage. The peak voltage detector detects the peak value of the control voltage and outputs the detection signal based on the detection result. The PLL detects the peak value of control voltage and controls the operation of a charge pump circuit based on the detection result thereby decreasing the peaking and ringing phenomena of the control voltage and then stably operating in a manner that is insensitive to variation in PVT. | 02-05-2009 |
20090058535 | CONSTANT CALIBRATION - An oscillating signal of relatively precise frequency can be generated by tuning an oscillator using an external stable oscillating source as a reference. Calibration logic can be included to compare a signal from the local oscillator to the reference signal and vary the local signal to a desired frequency. In one embodiment, the frequency of the local signal can be constantly or periodically compared with a threshold value and if the frequency exceeds the threshold value, the local oscillator can be modified to produce a signal having a frequency that is closer to a desired frequency. | 03-05-2009 |
20090058536 | APPARATUS AND METHOD FOR PHASE LOCK LOOP GAIN CONTROL USING UNIT CURRENT SOURCES - A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for-changing PLL operating conditions, in addition to compensating for variable VCO gain. | 03-05-2009 |
20090085672 | FREQUENCY SYNTHESIZER - By performing rough adjustment of a local oscillation frequency by a first lock loop using an up/down counter ( | 04-02-2009 |
20090096535 | All-Digital Phase-Locked Loop - For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with only digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By modulating certain parameters within the ADPLL by following an all-pass frequency response, a loop gain of the ADPLL may be precisely modulated, and an available bandwidth of the ADPLL is also significantly broadened. | 04-16-2009 |
20090115534 | PHASE LOCKED OSCILLATOR - There is provided an analog phase locked oscillator comprising a sampling phase detector, a loop filter, a voltage controlled oscillator, a frequency multiplier and a feedback loop where the feedback loop connects the output of said oscillator with the input of said phase detector through said frequency multiplier. The sampling phase detector is adapted to perform a discrete phase comparison between a reference frequency and the multiplied feedback signal. The voltage controlled oscillator is adapted to give out a constant frequency at a multiply of the reference frequency divided with the multiplication factor of the multiplier. | 05-07-2009 |
20090121794 | Phase lock control system for a voltage controlled oscillator - A phase lock control system is presented for controlling a voltage controlled oscillator. The system includes a voltage controlled oscillator that produces a frequency signal exhibiting an output frequency that varies dependent upon the value of a control voltage applied thereto. A frequency deviation determining system employs a counter intermittently triggered ON for a fixed time by successive timing pulses received from a reference source and a comparator that determines any frequency deviation of the output frequency relative to a preset frequency. An error filter monitors the comparator for any frequency deviation for a plurality of samples of the frequency deviation determinations. A controller varies the control voltage to vary the output frequency in a direction to eliminate any frequency deviation. | 05-14-2009 |
20090128242 | FREQUENCY GENERATION IN A WIRELESS COMMUNICATION UNIT - A wireless communication unit comprises a frequency generation circuit employing a fractional-based synthesiser, a voltage controlled oscillator circuit and a charge pump. A characterising function characterises a charge pump gain at a number of synthesized frequencies. A memory element is arranged to store characterised parameters. A scaling function is operably coupled to the memory element and the voltage controlled oscillator circuit and arranged to compensate for K | 05-21-2009 |
20090128243 | SEMICONDUCTOR DEVICE OUTPUTTING OSCILLATION SIGNAL - A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit. | 05-21-2009 |
20090140817 | TRANSISTOR VOLTAGE-CONTROLLED OSCILLATOR AND FREQUENCY SYTHESIZER HAVING THE SAME - A transistor voltage-controlled oscillator (VCO) and a frequency synthesizer having the transistor VCO are provided. The frequency synthesizer adopts a divide-by-five injection-locked frequency divider, which includes a five-stage inverter ring oscillating frequency dividing circuit for reducing the operating frequency of the oscillating signal from the VCO, thus decreasing power consumption due to counting operation of the frequency synthesizer. The transistor VCO includes three transistor switching capacitor sets connected in parallel to one another to form a parallel structure. The gates of the transistor switching capacitor sets are connected to respective operating voltage sources, so as to switch the status of the corresponding transistor switching capacitor set, which in turn adjusts the harmonic frequency generated by the VCO, thereby allowing the VCO to generate a corresponding operating frequency with enough bandwidth. | 06-04-2009 |
20090160560 | Phase locked loop and method for controlling the same - Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump. | 06-25-2009 |
20090179707 | SIGNAL PROCESSING CIRCUIT, SIGNAL PROCESSING METHOD, AND PLAYBACK APPARATUS - A signal processing circuit includes a feedback control loop that includes a loop filter and that detects the difference between a target value and a control value to control the difference so that the difference has a predetermined value. A closed loop formed in the feedback control loop is expressed by the delay of the entire closed loop serving as the feedback control loop, the loop filter, and simple integration of a final stage. The signal processing circuit includes a moving average calculating unit configured to calculate a moving average of outputs from the loop filter; a multiplying unit configured to multiply a value calculated in the loop filter by a certain gain; and an integrating unit provided upstream of the loop filter so that calculation results by the moving average calculating unit and the multiplication unit are concurrently fed back to an input into the loop filter. | 07-16-2009 |
20090189701 | Single-Ended to Differential Translator to Control Current Starved Delay Cell Bias - A method, system, and circuit device for interfacing single-ended charge pump output to differential voltage controlled oscillator (VCO) inputs to yield low duty cycle distortion from a VCO. A single-ended charge pump output is utilized to create a compliment differential voltage leg, while optimally centering the common-mode voltage level to interface to a current starved ring VCO. A replica of the VCO's current starved delay cell is implemented along with negative feedback to generate the compliment differential voltage leg. The single-ended charge pump output is coupled to a first transistor, while a second transistor is coupled to the output of an error amplifier. The error amplifier utilizes negative feedback to bias the second transistor, forcing the output of the replica circuit to equal a reference voltage. | 07-30-2009 |
20090195321 | INTEGRATED FREQUENCY CALIBRATION ARCHITECTURE - In an exemplary embodiment, a free running VCO has two modes: a normal operating mode and a calibration mode. In the calibration mode, the free running VCO is phase lock looped with itself instead of a calibration VCO. Furthermore, in an exemplary embodiment, a tuning voltage for the free running VCO is adjusted to offset any tuning error. In addition, in various embodiments a reference crystal oscillator used in the phase lock loop is located on a DSP module instead of on the RF module. In yet another exemplary embodiment, the free running VCO is the only high frequency VCO on a radio frequency module. | 08-06-2009 |
20090231046 | Low spur phase-locked loop architecture - A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below −80 dBc. | 09-17-2009 |
20090261909 | Voltage-controlled oscillator including plurality of delay cells - A voltage-controlled oscillator includes a delay circuit. The delay circuit includes a first buffer inverter which receives one of the differential input signal and outputs an other of the differential output signal, a second buffer inverter which receives the other of the differential input signal and outputs the one of the differential output signal, a first latch inverter which receives the one of the differential output signal, and includes an output connected to an output of the first buffer inverter, and a second latch inverter which receives the other of the differential output signal, and includes an output connected to an output of the second buffer inverter. The first latch inverter and the first buffer inverter receive a current produced from different voltage-current conversion circuits. | 10-22-2009 |
20090278614 | PHASE SYNCHRONIZING CIRCUIT - A constant determination unit ( | 11-12-2009 |
20090289725 | Self-Biased Phase Locked Loop - The present invention discloses a self-bias PLL including a phase frequency detector, a charge pump, a loop filter, a voltage control oscillator, a divider and a bias current converter. A charging or discharging current output from the charge pump equals to a first control current. A resistor of the loop filter is controlled by a first control voltage a second control voltage which is adjusted according to the first control voltage and a second control current. The loop filter increases or decreases the first control voltage according to the charging or discharging current output from the charge pump. The voltage control oscillator generates a bias current and an oscillation voltage according to the first control voltage and increases or decreases an oscillation frequency according to the increase or decrease of the oscillation voltage. The circuit structure of the self-bias PLL is simple and the self-bias PLL has a low jitter. | 11-26-2009 |
20090289726 | Self-Biased Phase Locked Loop - A self-biased PLL includes a first charge pump and a second charge pump, an output terminal of the first charge pump is connected with a discharge-charge capacitor to output a control voltage, an output terminal of the second charge pump is connected with an output terminal of a bias generator for outputting a first bias voltage equal to the control voltage, wherein, a current output from the first charge pump is equal to a value obtained through dividing the production of a first constant with a bias current of a voltage control oscillator by a frequency division factor of a frequency divider; a current output from the second charge pump is equal to a value obtained through dividing the bias current of the voltage control oscillator by a second constant; and a multiple relation exists between an output resistance of the bias generator and an equivalent resistance of a differential buffer delay stage in the voltage control oscillator. | 11-26-2009 |
20090295489 | PLL CIRCUIT - In a PLL circuit, a voltage controlled oscillator | 12-03-2009 |
20100019854 | System And Method For Effectively Implementing A Loop Filter Device - A system and method for effectively generating an electronic control signal includes a loop filter that has a first capacitor, a second capacitor, and a damping resistor. The first capacitor typically has a significantly greater capacitance than said second capacitor. A primary charge pump provides a primary charge current to the loop filter, and a damping charge pump provides a damping charge current to the loop filter. The loop filter responsively generates the electronic control signal for regulating the output frequency of a voltage-controlled oscillator. All components of the loop filter are sized to be implemented as part of an integrated circuit device. | 01-28-2010 |
20100026396 | COMPENSATED HIGH-SPEED PLL CIRCUIT - The invention relates to a compensation method and phase-locked loop (PLL) circuit, wherein different kinds of two-point modulations are used and the integral regulator of a loop filter is replaced by introducing predetermined settings at the loop filter or at a voltage controlled oscillator. Thereby, the dynamic settling time of the PLL circuit can be improved to gain time for other circuit components which can thus assure required precision for the modulation. | 02-04-2010 |
20100052796 | Device Having Digitally Controlled Oscillator - A device includes a digitally controlled oscillator and an interpolator having a data input and a data output coupled to the digitally controlled oscillator. The interpolator may be configured to receive an oscillator control signal at the data input and to provide an interpolated oscillator control signal at the data output. An interpolation rate of the interpolator may depend on the oscillator control signal. Alternatively, a device can include a digitally controlled oscillator having a control input, a sampling unit coupled to the control input of the digitally controlled oscillator, and a timing error detector coupled to an output of the digitally controlled oscillator. The sampling rate of the sampling unit can depend on an output of the timing error detector. | 03-04-2010 |
20100060364 | PROGRAMMABLE VOLTAGE-CONTROLLED OSCILLATOR - The invention discloses a programmable voltage-controlled oscillator. The programmable voltage-controlled oscillator has an output frequency. The programmable voltage-controlled oscillator includes a control unit, a current selector, a current mirror unit, an oscillator module, and a one-time-programming component. The one-time-programming component is used for providing a programmable code. The current selector is used for generating a selected current according to the programmable code. The current mirror unit is used for generating a first mirroring current and a second mirroring current according to the selected current. The oscillator module is used for oscillating according to the first mirroring current and the second mirroring current. After the programmable code is tuned to drive the output frequency to approach a predetermined frequency, the control unit will burn the tuned programmable code into one-time-programming component. | 03-11-2010 |
20100060365 | Oscillation frequency control circuit - To provide a highly stable oscillation frequency control circuit wherein the frequency thereof is corrected, an adequate range of the input levels of external reference signals is determined in accordance with temperature characteristics in detecting the external reference signal, and the control voltage to a VCO is controlled within and outside the adequate range. An oscillation frequency control circuit includes a selection switch that connects the phase comparator to the loop filter in an external reference synchronization mode and that connects the fixed voltage supplying circuit to the loop filter in a fixed voltage mode, and a CPU that switches the selection switch to the external reference synchronization mode or to the fixed voltage mode based on whether the detected voltage of an external reference signal level is within or outside of the adequate range. | 03-11-2010 |
20100090769 | Digital Loop Filter for All-Digital Phase-Locked Loop Design - A digital loop filter installed in an all-digital phase-locked loop (PLL) receives a digitally controlled oscillator (DCO) control code transmitted from a PLL controller in the all-digital PLL, and calculate an average value, such that the PLL controller can produce another DCO control code by the average value for controlling and adjusting an output signal of a digitally controlled oscillator (DCO) in the neighborhood of the average value to maintain compensating a phase/frequency difference with an input signal, so as to minimize the jitter effect of the input signal on the all-digital PLL, reduce the jitter effect of the output signal, and keep tracking and locking the frequency and the phase of the input signal. | 04-15-2010 |
20100102889 | SYSTEMS AND METHODS FOR TRACKING COMMUNICATION PARAMETERS OVER A PLURALITY OF FREQUENCY BANDS - In at least some embodiments, a communication system includes a receiver having a local oscillator (LO) for each of a plurality of frequency bands. Each LO is controlled by a separate phase-locked loop (PLL) that tracks carrier frequency offset (CFO) using a common phase error (CPE). The CPE is selectively weighted based on at least one inter-band frequency correlation (IFC) coefficient. | 04-29-2010 |
20100117741 | PLL Circuit - A VCO/current switching circuit outputs a VCO selection signal for selecting one VCO out of two or more VCOs on the basis of the externally provided frequency division data. Moreover, when switching the VCOs, the VCO/current switching circuit outputs a switching signal for changing the output current of the variable charge pump to a larger value than normal (value when it is locked). After completing the switching of the VCOs, the VCO/current switching circuit outputs a switching signal for changing the output current of the variable charge pump to a normal small value. | 05-13-2010 |
20100141347 | Band Selecting Method Applied to Voltage Controlled Oscillator of Phase Locked Loop Circuit and Associated Apparatus - A band selecting method applied to a voltage controlled oscillator (VCO) of a phase locked loop (PLL) and an associated method is provided. The band selecting method generates an open-loop control voltage according to a temperature signal; inputting the open-loop control voltage into the VCO; switching sequentially between a plurality of frequency bands of the VCO and generating a plurality of voltage controlled signals for the frequency bands; selecting a preferred voltage controlled signal and its corresponding frequency band as an operating band for the PLL. | 06-10-2010 |
20100164633 | PLL CIRCUIT AND RADIO COMMUNICATION APPARATUS - A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector. | 07-01-2010 |
20100164634 | PHASE LOCKED LOOP CIRCUIT - A phase locked loop circuit is provided comprising a voltage controlled oscillator (VCO), frequency divider, phase frequency detector (PFD), charge pump, waveform generator, loop filter, switching circuit, and lock detector. The VCO generates an oscillation signal. The frequency divider multiplies the frequency of the oscillation signal. The PFD compares the frequency-multiplied oscillation signal and an externally inputted reference signal to generate an error signal. The charge pump generates a signal according to the error signal. The loop filter controls the VCO to modulate the frequency of the oscillation signal and generate a spread spectrum clock based on the signal of the charge pump or waveform generator. The lock detector controls the switching circuit to selectively connect the charge pump to the loop filter during a non-lock state and the waveform generator to the loop filter during a lock state. | 07-01-2010 |
20100171557 | VOLTAGE CONTROLLED OSCILLATOR, AND PLL CIRCUIT AND WIRLESS COMMUNICATION DEVICE EACH USING THE SAME - A voltage controlled oscillator includes first and second variable capacitance circuits | 07-08-2010 |
20100194482 | COMPENSATION OF VCO GAIN CURVE OFFSETS USING AUTO-CALIBRATION - A method is provided for selecting an operating band of a voltage-controlled oscillator (“VCO”) of a phase locked loop (“PLL”) for which the lock frequency is closest to a center of the frequency range of the operating band. In such method, steps can be performed to determine the maximum and minimum frequencies of the operating band and the center frequency between them. From the center frequency of the operating band and the lock frequency within such operating band, a difference value can then be determined. The operating bands of the PLL can be tested until an operating band having the smallest difference value is determined. The VCO can then be set to such operating band in order for the lock frequency to be closest to the center frequency of the operating band. | 08-05-2010 |
20100194483 | AUTO-CALIBRATION FOR RING OSCILLATOR VCO - A phase locked loop (“PLL”) includes a voltage controlled oscillator (“VCO”) operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating the VCO. Such method can include switching the VCO to a given operating band from among the plurality of operating bands of the VCO; determining a band center frequency at which the VCO oscillates in the given operating band when the control voltage is set to a center of a range of minimum to maximum control voltages [CVmin, CVmax]; determining a difference between the band center frequency and the selected output frequency when the selected output frequency is within the given operating band; switching the VCO to another operating band; repeating the above steps until a difference between the band center frequency and the selected output frequency increases; and selecting the operating band for operation of the VCO for which the difference between the band center frequency and the selected output frequency is smallest. | 08-05-2010 |
20100194484 | OSCILLATOR CIRCUIT AND MEMORY SYSTEM - An oscillator circuit generates a constant delay time by use of a current source and a load element to determine a frequency of a clock. The oscillator circuit includes an integrator which integrates the clock, a first comparator which compares an output voltage of the integrator with a reference voltage, and a variable current source which changes a current in accordance with the comparison result of the first comparator. The frequency is corrected in accordance with the current of the variable current source. | 08-05-2010 |
20100237952 | CURRENT CONTROLLED OSCILLATOR WITH REGULATED SYMMETRIC LOADS - An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, V | 09-23-2010 |
20100244967 | OSCILLATOR - An oscillator includes: a vibrator having a first electrode and a second electrode disposed with a gap with the first electrode; a reference voltage supply circuit adapted to supply a reference voltage; and a voltage adjustment circuit having a step-up circuit operating in response to input of clock pulses and adapted to convert the reference voltage into a voltage of a predetermined level and to output the voltage of the predetermined level, wherein the vibrator is configured so as to apply the voltage of the predetermined level, which is output from the voltage adjustment circuit, between the first electrode and the second electrode, and the clock pulses to be input into the step-up circuit are obtained using the vibrator as a source. | 09-30-2010 |
20100244968 | VOLTAGE-CONTROLLED OSCILLATOR, AND PLL CIRCUIT, FLL CIRCUIT, AND WIRELESS COMMUNICATION DEVICE USING THE SAME - Provided is a voltage-controlled oscillator that can hold an oscillation frequency at a desired value when an oscillation frequency changes due to the temperature, without narrowing a variable range of the oscillation frequency, and a PLL circuit, an FLL circuit, and a wireless communication device, which use the voltage-controlled oscillator. A control voltage Vt is applied to a connection point Y between variable capacitors | 09-30-2010 |
20100259332 | COMPENSATION CIRCUIT FOR VOLTAGE CONTROLLED OSCILLATOR - A circuit can be used to a control the voltage of a voltage controlled oscillator (VCO) can include a first comparator, a second comparator, an accumulator, and an output device. The first comparator outputs a first pulse signal when the control voltage is higher than a high threshold voltage. The second comparator outputs a second pulse signal when the control voltage is lower than a low threshold voltage. The accumulator increases the value of a switch control signal if the first pulse signal is received or decreases the value of the switch control signal if the second pulse signal is received. The output device generates a compensation voltage to compensate the control voltage of the VCO depending on the value of the switch control signal. | 10-14-2010 |
20100271138 | PHASE-LOCKED LOOP AND METHOD FOR OPERATING THE SAME - A phase-locked loop (PLL) system generates an oscillator signal based on an input reference signal. A calibration circuit generates a calibration current, and a voltage-to-current converter converts a control voltage into a first current. A current-controlled oscillator generates the oscillator signal based on the first current and the calibration current. A charge pump circuit, which is connected to a phase detector, the voltage-to-current converter, and the calibration circuit, generates a charge pump current based on the first current and the calibration current. The charge pump current is used to generate the control voltage based on an error signal. | 10-28-2010 |
20100271139 | SELF-CALIBRATING OSCILLATOR - An oscillator that increases the accuracy of an output frequency, without using a charge pump, has an oscillation circuit, first and second voltage supply circuits, and a calibration value generation circuit. The first voltage supply circuit includes a resistor and a capacitor, the resistance and capacitance of which are determined so that a first voltage reaches a reference voltage within a reference time. The second voltage supply circuit includes first and second switching means, which perform switching when receiving pulse signals corresponding to the frequency of the oscillation circuit to raise the second voltage. A calibration value generation circuit provides the oscillation circuit with a calibration value that lowers the frequency when the second voltage reaches the reference voltage before the first voltage and raises the frequency when the second voltage reaches the reference voltage after the first voltage. | 10-28-2010 |
20100315171 | VOLTAGE TRANSLATION USING FEEDBACK TO ADJUST OUTPUT VOLTAGE RANGE - Apparatus are provided for a voltage-controlled oscillator module. A voltage-controlled oscillator module comprises an input node for receiving an input voltage, a voltage-controlled oscillator, and voltage translation circuitry coupled between the input node and the voltage-controlled oscillator. The voltage translation circuitry is configured to generate a control voltage based on the input voltage and the voltage-controlled oscillator generates an oscillating signal at an oscillation frequency in response to the control voltage. Biasing circuitry is coupled to the voltage translation circuitry, and the biasing circuitry is configured to adjust the ratio of the control voltage to the input voltage. | 12-16-2010 |
20100327981 | Charge Pump Linearization Technique For Delta-Sigma Fractional-N Synthesizers - A delta-sigma fractional-N frequency synthesizer having a charge pump with error canceling circuitry eliminates a non-linear term from the charge pump transfer function. The charge pump includes a matched pair of charging current sources, each supplying a first current I | 12-30-2010 |
20110175682 | PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER AND LOOP LOCKING METHOD THEREOF - A phase-locked loop frequency synthesizer and a loop locking method thereof are provided. The phase-locked loop frequency synthesizer includes a reference route sigma-delta modulator feedback circuit, a reference phase integration circuit coupled to the output end of the reference route sigma-delta modulator feedback circuit, a phase/frequency detector coupled to the output ends of the reference and feedback phase integration circuit, a loop filter coupled to the output end of the phase/frequency detector and the input end of the reference route sigma-delta modulator feedback circuit, an oscillator coupled to the output end of the loop filter, and a feedback phase integration circuit coupled to the output end of the oscillator and the input end of the phase/frequency detector. In the phase-locked loop frequency synthesizer, the oscillator generates corresponding frequency output signals which yield the advantages of resisting noise signals, enhancing resolution, and facilitating integration. | 07-21-2011 |
20110234324 | SYSTEM AND METHOD FOR REDUCING LOCK TIME IN A PHASE-LOCKED LOOP - Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop. | 09-29-2011 |
20110254633 | METHOD AND APPARATUS FOR ALLEVIATING CHARGE LEAKAGE OF VCO FOR PHASE LOCK LOOP - Methods and apparatuses for alleviating charge leakage of VCO for phase lock loop are disclosed. The method comprises: receiving an input signal; generating an error signal representing a timing difference between the input signal and an output signal; filtering the error signal into a control signal; buffering the control signal into a buffered control signal; and generating the output signal in accordance with the buffered control signal. Buffering the control signal comprising using a high input resistance and low output resistance buffer circuit. | 10-20-2011 |
20120126901 | PROGRAMMABLE ELECTRO-MAGNETIC-INTERFERENCE (EMI) REDUCTION WITH ENHANCED NOISE IMMUNITY AND PROCESS TOLERANCE - A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC. | 05-24-2012 |
20120176201 | PID CONTROL FOR TRANSMITTER-RECEIVER SYNCHRONIZATION - Various embodiments relate to a receiver and a timing circuit for synchronization between a transmitter clock of an MPEG stream and the local system clock of a receiver. The timing circuit may implement a phase-locked loop (PLL) circuit with a MD controller to produce a control signal based on the difference between the transmitter reference clock and the local system clock. Various embodiments may use clock differential signals and an accumulated error signal to produce proportional, integral, and derivative output components for a control signal. The control signal may control a signal generator that adjusts the frequency and/or phase of the local signal clock to lock with the transmitter reference clock. Various embodiments may also include an outlier filter to remove error signals outside a defined range and/or a programmable system clock to add precision to the generated local system clock. | 07-12-2012 |
20120326795 | VCO CALIBRATION SCHEME - A technique to use a two-step calibration procedure to calibrate a voltage controlled oscillator (VCO) of a phase-locked loop. The first calibration step is an open-loop calibration procedure in which a control voltage of the VCO is temperature compensated and the VCO is tuned using a search routine to generate a corresponding output frequency based on the control voltage. The second step is a closed-loop calibration procedure to adjust the tuning components of the VCO to correct for a 1 LSB error. | 12-27-2012 |
20130120072 | SYSTEM AND METHOD OF CALIBRATING A PHASE-LOCKED LOOP WHILE MAINTAINING LOCK - A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current. | 05-16-2013 |
20130257546 | PHASE LOCKED LOOP WITH ADAPTIVE LOOP FILTER - A PLL including an adaptive loop filter. The PLL includes a feedback circuit which provides a feedback signal based on an output signal and a phase detector generating an adjust signal based on a frequency of the feedback signal compared with a reference frequency. A charge pump receives the adjust signal and provides a control voltage. The adaptive loop filter includes a capacitor and an adaptive resistance with a current control input. A VCO has an output providing the output signal based on a voltage level of the control voltage. A bias generator converts the control voltage to a loop bias current, and has a bias output based on the loop bias current coupled to the current control input of the adaptive resistance. The bias output of the bias generator may also be used to control the charge current and the VCO using currents proportional to the loop bias current. | 10-03-2013 |
20140104005 | VOLTAGE-TO-CURRENT CONVERTER AND VOLTAGE CONTROLLED OSCILLATOR HAVING VOLTAGE-TO-CURRENT CONVERTER - A voltage controlled oscillator includes a voltage-to-current converter and a current controlled oscillator, where the voltage-to-current converter is used for converting an input voltage to generate an output current, and the current controlled oscillator is used for generating an output frequency signal according to the output current. In addition, the voltage-to-current converter includes an input terminal, a resistor, a current mirror and a current generating circuit, where the input terminal is for receiving the input voltage; the resistor is coupled to the input terminal; the current mirror is coupled to the resistor, and is used for mirroring a reference current to generate a mirrored current, where the reference current is formed according to at least a current flowing through the resistor; and the current generating circuit is coupled to the current mirror, and is used for generating the output current according to at least the mirrored current. | 04-17-2014 |
20140184343 | PHASE LOCK LOOP, VOLTAGE CONTROLLED OSCILLATOR OF THE PHASE LOCK LOOP, AND METHOD OF OPERATING THE VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal. | 07-03-2014 |
20140218119 | COMMON REFERENCE CRYSTAL SYSTEMS - One embodiment of communication system comprises a crystal oscillator configured to output a reference clock; cellular radio frequency (RF) and baseband phase locked loops configured to receive the reference clock within a cellular module and compensate for calculated frequency errors between a received cellular downlink signal and a cellular local oscillator signal during operation of the cellular module; global positioning system (GPS) frequency compensation circuitry configured to receive the reference clock within a GPS module and compensate for calculated frequency errors during operation of the GPS module; and a temperature sensing circuit which includes a plurality of sensing resistors and is configured to output a signal corresponding to a temperature of a reference crystal which is translated to a frequency deviation, wherein the (GPS) frequency compensation circuitry is configured to offset the frequency deviation and output a temperate compensated signal to meet GPS clock frequency requirements. | 08-07-2014 |
20140266472 | TEMPERATURE COMPENSATED PLL CALIBRATION - In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control. | 09-18-2014 |
20140292417 | VOLTAGE-CONTROLLED OSCILLATOR MODULE AND PHASE-LOCKED LOOP DEVICE INCLUDING THE SAME - A voltage-controlled oscillator (VCO) module combines a low VCO-gain value with compensation for large frequency drifts. The VCO module comprises a VCO circuit and a time-integrator. The VCO circuit is fed with a first frequency tuning voltage and a second frequency tuning voltage which is produced by the time-integrator from the first frequency tuning voltage. In some embodiments, the time-integrator may be comprised of a transconductor connected in series with a capacitor, and the transconductor may have a linear operation range with low slope or zero-slope, located between two side ranges with deeper slope. | 10-02-2014 |
20150022272 | CLOSED LOOP DYNAMIC VOLTAGE AND FREQUENCY SCALING - A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling. | 01-22-2015 |
20150311902 | PLL WITH ACROSS-STAGE CONTROLLED DCO - In some embodiments, a PLL comprises an across-stage DCO controller and a DCO. The across-stage DCO controller comprises a first detector and a second tuning code adjustor. The first detector receives a first tuning code in a current stage in which an output frequency of the DCO is tuned by a first step size and generates a first detect signal which indicates whether the first tuning code exceeds a first range that the DCO can be correspondingly tuned in the current stage. The second tuning code adjustor adjusts a second tuning code from a previous stage in which the output frequency of the DCO is tuned by a second step size in response to the first detect signal. The second step size is larger than the first step size. The DCO generates the output frequency in response to codes comprising the adjusted second tuning code. | 10-29-2015 |
20150311906 | OSCILLATOR CROSSTALK COMPENSATION - Systems and methods for mitigating crosstalk between controlled oscillators of Phase-Locked Loops (PLLs) are disclosed. In one embodiment, a system includes a first PLL including a first controlled oscillator and a second PLL. The system further includes a compensation signal generator adapted to generate a compensation signal at an offset frequency that is approximately equal to an offset between output frequencies of the first and second PLLs and apply the compensation signal to the first controlled oscillator such that the output signal of the first controlled oscillator is modulated by the compensation signal. An amplitude and a phase of the compensation signal are such that, when the compensation signal is applied to the first controlled oscillator, a crosstalk signal output by the first controlled oscillator resulting from crosstalk from the second controlled oscillator of the second PLL to the first controlled oscillator of the first PLL is mitigated. | 10-29-2015 |
20160197617 | WIRELESS CHIPSET WITH A NON-TEMPERATURE COMPENSATED CRYSTAL REFERENCE | 07-07-2016 |
20160204786 | LOCAL OSCILLATOR | 07-14-2016 |