| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 331010000 | Plural A.F.S. for a single oscillator | 31 |
| 20080204150 | Method and System for a Fast-Switching Phase-Locked Loop Using a Direct Digital Frequency Synthesizer - Aspects of a method and system for a fast-switching Phase-Locked Loop using a Direct Digital Frequency synthesizer may include generating a second signal from a first signal by: frequency translating an inphase component of the first signal utilizing a filtered fast-switching oscillating signal generated using at least a direct digital frequency synthesizer (DDFS), and frequency translating a corresponding quadrature component of the first signal utilizing a phase-shifted version of the generated and filtered fast-switching oscillating signal. The inphase and quadrature components of the first signal may be multiplied with the filtered fast-switching oscillating signal and a phase-shifted version of the filtered fast-switching oscillating signal, respectively. The filtered fast-switching oscillating signal may be obtained by removing at least one frequency-sum term of the fast-switching oscillating signal, where the fast-switching signal oscillating signal may be generated from a signal generated by the DDFS that may be multiplied with an oscillating reference signal. | 08-28-2008 |
| 20080204151 | SYSTEMS AND TECHNIQUES FOR AUTO-CALIBRATION AND FAST TUNING OF VOLTAGE CONTROLLED OSCILLATORS IN PHASE-LOCK LOOPS - The present invention provides novel systems and techniques for the calibration and fast tuning of VCOs in PLLs. Information for coarse tuning before normal operation are calculated and stored. Therefore, these systems and techniques decrease significantly the time needed for a PLL to transition from one frequency to another. These techniques include the steps of: determining a digital code D | 08-28-2008 |
| 20080252383 | Phase locked loop and method for compensating temperature thereof - Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time. | 10-16-2008 |
| 20080284524 | Phase Locked Loop Circuit Having Regulator - Embodiments of present invention provide a circuit including a voltage regulator, a phase frequency detector, a charge pump, a low pass filter a control-voltage generating circuit and a voltage controlled oscillator. In a first mode of operation the voltage controlled oscillator produces an output clock in accordance with a control voltage produced from the control-voltage generating circuit and the output voltage of the voltage regulator. In a second mode of operation, the voltage controlled oscillator produces an output clock in accordance with a control voltage from the low pass filter and the output voltage of the voltage regulator. | 11-20-2008 |
| 20090002079 | CONTINUOUS GAIN COMPENSATION AND FAST BAND SELECTION IN A MULTI-STANDARD, MULTI-FREQUENCY SYNTHESIZER - A frequency synthesizer capable of high speed, low power, wideband operation including a method of gain compensation, and a method of fast voltage controlled oscillator (VCO) band calibration. In addition, the frequency synthesizer may include two or more switchable independent loop filters to facilitate wideband operation. Such a frequency synthesizer may be used in many applications, and in one example, may be particularly suitable for use in a multi-band, multi-standard transmitter or radio transceiver. | 01-01-2009 |
| 20090039967 | PHASED-LOCKED LOOP (PLL) SYNTHESIZER-SYNTHESIZER WITH IMPROVED VOLTAGE-CONTROLLED OSCILLATOR (VCO) PRE-TUNING - An apparatus for providing Phased-Locked Loop (PLL) synthesis comprises a phase detector, at least one switchable filter, an oscillator controlled by a control voltage (u | 02-12-2009 |
| 20090039968 | DUAL LOOP ARCHITECTURE USEFUL FOR A PROGRAMMABLE CLOCK SOURCE AND CLOCK MULTIPLIER APPLICATIONS - A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal. | 02-12-2009 |
| 20090102564 | METHOD AND APPARATUS FOR COMPENSATING FOR TUNING NONLINEARITY OF AN OSCILLATOR - Techniques to compensate for nonlinearity of a tuning function of an oscillator are described. The tuning nonlinearity of the oscillator may be modeled as a disturbance input to the oscillator and may be compensated with an equal but opposite disturbance. In one design, a nonlinearity correction signal to compensate for the tuning nonlinearity may be generated, e.g., based on a phase error signal in a phase-locked loop (PLL) and a scaling factor determined adaptively. The nonlinearity correction signal may compensate for the n-th (e.g., second) order tuning nonlinearity, and an n-th order (e.g., squared) modulating signal may be used to derive the scaling factor and the nonlinearity correction signal. A control signal for the oscillator may be generated based on the nonlinearity correction signal and possibly one or more other signals. The control signal may be applied to the oscillator to adjust the oscillation frequency of the oscillator. | 04-23-2009 |
| 20090146742 | PLL Apparatus - It is an object of the present invention to provide a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a trouble. | 06-11-2009 |
| 20090153252 | MULTI-BAND VOLTAGE CONTROLLED OSCILLATOR CONTROLLING MODULE, PHASE LOCKED LOOP UTILIZING WHICH AND RELATED METHOD THEREOF - A multi-band VCO module includes a multi-band VCO and a controlling module. The multi-band VCO is for selecting a specific band from a plurality of bands according to a band selecting signal, and for outputting an oscillating signal according to a predetermined voltage and the specific band. The controlling module, coupled to the multi-band VCO, is for setting the band selecting signal according to a reference frequency of the reference signal and an oscillating frequency of the oscillating signal. A related method and a PLL circuit utilizing the multi-band VCO module are also disclosed. | 06-18-2009 |
| 20090153253 | SYSTEM AND METHOD FOR REDUCING LOCK TIME IN A PHASE-LOCKED LOOP - Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop. | 06-18-2009 |
| 20090167443 | Digitally compensated highly stable holdover clock generation techniques using adaptive filtering - A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider. | 07-02-2009 |
| 20090231044 | VOLTAGE CONTROLLED OSCILLATOR HAVING TEMPERATURE DETECTING CIRCUIT - A VCO circuit includes a temperature detector circuit, a voltage generator circuit, a switch, a resonance circuit and an oscillator. The temperature detector detects a temperature, and the voltage generator circuit generates a voltage for coarse adjustment corresponding to the detected temperature and outputs the same voltage. The switch selects one of a DC voltage for fine adjustment and the voltage for coarse adjustment. The resonance circuit includes a varactor diode having a capacitance value adjusted based on the voltage selected by the switch, capacitors and an inductor, and has a predetermined resonance frequency. The oscillator generates an oscillation signal having an oscillation frequency corresponding to the resonance frequency by using the resonance circuit and outputs the same signal. | 09-17-2009 |
| 20090315628 | VARIANCE CORRECTION METHOD, PLL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A variance correction method includes generating a reference current depending on a resistance within a lowpass filter and outputting the reference current to a voltage controlled oscillator, and correcting characteristics of the lowpass filter and a gain of the voltage controlled oscillator based on an output clock of the voltage controlled oscillator. | 12-24-2009 |
| 20100052795 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention provides a semiconductor integrated circuit capable of reducing a chip occupied area and reducing variations in control gain of a digitally controlled oscillator. The semiconductor integrated circuit is equipped with the digitally controlled oscillator. The digitally controlled oscillator comprises oscillation transistors and a resonant circuit. The resonant circuit comprises inductances, a frequency coarse-tuning variable capacitor array and a frequency fine-tuning variable capacitor array. The frequency coarse-tuning variable capacitor array comprises a plurality of coarse-tuning capacitor unit cells. The frequency fine-tuning variable capacitor array comprises a plurality of fine-tuning capacitor unit cells. The capacitance values of the coarse-tuning capacitor unit cells of the frequency coarse-tuning variable capacitor array are set in accordance with a binary weight 2 | 03-04-2010 |
| 20100207693 | FREQUENCY SYNTHESIZER WITH MULTIPLE TUNING LOOPS - A frequency synthesizer with multiple tuning loops, e.g., a fine tuning loop and a coarse tuning loop, is described. The fine tuning loop may operate over a limited tuning range and may have fine frequency resolution. The coarse tuning loop may operate over a wide tuning range and may have coarse frequency resolution. The fine tuning loop may receive a reference signal at a reference frequency and generate a fine tuning signal at a first frequency adjustable in fine steps. The coarse tuning loop may receive the reference signal, generate an output signal at an output frequency, and generate a coarse tuning signal at a second frequency based on the output signal and the fine tuning signal. The second frequency may be adjustable in coarse steps, e.g., in integer multiples of the reference frequency. The output frequency may be determined based on the first frequency and the second frequency. | 08-19-2010 |
| 20100225402 | VCO TUNING WITH TEMPERATURE COMPENSATION - Techniques for setting a fine tuning input signal Vtune for a voltage-controlled oscillator (VCO) in a coarse tuning mode of the VCO. In an exemplary embodiment, the fine tuning input signal during coarse tuning mode is made temperature-dependent to account for possible variation of Vtune over temperature during fine tuning mode. Methods and apparatuses employing the techniques are further described. | 09-09-2010 |
| 20100237951 | FREQUENCY CALIBRATION OF RADIO FREQUENCY OSCILLATORS - A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF VCO fine frequency tuning signal is monitored continuously to determine if the control voltage is within specified limits. If the RF VCO fine frequency tuning voltage is too low or too high for the RF VCO to meet system requirements or lock on the current desired frequency, an interrupt signal is asserted. In response to the interrupt signal, a wireless communications processor or a hardware state machine initiates coarse frequency calibration of the RF VCO at the desired frequency. After coarse frequency calibration has completed, the RF VCO fine frequency tuning voltage is within specified limits and is continuously monitored. | 09-23-2010 |
| 20110025424 | PLL/FLL CIRCUIT WITH GAIN CONTROL - An FLL circuit having a capability of configuring a desired loop bandwidth in a short period of time is provided. An FDC | 02-03-2011 |
| 20110037523 | CHARGE PUMP LINEARIZATION FOR DELTA-SIGMA FRACTIONAL-N PHASE LOCKED LOOPS - A method and apparatus for linearizing a phase locked loop (PLL) are provided. To accomplish this, three separate signal (two feedback/one reference or two reference/one feedback) are applied to two phase/frequency detectors (PFDs). Either an edge of the one reference signal or one feedback signal is approximately equidistant between corresponding edges of the two feedback or two reference signals so that the PFDs can properly apply actuation signals to a charge pump that account for jitter. Thus, a more linear PLL is provided. | 02-17-2011 |
| 20110057731 | Feedback-Based Linearization of Voltage Controlled Oscillator - Embodiments of the present invention enable a feedback-based VCO linearization technique. Embodiments include a frequency locked loop formed by feeding back a VCO's output into the VCO's input in negative phase by means of a frequency-to-voltage (F/V) converter. Embodiments enable constant VCO gain over a wide input tuning range and across PVT variations. Further, embodiments can be nested within a PLL, for example, with negligible area and power consumption overhead. | 03-10-2011 |
| 20110163815 | METHOD AND SYSTEM FOR CALIBRATING A FREQUENCY SYNTHESIZER - A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain. | 07-07-2011 |
| 20110254632 | PLL FREQUENCY SYNTHESIZER - A voltage-controlled oscillator (VCO) includes an inductor, a fine-adjustment capacitor, and a coarse-adjustment capacitor, and generates an oscillation clock. A frequency divider divides the frequency of the oscillation clock to generate a divided clock. A direct current (DC) voltage supply circuit supplies a DC voltage to a control node, and changes a voltage value of the DC voltage according to a DC value of an oscillation voltage in a coarse-adjustment mode. A frequency-band selection circuit switches a capacitance value of the coarse-adjustment capacitor based on a frequency difference between a reference clock and the divided clock so that an oscillation frequency band of the VCO is set to an oscillation frequency band corresponding to a target frequency in the coarse-adjustment mode. An oscillation control circuit increases or decreases a control voltage according to a phase difference between the reference clock and the divided clock in the fine-adjustment mode. | 10-20-2011 |
| 331011000 | Plural comparators or discriminators | 8 |
| 20080284525 | Noise canceling technique for frequency synthesizer - A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes an input terminal and an output terminal, a loop filter, a digital phase detector, and an analog phase detector. The digital phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output coupled to the loop filter, the digital phase detector configured to operate at a first phase comparison frequency. The analog phase detector included a first input coupled to the input terminal, a second input coupled to the output terminal, and an output alternating current (AC) coupled to the loop filter, the analog phase detector configured to operate at a second phase comparison frequency. The first phase comparison frequency is different from the second phase comparison frequency. | 11-20-2008 |
| 20090079506 | PHASE-LOCKED LOOP AND METHOD WITH FREQUENCY CALIBRATION - A phase-locked loop including a phase-voltage conversion unit, a calibration unit, and an oscillation feedback unit is provided. The phase-voltage conversion unit receives a reference signal having a first frequency and a first phase, and a first feedback signal having a second frequency and a second phase, and produces a first adjusting signal based on the first frequency, the second frequency, and a phase difference between the first phase and the second phase. The calibration unit receives the reference signal and the first feedback signal, and produces a second adjusting signal based on a frequency difference between the first frequency and the second frequency through a binary search operation. The oscillation feedback unit receives the first adjusting signal and the second adjusting signal, and has a controllable capacitor array controlled by the second adjusting signal for producing a second feedback signal having a third phase locked to the first phase. | 03-26-2009 |
| 20090140816 | SYNTHESIZER CHARACTERIZATION IN REAL TIME - A frequency synthesizer includes a phase locked loop (PLL) for generating a desired frequency. The PLL includes two loop filters. A characterization circuit is included, which is configured to receive a digital word for characterizing the PLL and provide a pre-charge value for pre-charging one of the loop filters to generate the desired frequency. A successive approximation analog to digital (A/D) converter is coupled between the loop filters and the characterization circuit, for providing both (a) the digital word to the characterization circuit, and (b) the pre-charge value to the selected loop filter. The digital word includes n-bits ranging in values from a most significant bit (MSB) to a least significant bit (LSB), and the pre-charge value is formed by the n-bits. The successive approximation A/D converter includes a successive approximation register (SAR) for forming the digital word, and a digital to analog (D/A) converter for forming the pre-charge value. The successive approximation A/D converter includes a comparator for comparing (a) a value corresponding to a loop filter voltage with (b) an analog value formed by a bit of the digital word. | 06-04-2009 |
| 20100315169 | PLL DISTURBANCE CANCELLATION - Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output. | 12-16-2010 |
| 20110012683 | METHOD AND APPARATUS OF PHASE LOCKING FOR REDUCING CLOCK JITTER DUE TO CHARGE LEAKAGE - a phase lock loop is disclosed, the phase lock loop comprising: a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal. | 01-20-2011 |
| 20130271227 | SELF-BIASED OSCILLATOR - Described herein is a self-biased oscillator. The self-biased oscillator comprises a first differentiator with adjustable resistance or capacitance, the first differentiator having an output node and an input node; and a second differentiator with adjustable resistance or capacitance, the second differentiator having an input node coupled to the output node of the first differentiator, and having an output node coupled to the input node of the first differentiator. | 10-17-2013 |
| 20130285752 | Reference-Less Frequency Detector - Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal. | 10-31-2013 |
| 331012000 | With phase-shifted inputs | 1 |
| 20080272850 | Lock Detector and Optical Phase Locked-Loop System - A lock detection apparatus detecting lock of an optical phase-locked loop apparatus including a first phase detector comparing phases of an input light signal and a beat light signal to output a first phase comparison signal, a loop filter forming the first phase comparison signal, and an optical voltage controlled oscillator outputting the beat light signal based on the formed first phase comparison signal. The lock detection apparatus includes: a phase shifter shifting the phase of the beat light signal; and a second phase detector comparing the phases of the input light signal and the phase-shifted beat light signal to output a second phase comparison signal, wherein the phase shifter shifts a quantity of the phase so that the phase comparison signal may not be 0 when the phases of the two light signals compared by the second phase detector synchronize with each other to the beat light signal. | 11-06-2008 |
