| Entries |
| Document | Title | Date |
|---|
| 20080197929 | Resonant Types Of Common-Source/Common-Emitter Struture For High Gain Amplification - Radio frequency/millimeter wave integrated circuits (RF/MMICs) that employ a resonance mechanism between an input stage and a transistor are disclosed. The circuits contain an input stage, a transistor; and a transformer connected between either a gate or a base of the transistor and a voltage supply of the input stage. The methods disclosed maximize either a collector current or a drain current of a transistor by placing a transformer between the transistor and a voltage source. | 08-21-2008 |
| 20080204140 | Compound semiconductor device and doherty amplifier using compound semiconductor device - A lower electron supply layer is disposed over a lower electron transport layer made of compound semiconductor. The lower electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the lower electron transport layer. An upper electron transport layer is disposed over the lower electron supply layer. The upper electron transport layer is made of compound semiconductor having a doping concentration lower than that of the lower electron supply layer or non-doped compound semiconductor. An upper electron supply layer is disposed over the upper electron transport layer. The upper electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the upper electron transport layer. A source and drain electrodes are disposed over the upper electron supply layer. A gate electrode is disposed over the upper electron supply layer between the source and drain electrodes. | 08-28-2008 |
| 20080204141 | Radio-Frequency Amplifier System - A device for measuring voltage levels includes a root mean square (RMS) detector. The RMS detector includes a linear multiplier, a log converter, a low-pass filter and a temperature compensator. The linear multiplier multiplies a voltage of an input signal by the voltage of the input signal. The low-pass filter couples to an output of the linear multiplier. The log converter generates a logarithmic signal having a voltage that is logarithmically related to a voltage of an output of the low-pass filter. The temperature compensator adjusts the logarithmic signal based on a temperature of the RMS detector. The RMS detector is capable of determine an RMS voltage level of the input signal. | 08-28-2008 |
| 20080224778 | Transmission line amplifier - A transmission line amplifier utilizes a transmission line transistor having a gate line, and first and second lines. The gate line is a gate of the transistor, one of the first and second lines is a source of the transistor, and the other is a drain of the transistor. The gate line includes an input terminal at a first end thereof, adapted to receive an input signal, and a gate line load terminal at a second end thereof, adapted to be connected to a gate line load. The second line is connected to a first supply voltage. The first line includes a first line load terminal at a first end thereof that is adapted to be connected to a first line load, and an output terminal at a second end thereof that is adapted to provide an output signal. | 09-18-2008 |
| 20080231367 | Amplifier - An amplifier according to the present invention includes an amplifying transistor, and an impedance converter circuit coupled to an output unit of the amplifying transistor and including a plurality of impedance converting transistors different in input impedance, which are series-connected. | 09-25-2008 |
| 20080231368 | WIRELESS FREQUENCY POWER AMPLIFIER, SEMICONDUCTOR DEVICE, AND WIRELESS FREQUENCY POWER AMPLIFICATION METHOD - A differential amplifier circuit is connected to the input node and the output node of the final amplification stage through detection circuits. The signal level difference output from the differential amplifier circuit does not change even if the input power varies. Because a change in the power gain at the output node does not travel back to the input node when the load impedance of the wireless frequency power amplifier varies, it is possible to detect only the change in the load impedance. Damage to the final stage can be prevented by controlling the operating current of the final stage and the gain of the drive stage according to the detected load variation. Nonlinear distortion in the wireless frequency power amplifier output can also be reduced by detecting and canceling the change in the gain of the drive stage by changing the gain of the adjustment stage. | 09-25-2008 |
| 20080238550 | POWER AMPLIFIER AND TRANSMISSION AND RECEPTION SYSTEM - A power amplifier includes: a first multi-finger FET formed on a semiconductor substrate; a second multi-finger FET formed on the semiconductor substrate; a first temperature detector which detects a channel temperature of the first FET; a second temperature detector which detects a channel temperature of the second FET; a third temperature detector which detects a temperature of the semiconductor substrate; a first detection circuit detecting a difference between an output of the first temperature detector and an output of the third temperature detector and converting the difference to thermoelectromotive force; a second detection circuit detecting a difference between an output of the second temperature detector and the output of the third temperature detector and converting the difference to thermoelectromotive force; and a comparator comparing outputs of the first and second detection circuits with each other to turn on one of the first and second switches and turn off the other. | 10-02-2008 |
| 20080238551 | AMPLIFIER CIRCUIT - An amplifier circuit for amplifying a high-frequency input signal comprises an amplifier stage, which amplifies the high-frequency input signal as a function of an operating point of the amplifier stage and generates an operating point-dependent signal, an observer stage, which replicates the amplifier stage and generates an observation signal, a regulator, which is supplied with the operating point-dependent signal and the observation signal, and an control element, which influences the operating point of the amplifier stage and is driven by the regulator, whereby the regulator drives the control element in such a way that the operating point of the amplifier stage is substantially independent of a level of the high-frequency input signal. | 10-02-2008 |
| 20080252376 | METAL-OXIDE-SEMICONDUCTOR CIRCUIT DESIGNS AND METHODS FOR OPERATING SAME - Complimentary Metal-Oxide-Semiconductor (CMOS) circuits made with core transistors are capable of reliable operation from an IO power supply with voltage that exceeds the reliability limit of the transistors. In embodiments, biasing of an operational amplifier is changed in part to a fixed voltage corresponding to the reliability limit. In embodiments, switched capacitor networks are made with one or more amplifiers and switches including core transistors, but without exposing the core transistors to voltages in excess of their reliability limit. In embodiments, operational transconductance amplifiers (OTAs) include core transistors and operate from IO power supplies. Level shifters for shifting the levels of a power down signal may be used to avoid excessive voltage stress of the OTAs' core transistors during turn-off. Non-level shifting means may be used to clamp output voltages and selected internal voltages of the OTAs, also avoiding excessive voltage stress of the core transistors during turn-off. | 10-16-2008 |
| 20080258815 | HIGH FREQUENCY POWER AMPLIFIER AND WIRELESS PORTABLE TERMINAL USING THE SAME - An object is to provide a high frequency power amplifier in which lowering of output power during operation is prevented, influence of thermal noise is suppressed, high frequency operation is stable, and long-term reliability is ensured. The high frequency power amplifier includes a plurality of transistors having gate electrodes, source regions and drain regions, the gate electrodes, source regions and drain regions being respectively connected in common, and a plurality of acoustic reflection layers being buried in portions of the semiconductor substrate, the portions being located between adjacent transistors, the acoustic reflection layers being disposed in a direction which is oblique to a length direction of the gate electrode. | 10-23-2008 |
| 20080258816 | LOW FREQUENCY ANALOG CIRCUIT AND DESIGN METHOD THEREOF - A low frequency analog circuit and a method for designing the same are provided. In a low frequency analog circuit according to the present invention, a part of MOS transistors employed in the circuit are operated at a weak inversion region. | 10-23-2008 |
| 20080284516 | Monolithic Lna Support Ic - A low noise amplifier (LNA) comprises: a plurality of FETs (F | 11-20-2008 |
| 20080290946 | Semiconductor integrated circuit device - To save power consumption in a semiconductor integrated circuit | 11-27-2008 |
| 20080297255 | Receiver Comprising an Amplifier - The invention relates to a receiver ( | 12-04-2008 |
| 20080303593 | MUGFET CIRCUIT FOR INCREASING OUTPUT RESISTANCE - In an embodiment, an apparatus includes a MuGFET device coupled to a reference source, the MuGFET device configured to receive an input signal at a gate thereof; and Also includes a further MuGFET device coupled between the MuGFET device and a first terminal of a load, a second terminal of the load coupled to a further reference source, the further MuGFET device configured to receive a further input signal at a gate thereof, and wherein the MuGFET device and the further MuGFET device are disposed above a substrate and configured to provide an output signal at the first terminal of the load. | 12-11-2008 |
| 20080303594 | Amplifier Circuit - There is provided an amplifier circuit including a plurality of unit amplifiers connected in parallel to an input signal terminal, wherein each of the unit amplifiers includes: a first switch switching an input signal inputted from the input signal terminal; a first field effect transistor having a gate connected to the input signal terminal via the first switch and amplifying the input signal of the input signal terminal to output the amplified input signal; a second switch connected in parallel to the first switch and switching the input signal of the input signal terminal at a complementary timing to a switching timing of the first switch; and a capacitor connected to the input signal terminal via the second switch. | 12-11-2008 |
| 20080303595 | AMPLIFYING CIRCUIT - An amplifier includes: a class AB input stage, receiving an input signal, for generating an inner signal according to the input signal; class AB output stage, includes: a biasing circuit, for providing a first voltage and a second voltage according to the inner signal; and an output stage, for generating an output signal according to the first voltage and the second voltage; wherein a voltage difference between the first voltage and the second voltage generated by the biasing circuit is corresponding to the input signal. | 12-11-2008 |
| 20080309412 | ORGANIC FIELD EFFECT TRANSISTOR SYSTEMS AND METHODS - An OFET includes a ferroelectric gate dielectric permitting electrical reprogramming, such as to implement an electrically re-programmable array logic (PAL) or a field-programmable gate array (FPGA). Methods of constructing such an OFET, PAL, or FPGA, can including roll printing. An OFET on a piezoelectric substrate provides local amplification in an active matrix. Methods of constructing such an OFET on a piezoelectric substrate can including rolling printing. Techniques permit direct measurement of trap distribution, such as across the channel length of an OFET device. Techniques permit direct measurement of the size and location of an electrically active grain structure in OFET devices. Techniques permit confirmation of the mechanism of operation of a number of OFET techniques, including use of silanes or thiols, or OFET operation or aging. Techniques provide an internal circuit probe, such as for a ferroelectric gate dielectric OFET or a piezoelectric substrate OFET, for example. | 12-18-2008 |
| 20080315952 | POWER AMPLIFIER SYSTEM PROVIDED WITH IMPROVED PROTECTION FUNCTION - A power amplifier system including a power terminal, a ground terminal, an output terminal, a ripple terminal, a control terminal to which a control signal is supplied from outside, a power amplifier circuit connected between the power terminal and the ground terminal, a negative potential detection circuit connected to the output terminal, and a bias circuit which supplies a bias voltage to the power amplifier circuit, and a bias start-up circuit controlling the startup operation of the bias circuit. | 12-25-2008 |
| 20090002072 | POWER AMPLIFICATION DEVICE - A power amplification device includes a BTL amplification circuit including a first amplification circuit and a second amplification circuit, the first amplification circuit including a first output transistor, a first power detection circuit, a second output transistor, and a second power detection circuit, the second amplification circuit including a third output transistor, a third power detection circuit, a fourth output transistor, and a fourth power detection circuit, a first comparator which compares output values of the first and fourth power detection circuits, and a second comparator which compares output values of the second and third power detection circuits. | 01-01-2009 |
| 20090009250 | Low Noise Amplifier - For a first transistor, a source thereof is coupled to an input terminal and a drain thereof is coupled to an output terminal. A first variable impedance circuit is arranged between a gate of the first transistor and ground, and the impedance thereof is changed according to a first control signal. A second variable impedance circuit is arranged between the gate and the source of the first transistor, and the impedance thereof is changed according to a second control signal. Furthermore, an impedance circuit is arranged between the gate of the first transistor and a power supply. The ratio of the impedances of the first and second variable impedance circuits can be set to an arbitrary value according to the first and second control signals in order to change the gain of the low noise amplifier. As the result, the generation of unwanted thermal noise can be prevented. | 01-08-2009 |
| 20090015333 | POWER AMPLIFIER MODULE AND A TIME DIVISION MULTIPLE ACCESS RADIO - A power amplifier module comprises a power amplifier circuit having an output power level controlled by a power supply voltage. A power supply transistor controls the power supply to the power amplifier circuit from a drive signal which is received from a drive circuit. The drive circuit generates the drive signal in response to a power level input signal, which specifically may correspond to a power ramping for a GSM cellular communication system. The power amplifier module furthermore comprises a detection circuit which determines an operating characteristic of the power supply transistor. The operating characteristic is preferably a saturation characteristic. A control circuit controls the drive signal in response to the operating characteristic. The control circuit preferably controls the drive signal such that the power supply transistor does not enter the linear region for a Field Effect Transistor and the saturated region for a bipolar transistor. | 01-15-2009 |
| 20090015334 | Bypass Circuit for Radio-Frequency Amplifier Stages - An amplifier circuit includes an amplifier and a phase shifter coupled in parallel to the amplifier and switchable such that the phase shifter has a first impedance for an alternating signal in an on state and has a second impedance for the alternating signal in an off state. The second impedance is higher than the first impedance. | 01-15-2009 |
| 20090021307 | MULTI-BAND, INDUCTOR RE-USE LOW NOISE AMPLIFIER - Described herein are multi-band LNAs that reuse inductors for different frequency bands to minimize chip area. In an embodiment, a multi-band LNA is capable of operating in a narrowband (NB) and a wideband (WB) while reusing at least one input impedance matching inductor and at least one load inductor for both bands. The reuse of inductors results in a more efficient use of chip area. In an exemplary embodiment, the LNA comprises a common source transistor and a common gate transistor. In this embodiment, the LNA operates in a common source configuration using the common source transistor to amplify input signals in the NB, and operates in a common gate configuration using the common gate transistor to amplify input signals in the WB. The LNA reuses an input impedance matching inductor and a load inductor in both configurations, and thus both bands. | 01-22-2009 |
| 20090051435 | RF AMPLIFIER WITH STACKED TRANSISTORS, TRANSMITTING DEVICE, AND METHOD THEREFOR - An RF transmitting device ( | 02-26-2009 |
| 20090051436 | METHOD AND SYSTEM FOR FET-BASED AMPLIFIER CIRCUITS - Amplifier circuits and methods are implemented using a variety of different embodiments. According to one such embodiment, a method is implemented using a field-effect transistor (FET) having a gate node, a source node and a drain node. A first circuit state is implemented in which the gate node, the source node and the drain node are connected to inputs that generate a stored a charge at the gate node, the amount of stored charge at the gate node being responsive to a first voltage level. A second circuit state is implemented in which the drain node is connected to a voltage source, the source node is connected to a load, and while charge at the gate node is preserved, current between the drain node to the source node drives a voltage level of the load to a proportionally amplified version of the first voltage level. | 02-26-2009 |
| 20090058530 | HIGH-VOLTAGE TRANSCONDUCTANCE CIRCUIT - The invention is a high-power transconductance circuit (HVTC) comprising three direct-coupled stages which can be substituted for a final-stage power-amplifying vacuum tube in an audio amplifier. The HVTC consists of an input stage, a driver stage, an output stage, and a power conditioner. The input to the HVTC is a composite signal consisting of an AC component and a DC component. The input stage conditions the input composite signal for input to the driver stage. The driver stage transforms the input composite signal into the driving signal for the output stage. The output stage utilizes one or more power transistors to drive a load. The power conditioner supplies regulated power to the HVTC. The input composite signal is direct-coupled through the input stage and the driver stage to the output stage. | 03-05-2009 |
| 20090066418 | AMPLIFIER CIRCUIT AND COMMUNICATION DEVICE - There is provided an amplifier circuit having a common-source amplifier, an output load connected to an output terminal of the common-source amplifier, a buffer circuit connected to the output terminal of the common-source amplifier, a feedback circuit connected between an output terminal of the buffer circuit and an input terminal of the common-source amplifier, and a control circuit for controlling an impedance of the feedback circuit in accordance with a gain of the common-source amplifier. | 03-12-2009 |
| 20090072906 | HIGH FREQUENCY POWER AMPLIFIER CIRCUIT AND ELECTRONIC COMPONENT FOR HIGH FREQUENCY POWER AMPLIFIER - In a high frequency power amplifier circuit that supplies a bias to an amplifying FET by a current mirror method, scattering of a threshold voltage Vth due to the scattering of the channel impurity concentration of the FET, and a shift of a bias point caused by the scattering of the threshold voltage Vth and a channel length modulation coefficient λ due to a short channel effect are corrected automatically. The scattering of a high frequency power amplifying characteristic can be reduced as a result. | 03-19-2009 |
| 20090072907 | ELECTRIC CIRCUIT - As for a transistor, overlapped are factors such as a variation of a gate insulation film which occurs due to a difference of a manufacturing process and a substrate used and a variation of a crystalline state in a channel forming region and thereby, there occurs a variation of a threshold voltage and mobility of a transistor. | 03-19-2009 |
| 20090085664 | POWER AMPLIFIER HAVING AN ADAPTIVE AMPLIFYING MECHANISM - By making use of two common-source amplifying units having a shared DC bias in conjunction with two current units or an extra amplifying unit, a power amplifier is capable of providing a high output power in a high power-gain operation and achieving a low power biasing consumption in a low power-gain operation. The two current units are utilized to provide auxiliary bias currents for diverting part of two bias currents corresponding to the shared DC bias for the two amplifying units so that the output power can be boosted in the high power-gain operation. Also, the extra amplifying unit can be coupled in series with the two amplifying units for improving the output power of the power amplifier in the high power-gain operation. The shared DC bias provides same bias current to the two amplifying units for achieving the low power biasing consumption in the low power-gain operation. | 04-02-2009 |
| 20090085665 | VARIABLE GAIN AMPLIFYING DEVICE - A variable gain amplifying device that amplifies an input signal and outputs the amplified signal, has a controlling circuit that controls the gain by controlling turning on and off of first MOS transistors and third MOS transistors so that the sum of the number of first MOS transistors turned on and the number of third MOS transistors turned on is “n” by outputting a control signal to the gates of the first MOS transistors and the third MOS transistors. | 04-02-2009 |
| 20090091390 | Programmable-gain amplifier systems to facilitate low-noise, low-distortion volume control - Programmable-gain amplifier systems are provided that are particularly suited for reducing degrading audio effects such as zipper noise. In one embodiment, these systems switchably couple an electronic potentiometer between an amplifier's inverting input terminal and interleaved tap points along a resistor that is coupled to the amplifier's output terminal. This arrangement introduces a number of fine gain steps between the gain steps that are realized with adjacent ones of the interleaved tap points to substantially reduce or eliminate zipper noise in a audio system that processes the system's output signal. The interleaved tap points facilitate efficient operation of the potentiometer during gain changes. They also permit the potentiometer to be effectively bypassed between gain changes so that distortion effects are substantially eliminated. | 04-09-2009 |
| 20090096525 | Power amplifier - Methods to implement power control in a digital power amplifier are described. | 04-16-2009 |
| 20090096526 | CASCODED CIRCUIT - A cascoded current-mirror circuit includes a first N channel MOS transistor, a second N channel MOS transistor, a third N channel MOS transistor and a fourth N channel MOS transistor. The first N channel MOS transistor and the second N channel MOS transistor are cascode-connected between a higher voltage source and a lower voltage source. The third N channel MOS transistor and the fourth N channel MOS transistor are cascode-connected between the higher voltage source and the lower voltage source. A drain of the first N channel MOS transistor is connected to gates of the first N channel MOS transistor, the second N channel MOS transistor, the third N channel MOS transistor and the fourth N channel MOS transistor. The threshold voltages of the second N channel MOS transistor and the fourth N channel MOS transistor are larger than those of the first N channel MOS transistor and the third N channel MOS transistor. | 04-16-2009 |
| 20090096527 | AUTOMATIC GAIN CONTROL CIRCUIT AND LOW NOISE AMPLIFYING CIRCUIT - By connecting an antenna damping circuit ( | 04-16-2009 |
| 20090102562 | CROSS-COUPLED LOW NOISE AMPLIFIER FOR CELLULAR APPLICATIONS - Cross-coupled low noise amplifier for cellular applications. A circuitry implementation that includes two pairs of metal oxide semiconductor field-effect transistors (MOSFETs) (either N-type of P-type) operates as an LNA, which can be used within any of a wide variety of communication devices. In one embodiment, this design is particularly adaptable to cellular telephone applications. A majority of the elements are integrated within the design and need not be implemented off-chip, and this can provide for a reduction in area required by the circuitry. A very high output impedance is provided by using two transistors (implemented in a triple well configuration) with resistive source degeneration. A higher than typical power supply voltage can be employed (if desired) to accommodate the voltage drops of the resistors and transistors. | 04-23-2009 |
| 20090108939 | AMPLIFYING APPARATUS AND BIAS STABILIZATION CIRCUIT - An amplifying apparatus including an amplifier having a first FET, a second FET having a source connected to a drain of the first FET, a load resistance connected to a drain of the second FET, a first bias circuit configured to supply a first bias voltage to a gate of the first FET, and a second bias circuit configured to supply a second bias voltage to a gate of the second FET. The second bias circuit includes a second comparison circuit configured to send a control signal to the gate of the second FET so that a bias voltage of a connection node between the first and second FETs changes in conjunction with an output voltage of the first bias circuit. | 04-30-2009 |
| 20090115525 | FREQUENCY TUNABLE LOW NOISE AMPLIFIER - A frequency tunable low noise amplifier | 05-07-2009 |
| 20090115526 | FET BIAS CIRCUIT - A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class. | 05-07-2009 |
| 20090115527 | OUTPUT STAGE CIRCUIT AND OPERATIONAL AMPLIFIER THEREOF - The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, there is no need extra frequency compensating component for compensating the transistor of the output stage circuit, and to save circuit layout area and cost can be achieved by the present invention. | 05-07-2009 |
| 20090140812 | HIGH-LINEARITY COMPLEMENTARY AMPLIFIER - A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages. | 06-04-2009 |
| 20090174480 | Systems and Methods for Cascode Switching Power Amplifiers - Example embodiments of the invention may provide systems and methods for a power amplifier. The systems and methods may include a first common-source device having a first source, a first gate, a first drain, and a first body, where the first source is connected to the first body, and wherein the first gate is connected to an input port. The systems and methods may further include a second common-gate device having a second source, a second gate, a second drain, and a second body, where the second source is connected to the first drain, where the second source is further connected to the second body, and where the second drain is connected to an output port. | 07-09-2009 |
| 20090174481 | MULTI-LINEARITY MODE LNA HAVING A DEBOOST CURRENT PATH - A modified derivative superposition (MDS) low noise amplifier (LNA) includes a main current path and a cancel current path. Third-order distortion in the cancel path is used to cancel third-order distortion in the main path. In one novel aspect, there is a separate source degeneration inductor for each of the two current paths, thereby facilitating tuning of one current path without affecting the other current path. In a second novel aspect, a deboost current path is provided that does not pass through the LNA load. The deboost current allows negative feedback to be increased without generating headroom problems. In a third novel aspect, the cancel current path and/or deboost current path is programmably disabled to reduce power consumption and improve noise figure in operational modes that do not require high linearity. | 07-09-2009 |
| 20090174482 | HIGH POWER INTEGRATED RF AMPLIFIER - An integrated HF-amplifÊer structure comprises in a first direction (FD) in the order mentioned: an input bond pad (IBP), a plurality of cells (CE | 07-09-2009 |
| 20090179702 | DOHERTY AMPLIFIER - An integrated Doherty amplifier structure comprises an input bond pad (IBP), and an output bond pad (OBP). A first transistor (T | 07-16-2009 |
| 20090179703 | HIGH EFFICIENCY POWER AMPLIFIER - Disclosed a power amplifier including a main amplifier with class bias AB and a peak amplifier with class C bias. A quarter-wave length transmission line having a length equal to one-fourth of the wave-length of a fundamental frequency is connected to an output side of the peak amplifier. Outputs of the main amplifier and the peak amplifier are combined. An envelope amplifier that modulates the drain bias voltage in accordance with an envelope of the modulation wave input signal and an envelope detector are provided as a drain-bias circuit for the main amplifier (FIG. | 07-16-2009 |
| 20090195314 | DEVICE AND METHOD FOR AMPLIFYING PULSED RF SIGNALS - Device and method are described for amplifying pulsed RF signals, comprising one or more transistors, each comprising a drain, a gate and a source. A device synchronizes the supply for the drain with an RF pulse. | 08-06-2009 |
| 20090195315 | SAMPLE-AND-HOLD AMPLIFIERS - A sample-and-hold amplifier is provided. The sample-and-hold amplifier comprises a sample-and-hold circuit and a buffer circuit. The sample-and-hold circuit receives an input signal and transmits the input signal to a first node according to a control signal. The buffer circuit is coupled between a supply voltage source and a ground and controlled by the first node to provide an output signal at an output node. The buffer circuit comprises a native MOS transistor coupled to the output node. | 08-06-2009 |
| 20090195316 | RE-CONFIGURABLE LOW NOISE AMPLIFIER UTILIZING FEEDBACK CAPACITORS - A re-configurable low noise amplifier utilizing feedback capacitors is disclosed. The low noise amplifier has output transistors, capacitor switch cells, and capacitance distributors all in an output terminal. The output transistors are for controlling selection of a specific frequency band in a wide band of frequencies. The capacitor switch cells are for adjusting a harmonic frequency for the specific frequency band. The capacitance distributor is for determining an amount of gain, and according to the gain, an output impedance feeds back to an input terminal of the low noise amplifier for input matching. Since the output terminal is at high impedance and suitable for a wide band of frequencies, input matching not only makes the low noise amplifier applicable to kinds of wireless communication standards, but also fulfills high gain and low noise figure. | 08-06-2009 |
| 20090201088 | Measuring Load Impedance Of An Amplifier Driving A Variable Load - According to an aspect of the present invention, the magnitude and phase angle of looking-in impedance driven by an amplifier are computed in digital domain during normal operation within a module containing the amplifier. In an embodiment, the computed magnitude and phase angle are used for impedance matching at a node driven by the amplifier. As a result, impedance matching may be obtained even in situations when the impedance changes during operation. | 08-13-2009 |
| 20090201089 | High frequency power amplifier - A high frequency power amplifier includes an amplifying device for amplifying an input high frequency signal, a harmonic reflection circuit for reflecting a harmonic outputted from the amplifying device, and a harmonic generating circuit provided at an input terminal of the amplifying device, the harmonic generating circuit including a divider for dividing an input signal of a fundamental wave into two parts, a harmonic generator for generating a second harmonic from one part of the fundamental wave signal, and a combiner for combining the second harmonic generated from the harmonic generator with the other part of the fundamental wave signal to offer a combined signal to the amplifying device, wherein the harmonic reflection circuit reflects the second harmonic. | 08-13-2009 |
| 20090237165 | Cross-coupled low noise amplifier for cellular applications - Cross-coupled low noise amplifier for cellular applications. A circuitry implementation that includes two pairs of metal oxide semiconductor field-effect transistors (MOSFETs) (either N-type of P-type) operates as an LNA, which can be used within any of a wide variety of communication devices. In one embodiment, this design is particularly adaptable to cellular telephone applications. A majority of the elements are integrated within the design and need not be implemented off-chip, and this can provide for a reduction in area required by the circuitry. A very high output impedance is provided by using two transistors (implemented in a triple well configuration) with resistive source degeneration. A higher than typical power supply voltage can be employed (if desired) to accommodate the voltage drops of the resistors and transistors. | 09-24-2009 |
| 20090243725 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor unit including first field effect transistors with first gate electrodes electrically connected together, first sources electrically connected together, and first drains electrically connected together, the first gate electrodes being electrically connected to the first drains, a second transistor unit including second field effect transistors with second gate electrodes electrically connected together, second sources electrically connected together, and second drains electrically connected together, the second gate electrodes being electrically connected to the first gate electrodes, and dummy gate electrodes electrically isolated from the first gate electrodes and the second gate electrodes. The first gate electrodes, the second gate electrodes, and the dummy gate electrodes are arranged parallel to one another, and at least one dummy gate electrode is located between any one of the first gate electrodes and any one of the second gate electrodes. | 10-01-2009 |
| 20090267696 | HIGH SLEW RATE AMPLIFIER, ANALOG-TO-DIGITAL CONVERTER USING SAME, CMOS IMAGER USING THE ANALOG-TO-DIGITAL CONVERTER AND RELATED METHODS - An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one compensation capacitor is coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage. The slew rate of the amplifier is enhanced by substantially reducing the negative feedback coupled through the capacitor during a period following the transition of a signal applied to an input terminal of the amplifier. If the first stage of the amplifier has complementary signal nodes, the negative feedback coupled through the capacitor may be reduced, for example, by closing a switch coupled between first and second complementary nodes of the first amplifier stage. | 10-29-2009 |
| 20090278605 | METHOD FOR IMPLEMENTATION AND PARAMETER SETTINGS OF A VOLTAGE ENHANCEMENT CIRCUIT FOR AMPLIFIERS AS AN INTEGRATED CIRCUIT (IC) - Voltage Enhancement Circuitry (VEC) for amplifiers, suitable of being implemented as an Integrated Circuit (IC), that comprises a VEC driver with a low output resistance (Rdson) while being in its inactive mode and a linearly increasing resistance that is changing linearly with the input control signal, while entering into its active mode, above a determined threshold; external contacts in the VEC, for connecting, whenever required, external feedback elements across the contacts; an external feedback loop connected to an input of the VEC driver, for sensing changes in the enhancement power; a threshold programming module, for externally programming and determining a threshold level for the input signal, above which enhancement is provided shaping the amplified video envelope pulse; an I-Boost module for sampling the amplitude of the video envelope input current and for amplifying the input current up to a pre-defined level; and a current controlled bias circuit for shifting, whenever required, the bias of the lower and/or of the upper valves of the VEC driver. | 11-12-2009 |
| 20090289717 | RADIO FREQUENCY (RF) POWER AMPLIFIER AND RF POWER AMPLIFIER APPARATUS - An RF power amplifier has a final-stage amplifier stage which generates an RF transmit output signal, a signal detector which detects an RF transmit output level, a first detector, a second detector and a control circuit. The final-stage amplifier stage includes a transistor and a load element and performs saturation type nonlinear amplification and non-saturation type linear amplification. The first detector and the control circuit maintain the RF transmit output signal approximately constant with respect to a variation in load at an antenna at the saturation type nonlinear amplification. The second detector and the control circuit reduce an increase in the output voltage of the final stage transistor with respect to an overload state of the antenna at the non-saturation type linear amplification. | 11-26-2009 |
| 20090295483 | RF Power Amplifiers with Linearization - Designs and techniques associated with power amplifiers for amplifying RF signals to provide variable power amplification and improved linearity in various RF amplification circuits, including power amplifiers operated under the power back-off conditions. | 12-03-2009 |
| 20090295484 | Low Bias Current Amplifier - An amplifier is provided that includes an output portion that sources and sinks current associated with an output load and an amplification portion that is biased by a relatively small bias current with respect to an output current of the amplifier. The amplification portion provides an amplified output signal to the output portion. The amplifier further comprises at least one impedance component coupled between the output portion and the amplification portion to alter at least one pole associated with the amplifier to mitigate instability of the amplifier related to the relatively small bias current. | 12-03-2009 |
| 20090309659 | Solid-state ultra-wideband microwave power amplifier employing modular non-uniform distributed amplifier elements - A number of identical non-uniformly distributed ultra-wideband power amplifier string building blocks are coupled together to form an ultra-wide bandwidth high-power amplifier. The non-uniform distribution results in an amplifier utilizing modular string building blocks that have input and output impedances with only real values. This permits the strings to be replicated and connected together with simple impedance matching. The internal impedance matching associated with the non-linear distribution also absorbs parasitic capacitance to permit the ultra-broadband operation. In one embodiment identical transistors are used for each cell so that the strings may be identically replicated. This permits modular re-use without reconfiguration. In one embodiment a non-uniform distributed power amplifier built using the subject building blocks provides an ultra-wideband multi-octave device suitable for electronic warfare and communications applications, especially to replace traveling wave tubes. | 12-17-2009 |
| 20090309660 | DEVICE FOR AMPLIFYING A BROADBAND RF SIGNAL - The present invention relates to a microwave signal amplification device comprising a cascode cell ( | 12-17-2009 |
| 20100013559 | High frequency amplifying device - An amplifying device includes a base plate and an integrated circuit (IC) package mounted on the base plate. The IC package includes a radio frequency (RF) output terminal and a power switching metal-oxide-semiconductor field-effect transistor (MOSFET) die mounted on the RF output terminal. The amplifying device also includes impedance matching circuitry coupled to the power switching MOSFET and the RF output terminal and an insulator substrate mounted on the base plate having thermal conductivity to provide electrical isolation and thermal transfer from the RF output terminal. | 01-21-2010 |
| 20100019849 | RF PRE-AMPLIFIERS AND POWER AMPLIFIERS - An RF amplifier circuit includes a MOSFET connected to an RF output of the circuit via an impedance matching network including an inductor and a tuning capacitor connected in parallel with the inductor and the MOSFET. DC voltage is applied to the MOSFET via a series path through a radio frequency choke and the inductor of the impedance matching network. | 01-28-2010 |
| 20100019850 | GALLIUM NITRIDE MATERIAL TRANSISTORS AND METHODS ASSOCIATED WITH THE SAME - Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation. | 01-28-2010 |
| 20100033251 | OUTPUT STAGE CIRCUIT AND OPERATIONAL AMPLIFIER - An output stage circuit is disclosed, which includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. By using twin-well CMOS transistors and a specific circuit configuration, the invention supports a HALF AVDD structure, reduces power consumption and saves the cost of triple-well CMOS process. | 02-11-2010 |
| 20100039180 | AMPLIFYING CIRCUIT - An amplifier having an output stage with a complementary pair of first and second transistors each coupled to an output node of the amplifier; control circuitry arranged to provide a control signal at a control node of the first transistor based on the voltage at an input node of the amplifier; and adjustment circuitry arranged to adjust the control signal to maintain the current through the first transistor above a minimum value. | 02-18-2010 |
| 20100052788 | BROADBAND MICROWAVE DEVICE WITH SWITCHABLE GAIN - The invention relates to a broadband microwave device with switchable gain comprising a microwave signal input E and output S, a distributed amplifier with a plurality of amplifying cells comprising an input transmission line for an input signal applied to the microwave signal input E, said input transmission line having one of its two ends linked to the microwave signal input E, an output transmission line for said amplified input signal having an output end of the distributed amplifier, the cells of the distributed amplifier settable either to an amplifying state or to a blocked state. A switch switches the microwave signal output S either to a non-amplification position linked to the other end of the input transmission line, or to an amplification position linked to the output end of the distributed amplifier. A control unit supplies switch position control and amplifying cell status control signals. | 03-04-2010 |
| 20100066451 | Compound semiconductor device and doherty amplifier using compound semiconductor device - A lower electron supply layer is disposed over a lower electron transport layer made of compound semiconductor. The lower electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the lower electron transport layer. An upper electron transport layer is disposed over the lower electron supply layer. The upper electron transport layer is made of compound semiconductor having a doping concentration lower than that of the lower electron supply layer or non-doped compound semiconductor. An upper electron supply layer is disposed over the upper electron transport layer. The upper electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the upper electron transport layer. A source and drain electrodes are disposed over the upper electron supply layer. A gate electrode is disposed over the upper electron supply layer between the source and drain electrodes. | 03-18-2010 |
| 20100073091 | CIRCUIT ARRANGEMENT FOR PROVIDING AN ANALOG SIGNAL, AND ELECTRONIC APPARATUS - A circuit arrangement for providing an analog signal is disclosed. The circuit arrangement comprises a biasing resistor; an analog input arrangement; and a signal output, wherein the biasing resistor and the analog input arrangement are connected in series between a supply voltage and a reference voltage, and the signal output is connected such that the alternating voltage over the biasing resistor is provided as an output signal. An electronic apparatus comprising such a circuit arrangement is also disclosed. | 03-25-2010 |
| 20100090767 | RF AMPLIFICATION DEVICE - An RF amplification device has amplification elements which amplify a radio frequency input signal in wireless radio communication. Transmission line transformers are coupled to one of an input electrode and an output electrode of the amplification elements and have a main line Lout arranged between the input and the output, and a sub line Lin | 04-15-2010 |
| 20100097142 | DRIVING CIRCUIT SYSTEM AND METHOD OF ELEVATING SLEW RATE OF OPERATIONAL AMPLIFIER - The invention discloses a driving circuit system and a method of elevating a slew rate of an operational amplifier. The driving circuit system comprises an operational amplifier, a judging module and a bias enhancing module. The operational amplifier has an input stage driven by a bias current. The bias enhancing module is electrically connected to the judging module and the input stage of the operational amplifier respectively. The judging module is used to generate a bias enhancing signal according to an edge-trigger of a control signal. When the bias enhancing module receives the bias enhancing signal, the bias enhancing module provides an additional current, which cooperates with the bias current, for driving the input stage of the operational amplifier, so as to elevating a slew rate of the operational amplifier. | 04-22-2010 |
| 20100102885 | Method And System For Amplifying A Signal Using A Transformer Matched Transistor - A power amplifier includes a transistor, a transmission line transformer, and a capacitor. The transistor is operable to receive a signal and to generate an amplified signal. The transistor has a source, a drain, and a gate. The gate has a first impedance and is operable to receive the signal to be amplified. The transmission line transformer has a first, second, third, and fourth port, the first port being coupled to the gate of the transistor and the third port, and the fourth port being coupled to a source device having a second impedance. The capacitor has a first end and a second end. The first end of the capacitor is coupled to the second port of the transmission line transformer and the second end is coupled to a ground. | 04-29-2010 |
| 20100102886 | AMPLIFIER DEVICE - Provided is an amplifier device including a J-FET, a bipolar transistor, a first resistor and a second resistor. The amplifier device has a configuration in which a gate of the J-FET is connected to one end of an ECM and one end of the first resistor, a drain of the J-FET is connected to an input terminal of the bipolar transistor, a high-potential side of the bipolar transistor is connected to one end of a load resistor, the other end of the first resistor is grounded, a source of the J-FET and a low-potential side of the bipolar transistor are connected to one end of the second resistor, the other end of the second resistor is grounded, and an output voltage is drawn from the high-potential side of the bipolar transistor. | 04-29-2010 |
| 20100109776 | Millimeter Wave Monolithic Integrated Circuits - A millimeter wave amplifier constructed on a substrate and configured for use at a frequency of 75 GHz or higher, may include four amplifier stages. A first inter-stage filter, resonant at an operating frequency of the amplifier, may couple the output of the first stage to the input of the second stage. A second inter-stage filter, resonant at the operating frequency, may couple the output of the second stage to the input of the third stage. A third inter-stage filter, resonant at the operating frequency, may couple the output of the third stage to the input of the fourth stage. A plurality of bias supply leads that couple a gate bias voltage and a drain bias voltage to each of the amplifier stages. A plurality of bias line filters, resonant at the operating frequency, may be connected from at least some of the bias supply leads to a ground plane. | 05-06-2010 |
| 20100109777 | Amplifying Circuit - An amplifying circuit includes amplifying unit comprising a first transistor unit having a gate width that is controllable and is controlled based on a first control signal. | 05-06-2010 |
| 20100117738 | MULTILAYER AMPLIFIER MODULE - An amplifier module includes an integrated circuit device including a first amplifier circuit electrically connected to a first input terminal. The amplifier circuit includes a number of x first amplifier branches electrically connected to the first input terminal. The amplifier module also includes a number y of first output terminals each assigned to a respective TX frequency band, a first switching unit that electrically connects one or more of the first amplifier branches to one of the first output terminals, and a multilayer substrate, on top of which the integrated circuit device and the switching unit are mounted. The substrate includes integrated passive matching elements that are part of matching circuits where x≧1 and y≧2. Each of the first amplifier branches is adapted to deliver a different power level at its output and is matched to a load at the first output terminals by one of the matching circuits. | 05-13-2010 |
| 20100117739 | AUDIO POWER AMPLIFIER AND A PRE-AMPLIFIER THEREOF - An audio power amplifier includes a pre-amplifier, an error amplifier, a comparator, a bridge circuit, and a feedback circuit, in which the gain of the pre-amplifier gradually increases when the audio power amplifier is powered on. The comparator generates a PWM signal by comparing a reference signal and an amplified audio signal. The bridge circuit has switches controlled according to the PWM signal such that a driving current alternately flows to and from a load. The feedback circuit generates the feedback signal indicating a condition of the load. | 05-13-2010 |
| 20100127776 | AMPLIFIER WITH BIAS CIRCUIT PROVIDING IMPROVED LINEARITY - An amplifying device includes a cascode amplifier and a biasing circuit. The cascode amplifier is configured to receive an input signal and to output an amplified output signal corresponding to the input signal. The biasing circuit is configured to bias the cascode amplifier, the biasing circuit including a first current mirror and a second current mirror stacked on the first current mirror. The biasing circuit improves linearity of the cascode amplifier across a wide temperature range. | 05-27-2010 |
| 20100127777 | POWER AMPLIFIER AND LIQUID JET PRINTING APPARATUS - A power amplifier includes: a modulator pulse-modulating a drive waveform signal serving as a reference of a drive signal applied to an actuator and outputting a plurality of modulated signals; a digital power amplifier having a plurality of digital power amplifier stages each including a pair of push-pull switching elements, amplifying the power of the plurality of modulated signals, and outputting multi-value amplified digital signals; and a low pass filter smoothing the amplified digital signals and outputting the drive signal, wherein the modulator includes a control section switching one of a state where the same modulated signal is connected to two or more of the digital power amplifier stages and a state where different modulated signals are connected to different digital power amplifier stages to the other. | 05-27-2010 |
| 20100134188 | BUFFER AMPLIFIER - A buffer amplifier has high input impedance and is less affected by temperature by supplying independent bias power to each of amplification units. The buffer amplifier includes a bias supply unit supplying bias power having a preset voltage level, an amplification unit receiving preset driving power and the bias power from the bias supply unit to amplify an input signal, and a compensation unit compensating for current unbalance of the driving power supplied to the amplification unit. | 06-03-2010 |
| 20100141343 | OPERATIONAL TRANSCONDUCTANCE AMPLIFIER HAVING TWO AMPLIFICATION STAGES - An operational amplifier having a first amplification stage with an input terminal to receive a signal to be amplified, and a first output terminal, and a second amplification stage having a first input terminal connected to the first output terminal, and an output terminal to provide the amplified signal. The first and second amplification stages define, between the input terminal and the output terminal, a signal transfer function having first and second poles. The amplifier further includes a decoupling stage having a further input terminal connected to the first stage input terminal, and a further output terminal connected to the second stage output terminal. The decoupling stage is so arranged as to introduce at least one zero in the operational amplifier transfer function. | 06-10-2010 |
| 20100148873 | TECHNIQUES FOR IMPROVING AMPLIFIER LINEARITY - Techniques for improving the linearity of a cascode amplifier. In an exemplary embodiment, an auxiliary common-gate amplifier is provided in parallel with the principal cascode branch. The auxiliary common-gate amplifier samples a cascoded node in the principal cascode branch. The auxiliary common-gate amplifier generates a current which, when combined with the current generated by the principal cascode branch, cancels a distortion component to generate an output current with improved linearity characteristics. In an exemplary embodiment, a phase shifting network couples the cascoded node to the auxiliary common-gate amplifier, and may include, e.g., a capacitor coupled to an inductor. | 06-17-2010 |
| 20100156538 | AMPLIFIER CIRCUIT AND RADIO RECEIVER - A feedback resistor is connected between an input terminal and an output terminal of an operational amplifier. A negative resistor is connected between an inverting input terminal and a non-inverting input terminal of the operational amplifier. | 06-24-2010 |
| 20100182090 | ULTRA LOW NOISE HIGH LINEARITY LNA FOR MULTI-MODE TRANSCEIVER - An amplifier for operating at low, middle or high linearity modes, the amplifier comprising a first low noise amplifier (LNA) coupled to a second low noise amplifier for providing amplification; a first degeneration inductor coupled to the first LNA for providing impedance matching; a −g | 07-22-2010 |
| 20100188153 | High-efficiency power amplification apparatus using saturated operation and method for controlling the same - A saturated power amplification apparatus and a method for controlling the same are provided, in which a power device is provided, and an output matcher matches a load impedance of the power device. The load impedance is a complex impedance exceeding an impedance generated during power matching in the saturated power amplification apparatus. | 07-29-2010 |
| 20100201447 | Radio-frequency circuit - A radio-frequency circuit comprises a low-noise amplifier, an NMOS mixer for converting a radio-frequency signal output from the low-noise amplifier into an intermediate-frequency signal, a polyphase filter for removing image noises, and a PMOS mixer for converting the intermediate-frequency signal passed through the polyphase filter into a baseband signal. | 08-12-2010 |
| 20100214020 | HIGH PRECISION FOLLOWER DEVICE WITH ZERO POWER, ZERO NOISE SLEW ENHANCEMENT CIRCUIT - A high performance follower device coupled with a slew enhancement circuit includes an amplifier circuit containing a follower device connected to a three-terminal device, whereupon current drawn through the three-terminal device is amplified through a current amplifier and sent to the source terminal of the follower device to stabilize the output voltage when the input signal is changed rapidly or if the output voltage is disturbed by a changing output load. The presence of a cascode device also allows for the bootstrapping of the follower device. | 08-26-2010 |
| 20100214021 | Class AB Rail-to-Rail Operational Amplifier - An operational amplifier includes an output unit, a voltage drop element and a feedback unit. The output unit is provided for sourcing an output current to an output of the operational amplifier when operating with a power unit for providing a current being multiple times the value of the output current. The voltage drop is provided for generating a voltage drop in accordance with the output current. The feedback unit is controlled with the voltage drop generated by the voltage drop element and controls the output unit and the power unit to regulate the output current in accordance with the voltage drop. | 08-26-2010 |
| 20100225398 | MULTI-PATH, MULTI-OXIDE-THICKNESS AMPLIFIER CIRCUIT - An embodiment of a multi-path, multi-oxide-thickness amplifier circuit includes a first amplifier having at least one thin-oxide output transistor, and a second amplifier having at least one thick-oxide output transistor. The first and second amplifiers are connected in parallel with each other between an input terminal and an output terminal of the amplifier circuit. The thin-oxide output transistor has a gate-oxide layer thickness that is less than a gate-oxide layer thickness of the thick-oxide output transistor. | 09-09-2010 |
| 20100225399 | POWER AMPLIFIER, AND METHOD OF CONTROLLING POWER AMPLIFIER - A power amplifier of the present invention comprises MOS transistor ( | 09-09-2010 |
| 20100237945 | CASCODE AMPLIFIER WITH PROTECTION CIRCUITRY - A cascode amplifier with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel, with at least one branch being switchable between “on” and “off” states. Each switchable branch includes a gain transistor coupled to a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor and the cascode transistor in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor and shorting the gate and source of the cascode transistor. | 09-23-2010 |
| 20100244963 | AMPLIFIER CIRCUIT AND THE CONTROLLING METHOD THEREOF - An amplifier circuit includes a first unit and a second unit. The first unit has a first amplifying unit, wherein the first amplifying unit provides a first main circuit unit and a first assistant circuit unit, and the first assistant circuit unit is configured for assisting the linearity of the first main circuit unit. The second unit includes a second amplifying unit, wherein the second amplifying unit has a second main circuit unit and a second assistant circuit unit, and the second assistant circuit unit is configured for assisting the linearity of the second main circuit unit. The first amplifying unit is configured for conducting in one half cycle of an input signal, and the second amplifying unit is configured for conducting in the other half cycle of the input signal. | 09-30-2010 |
| 20100244964 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin. | 09-30-2010 |
| 20100244965 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction. | 09-30-2010 |
| 20100259329 | FIELD-PLATED TRANSISTOR INCLUDING FEEDBACK RESISTOR - Embodiments include but are not limited to apparatuses and systems including a unit cell having a source electrode, a gate electrode to receive an input radio frequency (RF) signal, and a drain electrode to output an amplified RF signal. A field plate may be coupled with the source electrode, and a feedback resistor may be coupled between the field plate and the source electrode. | 10-14-2010 |
| 20100264988 | Low noise cascode amplifier - The present invention relates to a low noise cascode amplifier comprising a first transistor, a second transistor, a third transistor, a first inductor, and a second inductor. Furthermore, the first transistor can connect with the second transistor via the first inductor, and the second transistor can connect with the third transistor via the second inductor; thereby, a cascode device can be formed. The inductor and the parasitic capacitances can resonate at high frequency, so that the noise figure of the cascode amplifier can be reduced. | 10-21-2010 |
| 20100271132 | Amplifier circuit with resistive current limitter - An amplifier circuit includes first transistor of first conductivity type having source connected to first power supply, while having gate connected to input terminal and drain connected to output terminal; transistor of second conductivity type having source connected to second power supply and drain connected to the output terminal; second transistor of the first conductivity type whose source and gate are connected to the source and gate of the first transistor of the first conductivity type, respectively; resistor whose one end connected to drain of the second transistor of the first conductivity type, and an output control circuit; current input terminal connected to the opposite end of the resistor; and voltage output terminal connected to the gate of the transistor of the second conductivity type. The output control circuit controls the gate voltage of the transistor of the second conductivity type based on the input current of the current input terminal. | 10-28-2010 |
| 20100271133 | Electronic Circuits including a MOSFET and a Dual-Gate JFET - Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths. | 10-28-2010 |
| 20100283544 | HARMONIC PROCESSING CIRCUIT AND AMPLIFYING CIRCUIT USING THE SAME - The present invention provides a harmonic processing circuit capable of miniaturizing a circuit, and an amplifier circuit using this harmonic processing circuit. | 11-11-2010 |
| 20100283545 | MULTI-PATH, MULTI-STAGE FEED-FORWARD OPERATIONAL AMPLIFIER CIRCUIT - An embodiment of an amplifier circuit includes a plurality of amplifiers connected between input and output terminals to form at least partially parallel amplification paths between the terminals. A first plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common first series-connected amplifier, and a second plurality of the amplification paths have different first amplifiers. Optionally, a third plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common last series-connected amplifier, and a fourth plurality of the amplification paths have different last amplifiers. Alternatively, a first plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common last series-connected amplifier, and a second plurality of the amplification paths have different last amplifiers. In the alternative embodiment, optionally a third plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common first series-connected amplifier, and a fourth plurality of the amplification paths have different first amplifiers. | 11-11-2010 |
| 20100295619 | Low Noise Amplifier - An embodiment of an LNA includes a voltage input, a voltage output, an input transistor connected as a source follower with a current source at the drain and source nodes of the input transistor, an input resistor connected between the source follower source node and signal ground, a gain boosting transistor with the gate connected to the input transistor drain node, wherein the source node is connected to ground and the drain node is connected through a load resistor to the input transistor source node. Such an LNA provides substantial improvement in power efficiency by adapting an output stage of the LNA to reuse the supply current of the input transistors to the LNA through a load resistor. | 11-25-2010 |
| 20100301942 | AMPLIFIER WITH BYPASS SWITCH - An amplifying circuit of a receiver for receiving a signal in a wireless network includes an amplifier and a switch. The amplifier includes an amplifying transistor having a gate connected to an input for receiving the signal and a source/drain connected to a voltage source through an inductance. The amplifier also includes a bypass transistor having a gate connected to a control signal for activating the bypass transistor in a bypass mode and a source/drain connected in parallel with the inductance. The switch is connected in parallel with the amplifier between the input and an output, and activates in the bypass mode, enabling the received signal to bypass the amplifier. In the bypass mode, a voltage at the source/drain of the amplifying transistor is lower when the bypass transistor is activated than when not activated, the lower source/drain RF voltage reducing unwanted harmonics from the amplifier. | 12-02-2010 |
| 20100301943 | High Voltage Amplification Using Low Breakdown Voltage Devices - Methods and apparatus for amplifying signals over a wide frequency range to generate high voltage outputs feature a pair of switching modules which are connected in series. Switching modules, e.g., field-effect transistors (FETs), operate based on the voltage difference between an amplified signal and a fixed DC signal at two of their terminals, thereby generating an output waveform that has peak-to-peak voltage higher than, e.g. twice, the breakdown voltage of the transistors within the amplifier. The DC signals applied at the switching modules may be varied using an AC signal to improve the risetime of the output waveform and achieve a faster operational speed of the amplifier. | 12-02-2010 |
| 20100301944 | POWER AMPLIFIER - A power amplifier includes: a semiconductor substrate; a preceding-stage amplifying device on the semiconductor substrate, amplifying an input signal; a following-stage amplifying device on the semiconductor substrate, amplifying an output signal of the preceding-stage amplifying device; and an inter-stage matching circuit connecting the preceding-stage amplifying device to the following-stage amplifying device. The preceding-stage amplifying device has a first field effect transistor; the following-stage amplifying device has a heterojunction bipolar transistor; and the inter-stage matching circuit has a capacitance galvanically separating the output terminal of the preceding-stage amplifying device from the input terminal of the following-stage amplifying device. | 12-02-2010 |
| 20100301945 | POWER AMPLIFIER INTEGRATED CIRCUIT WITH COMPENSATION MECHANISM FOR TEMPERATURE AND OUTPUT POWER - A power amplifier integrated circuit, which generates an RF output signal by amplifying an RF input signal, includes a thermal-sensing circuit, a feedback circuit, a logic judging circuit, an adjusting circuit, and an amplifying circuit. The thermal-sensing circuit generates a thermal sensing signal according to the operational temperature, and the feedback circuit generates a power compensation circuit according to power variations in the RF output signal. The logic judging circuit outputs a compensation signal according to the thermal sensing signal and the power compensation signal. The adjusting circuit adjusts the level of the RF input signal according to the compensation signal, thereby generating a corresponding 1st stage RF signal. The amplifying circuit can amplify the 1st stage RF signal, thereby generating the corresponding RF output signal. | 12-02-2010 |
| 20100308915 | Phase Margin Modification In Operational Transconductance Amplifiers - The present disclosure relates to phase margin modification in operational transconductance amplifiers. | 12-09-2010 |
| 20100327976 | INTEGRATED POWER AMPLIFIER WITH LOAD INDUCTOR LOCATED UNDER IC DIE - A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier. | 12-30-2010 |
| 20110006845 | AMPLIFIER STAGE - An amplifier stage for generating an amplified output signal from an input signal, a mobile device comprising an audio amplifier, and an amplification method for generating an amplified output signal from an input signal using an amplifier stage are described. | 01-13-2011 |
| 20110012680 | SEMICONDUCTOR DEVICE, RADIO FREQUENCY CIRCUIT, AND RADIO FREQUENCY POWER AMPLIFIER - A semiconductor device and a radio frequency circuit which are appropriate for multiband, multimode performance can be realized as a semiconductor device including a field-effect transistor formed on a semiconductor substrate, and include: ohmic electrodes serving as source and drain electrodes of the field-effect transistor, first and second Schottky electrodes provided between the ohmic electrodes and serving as gate electrodes of the field-effect transistor, and a third Schottky electrode provided and grounded between the first and second Schottky electrodes. | 01-20-2011 |
| 20110018635 | MULTI-MODE LOW NOISE AMPLIFIER WITH TRANSFORMER SOURCE DEGENERATION - A multi-mode low noise amplifier (LNA) with transformer source degeneration is described. In an exemplary design, the multi-mode LNA includes first, second, and third transistors and first and second inductors. The first transistor has its source coupled to the first inductor, amplifies an input signal, and provides a first amplified signal in a first mode. The second transistor has its source coupled to the second inductor, amplifies the input signal, and provides a second amplified signal in a second mode. The third transistor has its source coupled to the second inductor. The first and third transistors receive the input signal and conduct current through the first and second inductors, respectively, in a third mode. The first transistor observes source degeneration from a transformer formed by the first and second inductors, amplifies the input signal, and provides a third amplified signal in the third mode. | 01-27-2011 |
| 20110018636 | SIGNAL AMPLIFICATION APPARATUS WITH ADVANCED LINEARIZATION - Provided is a signal amplification apparatus with advanced linearization, the signal amplification apparatus including: a driving unit having a structure of a cascode amplifier including a first active element and a second active element and outputting an amplification signal in which an input signal is amplified, to an output terminal; a third active element receiving a signal diverged between the first active element and the second active element while gate and drain terminals of the third active element are shorted; a fourth active element of which gate and drain terminals are connected to a source terminal of the third active element; and a fifth active element of which gate terminal is connected to the drain terminal of the fourth active element, outputting a non-linear signal having an opposite phase to the amplification signal to the output terminal so as to cancel a third-order inter-modulation distortion component included in the input signal. An amplification signal in which an input signal is amplified is combined with a non-linear signal having an opposite phase to the amplification signal and a low gain and is output so that a third-order inter-modulation distortion component included in the input signal can be cancelled and a signal with advanced linearity can be output. | 01-27-2011 |
| 20110032035 | AMPLIFIER MODULE WITH MULTIPLE OPERATING MODES - An amplifier module with multiple operating modes is described. In an exemplary design, the amplifier module includes an amplifier (e.g., a power amplifier), a switch, and an output circuit. The amplifier receives and amplifies an input signal and provides an amplified signal in a first mode. The switch is coupled to the output of the amplifier and bypasses the amplifier and provides a bypass signal in a second mode. The output circuit is coupled to the amplifier and the switch. The output circuit performs output impedance matching for the amplifier in the first mode. The output circuit also (i) receives the amplified signal and provides an output signal in the first mode and (ii) receives the bypass signal and provides the output signal in the second mode. The amplifier is enabled in the first mode and disabled in the second mode. | 02-10-2011 |
| 20110037519 | AMPLIFIER WITH VARIABLE MATCHING CIRCUIT TO IMPROVE LINEARITY - Techniques for reducing distortion and improving linearity of amplifiers are described. In an exemplary design, an apparatus includes a driver amplifier, a variable matching circuit, and a power amplifier. The driver amplifier amplifies a first RF signal and provides a second RF signal. The variable matching circuit receives the second RF signal and provides a third RF signal. The power amplifier amplifies the third RF signal and provides a fourth RF signal. The variable matching circuit matches a fixed impedance at the output of the driver amplifier to a variable impedance at the input of the power amplifier in order to improve the linearity of the amplifiers. In an exemplary design, the power amplifier includes a first transistor (e.g., an NMOS transistor) of a first type, and the variable matching circuit includes a second transistor (e.g., a PMOS transistor) of a second type that is different from the first type. | 02-17-2011 |
| 20110043284 | STACKED AMPLIFIER WITH DIODE-BASED BIASING - Techniques for improving linearity of amplifiers are described. In an exemplary design, an amplifier (e.g., a power amplifier) may include a plurality of transistors coupled in a stack and at least one diode. The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage to an associated transistor in the stack. Each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor may have higher gain at high input power due to the higher bias voltage from the at least one diode. The higher gain may improve the linearity of the amplifier. | 02-24-2011 |
| 20110043285 | DIGITAL TUNABLE INTER-STAGE MATCHING CIRCUIT - A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e.g., a driver amplifier), a second active circuit (e.g., a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors. | 02-24-2011 |
| 20110050345 | Linearization Circuits and Methods for Power Amplification - Linearization circuits of the invention are used in conjunction with power amplification circuits that comprise a power amplifier core. Exemplary linearization circuits comprise a replica of the power amplifier core. In operation, the linearization produces an envelope signal from an RF signal. The envelope signal is used to control the replica to produce an analog output signal which represents the inverse of the AM to AM distortion of the power amplifier core. The linearization circuit then biases the RF signal with the inverted non-linear signal of the replica to control the power amplifier core. The power amplifier core and the replica thereof can be defined on the same semiconductor die so both respond to process variables similarly. | 03-03-2011 |
| 20110057728 | AMPLIFIER CIRCUIT, INTEGRATED CIRCUIT AND RADIO FREQUENCY COMMUNICATION UNIT - An amplifier circuit for amplifying an input signal received at an input node of the amplifier circuit. The amplifier circuit comprises a feedback resistance connected between the input node of the amplifier circuit and an output node of the amplifier circuit. Transconductance circuitry is arranged to inject a transconductance current at a point along the feedback resistance. The transconductance circuitry is configurable to vary the point along the feedback resistance where the transconductance current is injected. | 03-10-2011 |
| 20110063032 | BALUN AMPLIFIER - A balun amplifier is provided, which includes two input terminals, two output terminals and two modules. The first and the second input terminals receive a single-ended input signal, respectively. The first and the second output terminals provide a differential output signal. The first module is coupled to the first input terminal, the first output terminal, and the second output terminal. The second module is coupled to the second input terminal, the first output terminal, and the second output terminal. The first and the second modules receive the single-ended input signal through the first and the second input terminals respectively, amplify the single-ended input signal respectively, and convert the single-ended input signal into the differential output signal. The circuit topologies of the first and the second modules are symmetric except that types of transistors in the first and the second modules are different. | 03-17-2011 |
| 20110063033 | OUTPUT STAGE OF A CLASS-A AMPLIFIER - An output stage of an integrated class-A amplifier in a technology adapted to a first voltage and intended to be powered by a second voltage greater than the first one, including: one or several transistors of a first channel type between a first terminal of application of the second voltage and an output terminal of the stage; transistors of a second channel type between this output terminal and a second terminal of application of the second voltage, wherein: a first transistor of the second channel type has its gate directly connected to an input terminal of the stage; at least a second and a third transistors of the second channel type are in series between the output terminal and said first transistor, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor, and the gate of the third transistor being biased to a fixed voltage. | 03-17-2011 |
| 20110068871 | AMPLIFIER FOR AMPLIFYING A HIGH-FREQUENCY SIGNAL - A transistor is provided to amplify a high frequency signal. A gate/base of the transistor receives the high frequency input signal. A variable capacitor is connected between the gate and a source/between the base and an emitter of the transistor. A variable inductor is connected with the source/the emitter of the transistor. | 03-24-2011 |
| 20110068872 | Amplifying apparatus - An amplifying apparatus amplifies an input signal supplied to an input terminal and outputs an output signal from an output terminal. The apparatus includes a high-potential power supply line through which a high voltage is supplied; a low-potential power supply line through which a low voltage is supplied; a control unit; and a power supply in which one of the high and low voltages is a fixed voltage, and which generates, as the other of the high and low voltages, one of a first voltage in which a polarity of the fixed voltage is inverted, and a second voltage which is closer to the ground potential than the first voltage is. The control unit controls the power supply to cause the other of the high and low voltages to be switched between the first voltage and the second voltage in accordance with a signal level of the output signal. | 03-24-2011 |
| 20110074511 | LAYOUT AND PAD FLOOR PLAN OF POWER TRANSISTOR FOR GOOD PERFORMANCE OF SPU AND STOG - A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%. | 03-31-2011 |
| 20110080217 | AUDIO AMPLIFIER - An audio amplifier includes a compensation unit, an output unit and a calibration unit. The compensation unit generates a compensation signal based on a digital input signal, a digital reference code, a mode signal and a digital approximation code. The output unit generates an output signal based on the compensated input signal. The calibration unit generates the digital approximation code based on the output signal and the mode signal. The digital approximation code includes a plurality of bits that are generated sequentially. | 04-07-2011 |
| 20110084765 | Three Dimensional Inductor and Transformer - A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip. | 04-14-2011 |
| 20110095824 | RF POWER AMPLIFIER INTEGRATED CIRCUIT AND UNIT CELL - A novel RF power amplifier integrated circuit (PA IC), unit cell, and method for amplifying RF signals are disclosed. One embodiment of a PA IC includes at least two linear arrays comprising transistor device units, and at least one linear array comprising capacitors. The transistor device units include source nodes that are jointly coupled to a source bus, and selected gate nodes that are jointly coupled to a gate bus. First electrodes of the capacitors are also jointly coupled to the source bus, and second electrodes of the capacitors are jointly coupled to the gate bus. Each linear array comprising capacitors is disposed between at least two linear arrays comprising transistor device units. In one embodiment, the PA IC includes unit cells. In some embodiments, each unit cell comprises two transistor device units and one or more capacitors. The capacitors are disposed between the transistor device units. The unit cells are disposed in linear arrays so that the transistor device units are disposed in linear arrays and the capacitors are disposed in linear arrays. | 04-28-2011 |
| 20110095825 | Error Amplifier - One of the objects of the present invention is to suppress variations in the frequency response of a feedback circuit due to variations in the value of a passive element in an error amplifier. One of the embodiments of the present invention provides a configuration allowing the frequency response of a feedback circuit in an error amplifier to be determined by not only the value of a passive element but the gain of an active element. This error amplifier includes a voltage-to-current converter which is an active element. In addition, a first terminal, a second terminal, an operational amplifier, a first resistor, a second resistor, first to fifth transistors, a first current source, and a second current source can be built into an integrated circuit, and a capacitor can be externally provided. | 04-28-2011 |
| 20110102087 | DC SLOPE GENERATOR - A system for generating a tunable DC slope includes: a first stage, supplied with an external voltage, for receiving a process, voltage and temperature (PVT) insensitive reference voltage and generating a voltage independent current; a second stage, coupled to the first stage and supplied with the external voltage, for generating a voltage dependent current and summing the voltage dependent current and the voltage independent current to generate a sloped voltage; and a third stage, coupled to the second stage and supplied with the external voltage, for amplifying the sloped voltage, and tapping the resultant sloped voltage at a desired point for generating the output DC slope. | 05-05-2011 |
| 20110102088 | LOW NOISE AMPLIFIER CIRCUIT - Low noise amplifier circuit. The low noise amplifier circuit includes an amplifier that amplifies an input to provide an output. The amplifier is coupled to an input terminal. The circuit also includes a device in a cascode connection with the amplifier. The circuit further includes a tuning circuit coupled to the device to phase shift the output. Further, the circuit includes a feedback circuit that is responsive to a phase-shifted output to enhance gain of the amplifier. The feedback circuit is coupled to the tuning circuit and the amplifier. | 05-05-2011 |
| 20110109391 | Power Amplifier with Stabilising Network - A power amplifier circuit comprising a transistor for receiving a signal to be amplified at an input and for outputting an amplified signal at an output; a modulated power supply connected to the transistor output; and a resistive element connected at the transistor output such that a low impedance is maintained at the transistor output across a range of operational frequencies. | 05-12-2011 |
| 20110121903 | POWER AMPLIFIER - There is provided a power amplifier that can increase power efficiency by preventing power consumption caused by DC components from an RF input signal. A power amplifier according to an aspect of the invention may include: an inverter amplification section amplifying an input signal according to an inverter method to thereby remove DC components from the input signal; an impedance matching section matching an impedance of a transmission path of the input signal amplified by the inverter amplification section; and an amplification section amplifying an impedance-matched signal from the impedance matching section according to a gain set beforehand. | 05-26-2011 |
| 20110140783 | DOHERTY AMPLIFIER WITH COMPOSED TRANSFER CHARACTERISTIC HAVING MULTIPLE PEAK AMPLIFIERS - A combination amplifier ( | 06-16-2011 |
| 20110140784 | Amplifier Circuit - An amplifier circuit includes a pair of amplifying devices, a first balun coupled between an input port of the amplifier circuit and RF input ports of the pair of amplifying devices and a second balun coupled between RF output ports of the pair of amplifying devices and an output port of the amplifier circuit wherein the first and second baluns are configured such that the amplifier circuit operates under open condition for signals at a second harmonic frequency even when the second harmonic frequency is within an operating frequency band of a fundamental frequency of the amplifier circuit. In one embodiment, the amplifier circuit includes a bypass circuit which selectively couples balun ports to ground such that in response to a first control signal, the amplifier circuit operates in an amplifying mode and in response to a second control signal, the amplifier circuit operates in a bypass mode. | 06-16-2011 |
| 20110148526 | Low noise amplifier with variable frequency response - The present invention relates a low noise amplifier with adaptive frequency responses and method of altering frequency responses thereof. The low noise amplifier comprises an inductive degeneration circuit, N cascode circuits and N switches. The inductive degeneration circuit has an input impedance and a frequency response characteristic. Each of the cascode circuits is connected in parallel to the inductive degeneration circuit. Each of the switches is connected to a corresponding cascode circuit respectively. Each of the cascode circuit is turned ON or OFF by enabling or disabling the corresponding switches to alter the frequency response characteristic. | 06-23-2011 |
| 20110156817 | POWER AMPLIFIER - Disclosed herein is a power amplifier. The power amplifier includes a first common source transistor for amplifying an input signal into a predetermined level, a second common source transistor for compensating for input capacitance and performing auxiliary amplification for the first common source transistor, and a common gate transistor connected to the first common source transistor in a cascode structure, configured to be connected in parallel to the second common source transistor and prevent the first common source transistor from breaking down, and configured to output a signal amplified by a value obtained by adding the gain of the first common source transistor and the gain of the second common source transistor to each other. | 06-30-2011 |
| 20110163812 | ULTRA LOW-POWER CMOS BASED BIO-SENSOR CIRCUIT - An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material. | 07-07-2011 |
| 20110169570 | AMPLIFIER - An amplifier includes a first amplifier comprising an N-type field-effect transistor receiving a reference voltage at a gate, a P-type field-effect transistor connected between a drain of the N-type field-effect transistor and a power supply voltage line, and a constant current source connected between a source of the N-type field-effect transistor and a ground, to output a voltage from a connection of the drain of the N-type and P-type field-effect transistors; a second amplifier comprising a resistance and P-type field-effect transistors connected in series between the power supply voltage line and the ground to receive the voltage output from the first amplifier at their gate, and outputting a voltage from a connection of the P-type field-effect transistor and the resistance; and a switch between an output of the first amplifier and the power supply voltage line and comprising an N-type field-effect transistor receiving a reference voltage at a gate. | 07-14-2011 |
| 20110169571 | RE-CONFIGURABLE AMPLIFIER - An amplifier stage in a radar system including an input matching stage, a transistor stage and an output matching stage. At least one of the matching stages includes a switch. Each switch is arranged to connect or disconnect a corresponding at least one grounded matching component to or from the matching stage. Each switch in the matching stages of the amplifier stage is a switch that is arranged to connect or disconnect grounded matching components to or from the matching stages. | 07-14-2011 |
| 20110181360 | Stacked linear power amplifier with capacitor feedback and resistor isolation - A power amplifier with stacked, serially connected, field effect transistors is described. DC control voltage inputs are fed to the gates of each transistor. Capacitors are coupled to the transistors. The inputs and the capacitors are controlled to minimize generation of non-linearities of each field effect transistor and/or to maximize cancellation of distortions between the field effect transistors of the power amplifier in order to improve linearity of the power amplifier output. | 07-28-2011 |
| 20110215871 | Electronic circuits including a MOSFET and a dual-gate JFET - Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths. | 09-08-2011 |
| 20110241781 | Variable Class Characteristic Amplifier - A power amplifier (PA) adjustably operable between two classes of operation. The range of operation lies in a range of operation between a conventional, linear, conjugately matched Class AB characteristic amplifier and a higher efficiency switching Class E characteristic amplifier. A circuit topology having a push-pull configuration that allows a Class E characteristic of operation. | 10-06-2011 |
| 20110248783 | CIRCUIT FOR AMPLIFYING A SIGNAL REPRESENTING A VARIATION IN RESISTANCE OF A VARIABLE RESISTANCE AND CORRESPONDING SENSOR - A circuit for amplifying a signal representing a variation in resistance of a variable resistance comprising at least one first load linked to an output terminal of a first transistor whose other terminal is associated with a variable resistance, in such a way as to allow the recovery of the amplified signal at the terminals of the first load. | 10-13-2011 |
| 20110254627 | SIGNALING SYSTEMS, PREAMPLIFIERS, MEMORY DEVICES AND METHODS - Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit. | 10-20-2011 |
| 20110291761 | HIGH-SPEED SENSING FOR RESISTIVE MEMORIES - Embodiments of the present disclosure use one or more gain stages to generate an output voltage representing whether a resistive memory element of a data cell stores a high data value or a low data value. In a particular embodiment, an apparatus includes a sensing circuit. The sensing circuit includes a first amplifier stage that is configured to convert a first current through a first resistive memory element of a memory cell into a first single-ended output voltage. A second amplifier stage is configured to amplify the first single-ended output voltage of the first amplifier stage to produce a second single-ended output voltage. | 12-01-2011 |
| 20110291762 | INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a cell array including a plurality of unit cells, a first amplification circuit amplifying an input signal received from at least one unit cell among the unit cells, a signal transmission unit to transmit the signal to the first amplification circuit in response to a selection signal, first amplification control circuit to output a first amplification control signal controlling an amplification operation of the first amplification circuit, a second amplification circuit to amplify an output signal of the first amplification circuit, a second amplification control circuit to output a second amplification control signal controlling an amplification operation of the second amplification circuit, and a voltage adjustment circuit to adjust an internal voltage of the first amplification circuit in response to a voltage adjustment signal before the first and second amplification circuits perform the amplification operation. | 12-01-2011 |
| 20110304396 | POWER AMPLIFIER AND PROCESSING DEVICE UTILIZING THE SAME - A processing device including a control unit and a power amplifier is disclosed. The control unit generates a plurality of control signals according to an input signal. The power amplifier includes a plurality of switches. The control signals control the switches to turn on or off such that a short through current does not occur in the power amplifier. | 12-15-2011 |
| 20110304397 | HIGH EFFICIENCY AUDIO AMPLIFIER SYSTEM - A high efficiency amplifier system may include multiple output stages cooperatively operating to produce an amplified output signal. The amplifier system may be used in an audio system. The amplifier system may include a non-switchmode amplifier stage cooperatively operating with a switchmode amplifier stage to generate the amplifier output signal. The non-switchmode amplifier stage may selectively enable and disable the switchmode amplifier stage to optimize efficient operation. In addition, the switchmode amplifier stage may include multiple switching stages operated with interleave. The switching stages may be controlled to balance current output of the respective switching stages based on a measured current flow in at least one of the switching stages. | 12-15-2011 |
| 20110316631 | LNA CIRCUIT FOR USE IN A LOW-COST RECEIVER CIRCUIT - A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal. | 12-29-2011 |
| 20110316632 | OPTICAL COMMUNICATION DEVICE - An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP | 12-29-2011 |
| 20120007678 | Broadband Transistor Bias Network - An amplifying circuit for use in, for example, broadband transceivers is described. A bias filter is connected between an amplifying transistor and a power supply to block a wide range of frequencies associated with amplified RF input signals from reaching the power supply, while permitting DC power to reach the transistor. | 01-12-2012 |
| 20120007679 | Integrated RF Front End with Stacked Transistor Switch - A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits. | 01-12-2012 |
| 20120032741 | Integrated Bluetooth and Wireless LAN Transceivers Having Merged Low Noise and Power Amplifier - A group of transistors operate as a combined power amplifier, to amplify signals to be transmitted, and as a low noise amplifier, to amplify signals which are received. In a first mode, the group of transistors is configured to amplify the signals to be transmitted by turning all of the transistors in both a first subset and a second subset on. In a second mode, the group of transistors is configured to amplify the signals which have been received by turning on the first subset of transistors and turning off the second subset of transistors. | 02-09-2012 |
| 20120038423 | VARIABLE GAIN BICMOS AMPLIFIER - An amplifier circuit comprising: a MOSFET amplifier circuit; a BJT amplifier circuit; a MOSFET switch circuit arranged for switching between the MOSFET amplifier circuit and the BJT amplifier circuit to implement different gain modes of the amplifier circuit. | 02-16-2012 |
| 20120056672 | Class-AB/B amplifier and quiescent control circuit for implementation with same - Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit. | 03-08-2012 |
| 20120056673 | BUFFERING APPARATUS AND METHOD - The output impedance of an amplifier is substantially matched to an input impedance of a receiver using a buffer circuit. The buffer circuit includes a primary transistor and a secondary transistor. A first back gate terminal of the primary transistor is coupled to a second back gate terminal of the secondary transistor and the primary transistor is configured to have an output for the buffer circuit. An input signal is received from the amplifier at a gate terminal of the secondary transistor. The first back gate terminal of the primary transistor is responsively driven independently from the output of the buffer circuit to effectively adjust a transconductance of the primary transistor and substantially match an output impedance of the amplifier with an input impedance of the receiver. | 03-08-2012 |
| 20120086511 | DISTRIBUTED POWER AMPLIFIER WITH ACTIVE MATCHING - A distributed power amplifier arranged to operate over a bandwidth. An input side with an input terminal is arranged to receive an input signal and connected to an input transmission line. An output side with an output terminal is adapted to deliver an output signal and connected to an output transmission line. A power splitter is connected to the input terminal, thus being arranged to divide the input signal in a first path to the input transmission line and in a second path to an input of an active matching circuit. The active matching circuit has an output connected to the output transmission line. The other end of the output transmission line is connected to the output terminal. A method to design a distributed power amplifier and to modify existing distributed power amplifiers. | 04-12-2012 |
| 20120092072 | OFFSET COMPENSATION FOR SENSE AMPLIFIERS - A sense amplifier having compensation circuitry is described. The compensation circuitry includes at least one pair of compensation transistors. When compensation is desired, one or a combination of the bulk of the at least one pair of compensation transistors is provided with one or a combination of compensation voltages. | 04-19-2012 |
| 20120098598 | HIGH- FREQUENCY POWER AMPLIFIER - A radio frequency power amplifier having a transistor | 04-26-2012 |
| 20120098599 | ENHANCEMENT MODE HEMT FOR DIGITAL AND ANALOG APPLICATIONS - An enhancement mode (E-mode) HEMT is provided that can be used for analog and digital applications. In a specific embodiment, the HEMT can be an AlN/GaN HEMT. The subject E-mode device can be applied to high power, high voltage, high temperature applications, including but not limited to telecommunications, switches, hybrid electric vehicles, power flow control and remote sensing. According to an embodiment of the present invention, E-mode devices can be fabricated by performing an oxygen plasma treatment with respect to the gate area of the HEMT. The oxygen plasma treatment can be, for example, an O2 plasma treatment. In addition, the threshold voltage of the E-mode HEMT can be controlled by adjusting the oxygen plasma exposure time. By using a masking layer protecting regions for depletion mode (D-mode) devices, D-mode and E-mode devices can be fabricated on a same chip. | 04-26-2012 |
| 20120126898 | AMPLIFYING APPARATUS - An amplifying apparatus includes a first amplifier that amplifies an input signal on the basis of a value of a drain voltage and outputs a transmission signal, a distortion compensator that corrects a power amplitude of the input signal on the basis of a difference in power amplitude between the input signal and the transmission signal outputted from the first amplifier, a drain voltage controller that generates the drain voltage on the basis of the power amplitude of the input signal to be corrected, and a drain voltage corrector that corrects the drain voltage on the basis of the difference. | 05-24-2012 |
| 20120133440 | POWER AMPLIFYING DEVICE AND COUPLED POWER AMPLIFYING DEVICE - A power amplifying device includes earth parts which are connected with via holes for grounding, source electrode earth conductors which connect the earth parts, source electrodes which are coupled to the source electrode earth conductors, an inner source electrode which is not in contact with the source electrode earth conductors, a drain electrode, a gate electrode and an air bridge which directly connects the inner source electrode and earth parts. | 05-31-2012 |
| 20120146728 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device is provided with a compound semiconductor layer and a gate electrode formed on the compound semiconductor layer via a gate insulating film, in which the gate insulating film is one in which Si | 06-14-2012 |
| 20120154052 | POWER AMPLIFYING APPARATUS - There is provided a power amplifying apparatus including: a power amplifier; a power regulator providing a driving voltage and a driving current corresponding to a control voltage to the power amplifier; a current sensing unit sensing a current and a voltage corresponding to the driving current and controlling the driving voltage according to the sensed current; a current control unit controlling a current bias according to the sensed voltage of the current sensing unit; and a current bias circuit unit controlling a bias current of the power amplifier according to the controlling of the current control unit. | 06-21-2012 |
| 20120161874 | Operational Amplifier - An operational amplifier comprises: a plurality of transistors, comprising: a first transistor; and a second transistor, wherein a source of the first transistor is connected to a source of the second transistor; wherein the first transistor and the second transistor have near zero threshold voltage. | 06-28-2012 |
| 20120169423 | RADIO FREQUENCY AMPLIFIER CIRCUIT - A radio frequency amplifier circuit according to the present invention is for providing a radio frequency amplifier circuit with high output and high efficiency, and includes (i) a first harmonic processing circuit ( | 07-05-2012 |
| 20120188017 | POWER SUPPLY CIRCUIT OF POWER AMPLIFIER, AND TERMINAL - Embodiments of the present invention a power supply circuit of a power amplifier and a terminal, relating to the communication field. The power supply circuit of the power amplifier includes a direct current/direct current converter chip, where the direct current/direct current converter chip includes an input pin, an inductance pin, and a feedback pin, and the input pin is connected to a power supply and the inductance pin is connected to a voltage input end of the power amplifier through an LC storage circuit. A control circuit is connected between the voltage input end of the power amplifier and the feedback pin; the control circuit includes a control voltage, where the control voltage adjusts the voltage at the voltage input end of the power amplifier through the control circuit and the control voltage is variable. | 07-26-2012 |
| 20120218040 | CLASS-AB POWER AMPLIFIER - According to an embodiment, a class-AB power amplifier includes an amplifying element whose power supply voltage is expressed as Vdc and whose maximum current is expressed as Imax, a conduction angle θo of the amplifying element being more than π(rad) and less than 2·πr(rad), and load impedance of a fundamental wave being expressed as Z | 08-30-2012 |
| 20120218041 | AMPLIFIER CIRCUIT - An amplifier circuit includes: a first transformer in which a first inductor and a second inductor are magnetically coupled; a first field-effect transistor in which a gate is connected to a first input node via the first inductor, a drain is connected to a drain bias potential node via the second inductor, and a source is connected to a reference potential node; and a first output node connected to the drain of the first field-effect transistor. | 08-30-2012 |
| 20120235747 | Broadband, High-Linearity Led Amplifier Having High Output Capacity in a Compact Design - An amplifier circuit for actuating a light diode is provided. The amplifier circuit may have a small output impedance of approximately 3 Ohms, a large bandwidth having a lower threshold frequency of 200 kHz and an upper threshold frequency of 5 MHz, for example, and an amplitude of the output current of several 100 mA, for example. The amplifier circuit may have an entry stage for actuating a driver circuit that actuates the light diode by means of a direct current supply. | 09-20-2012 |
| 20120249246 | OPERATIONAL AMPLIFIER - An operational amplifier includes an input stage, an output stage, an output enable switch, an internal capacitor, a coupling effect reduction circuit. The input stage provides an intermediate signal according to an input signal. The output stage, including an output node, provides a driving signal according to the intermediate signal. The output enable switch is turned on during an output enable period, having a start time point, to drive a load with the driving signal. The internal capacitor is coupled between the input stage and the output stage. The coupling effect reduction circuit, coupled between the internal capacitor and the output node or between the internal capacitor and the input stage, is turned off during an operational period starting from the start time point, to prevent coupling charge generated when the output enable switch is turned on from affecting operational voltage levels of the input stage. | 10-04-2012 |
| 20120268210 | IMPEDANCE MATCHING ARRANGEMENT FOR AMPLIFIER HAVING SPLIT SHUNT CAPACITOR AND AMPLIFIER INCLUDING THE SAME - An amplifier having an operating frequency includes: an input port and an output port; three gain elements, each having an input terminal and an output terminal; an input matching network; and an output matching network. The input matching network includes: a first microstrip line which is connected to the input port and is an inductor at the operating frequency; a second microstrip line extending between the input terminals of the three gain elements; and a first split shunt capacitor connecting the first microstrip line to the second microstrip line. The output matching network includes: a third microstrip line which is connected to the output port and is an inductor at the operating frequency; a fourth microstrip line extending between the output terminals of the three gain elements; and a second split shunt capacitor connecting the third microstrip line to the fourth microstrip line. | 10-25-2012 |
| 20120268211 | POWER AMPLIFIER - According to an embodiment, a power amplifier includes: an MMIC substrate; a high frequency probe pad disposed on the MMIC substrate; and a metal plate disposed on the MMIC substrate so as to adjoin to the high frequency probe pad, and connected to an MMIC external circuit via a bonding wire. | 10-25-2012 |
| 20120274402 | HIGH ELECTRON MOBILITY TRANSISTOR - A high electron mobility transistor (HEMT) includes a substrate, a heterojunction on the substrate including a first layer having a Group III-nitride semiconductor material interfaced to a second layer having a doped Group III-nitride semiconductor material. A gate electrode is on a surface of the heterojunction, and a source and a drain are on opposite sides of said gate electrode. A patterned field shaping (FS) layer formed from a wide band-gap semiconductor material is over the heterojunction on at least a portion between the gate electrode and the drain. | 11-01-2012 |
| 20120299657 | MULTI-MODE POWER AMPLIFIER - There is provided a multi-mode power amplifier operable in a low power mode having a preset power range and in a high power mode having a power range higher than the power range of the low power mode. The multi-mode power amplifier includes: a high power amplifying unit including at least one cascode amplifier to amplify an input signal to a high power level having a preset power range; a low power amplifying unit sharing a common source node of the at least one cascode amplifier to amplify the input signal to a low power level having a power range lower than the high power level; and a coupling unit coupling a transfer path of a signal output from the high power amplifying unit and a transfer path of a signal output from the low power amplifying unit to each other. | 11-29-2012 |
| 20120306576 | METHOD AND SYSTEM FOR IMPROVING LINEARITY OF AN AMPLIFIER BY MEANS OF IM3 CANCELATION - An amplifier for providing improved third-order intermodulation (IM3) cancelation. The amplifier may comprise a main branch for amplifying input signals and an auxiliary branch for generating IM3 signals that are equal to corresponding IM3 components resulting from amplifying input signals via the main branch, with both of the main and the auxiliary branches being configured as differential circuits. The differential implementation may result in the auxiliary branch generating IM3 distortion signals with minimal or no non-IM3 signals. Each of the main and the auxiliary branches may comprise at least two transistor elements. Separate bias current sources may be applied to each of the main and the auxiliary branches. Operation of the auxiliary branch may be controlled by adjusting one or both of the bias current sources. Outputs of the main and the auxiliary branches may be cross-coupled, to invert a sign of IM3 distortion signals generated via the auxiliary branch. | 12-06-2012 |
| 20120319778 | SEMICONDUCTOR POWER AMPLIFIER - A semiconductor power amplifier of an embodiment includes: a plurality of unit FETs disposed in parallel in a direction of a substantially straight line connecting source electrodes of the unit FETs; a first via hole which connects the two source electrodes positioned between adjacent ones of the unit FETs in common and an RF ground electrode; and a second via hole which connects the source electrode on a side having no adjacent unit FET and the RF ground electrode. Each unit FET includes: a gate electrode which connects gate finger electrodes and leads out the gate finger electrodes; a drain electrode which connects drain finger electrodes disposed facing the gate finger electrodes and leads out the drain finger electrodes ; and two source electrodes which connects source finger electrodes disposed facing the gate finger electrodes and lead out the source finger electrodes to opposing sides in a widthwise direction thereof. | 12-20-2012 |
| 20120319779 | TRANSFORMER AND CMOS POWER AMPLIFIER INCLUDING THE SAME - Disclosed herein is a transformer including: a primary coil formed of a first conductor having a predetermined length and including a first end and second end for receiving a signal, wherein the first conductor is formed as a first loop; and a secondary coil that is coupled to the primary coil in an electromagnetic coupling, and is formed of a second conductor having a predetermined length and including a first end and a second end for outputting a signal, wherein the second conductor is formed as a second loop, wherein the primary coil and the secondary coil are stacked while crossing each other. Accordingly, power transformer efficiency may be increased. | 12-20-2012 |
| 20120326788 | Amplifier Bandwidth Extension for High-Speed Tranceivers - There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit. | 12-27-2012 |
| 20130021102 | HIGH FREQUENCY AMPLIFIER CIRCUIT - A high frequency amplifier circuit includes a first transistor that has a first terminal, a second terminal and a control terminal, the first terminal being grounded, a second transistor that has a first terminal, a second terminal and a control terminal, the control terminal of the second transistor being coupled to the second terminal of the first transistor, the first terminal of the second transistor being coupled to only the second terminal of the first transistor with respect to high frequency wave, the second terminal of the second transistor being coupled to a direct-current power supply, and a first resistor of which first terminal is coupled to a node between the second terminal of the first transistor and the control terminal of the second transistor, and of which second terminal is coupled to the first terminal of the second transistor. | 01-24-2013 |
| 20130033325 | RF POWER TRANSISTOR CIRCUIT - A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a power supply voltage terminal. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the control electrode of the first power transistor and the power supply voltage terminal. The first decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency. | 02-07-2013 |
| 20130049867 | CLASS OF POWER AMPLIFIERS FOR IMPROVED BACK OFF OPERATION - One embodiment of the present invention relates to a power amplifier comprising a plurality of amplifying elements connected in a serial-parallel matrix configuration, containing parallel columns having amplifying elements connected in series. The parallel columns are connected to a common output path coupled to a supply voltage source configured to provide an equal supply voltage to each of the columns. One or more input signals (e.g., RF input signals) are connected to the power amplifier by way of input terminals on a first row of amplifying elements. The remaining amplifying elements have control terminals that are connected to independent control signals, which allow each amplifying element to be operated independent of the other amplifying elements in the matrix. This selective operation of amplifying elements allows for improved efficiency over a wide range of power amplifier output powers. | 02-28-2013 |
| 20130057349 | CMOS POWER AMPLIFIER - There is provided a complementary metal oxide semiconductor (CMOS) power amplifier including: a load unit connected between an operating voltage supply terminal and an output terminal; an amplifying unit formed as a cascode structure between the load unit and a ground, amplifying a power of an input signal input through an input terminal and outputting the amplified signal through an output terminal; and a threshold voltage control unit varying a threshold voltage of the amplifying unit according to a magnitude of the input signal input through the input terminal. | 03-07-2013 |
| 20130076441 | HIGH-FREQUENCY AMPLIFIER - According to one embodiment, a high-frequency amplifier is provided with a field effect transistor for performing amplification, and a stabilizing circuit. The field effect transistor has a source which is configured to be grounded. The stabilizing circuit is connected to a gate of the field effect transistor. The stabilizing circuit has impedance which changes so as to increase as the voltage of a drain of the field effect transistor increases. | 03-28-2013 |
| 20130076442 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed over the substrate; and an amorphous insulating film formed between the substrate and the compound semiconductor stacked structure. | 03-28-2013 |
| 20130076443 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; and a p-type semiconductor layer formed between the electron supply layer and the gate electrode. The p-type semiconductor layer contains, as a p-type impurity, an element same as that being contained in at least either of the electron channel layer and the electron supply layer. | 03-28-2013 |
| 20130076444 | Amplification Circuit, Communication Device, and Transmission Device Using Amplification Circuit - Provided are an amplification circuit capable of amplifying an input signal having a changing duty ratio with high efficiency, and a transmission device and a communication device using the amplification circuit. The amplification circuit includes: a transistor circuit ( | 03-28-2013 |
| 20130082779 | AMPLIFIER - To suppress the occurrence of distortion. There are included an initial-stage amplifier circuit PREA that receives an input signal IN, a first source-grounded transistor Tr | 04-04-2013 |
| 20130093519 | POSITIVE AND NEGATIVE VOLTAGE INPUT OPERATIONAL AMPLIFIER SET - A positive and negative voltage input operational amplifier includes a positive operational amplifier and a negative operational amplifier. Each of the positive operational amplifier and the negative operational amplifier has a reduced layout area and a lowered static current, so that the power consumption is effectively reduced. | 04-18-2013 |
| 20130099865 | LOW-STRESS CASCODE STRUCTURE - An amplifier system comprises a cascode common-source (CS) amplifier including a plurality of transistors connected in a common-source configuration. A stress reducing circuit is connected to at least one of the plurality of transistors to equalize a voltage drop across the plurality of transistors. The stress reducing circuit includes a first transistor including a control terminal, a first terminal and a second terminal. The second terminal of the first transistor is connected to a first terminal of a first one of the plurality of transistors. A capacitance has a first terminal connected to the control terminal of the first transistor and a second terminal connected to a control terminal of a second one of the plurality of transistors. | 04-25-2013 |
| 20130127538 | CMOS INTEGRATED CIRCUIT AND AMPLIFYING CIRCUIT - There is provided a CMOS integrated circuit suppressing gate resistance and preventing increase in noise figure (NF), while an input transistor has a comb structure. The transistor includes: a gate electrode extended from a gate wiring to form a comb shape and receiving an input signal from an input terminal; a source electrode extended from a source wiring facing the gate wiring to form a comb shape and connected to a ground terminal, comb teeth thereof being interposed in every other space between comb teeth of the gate electrode; a drain electrode extended from a drain wiring facing the gate wiring to form a comb shape, comb teeth thereof being interposed in every other space between comb teeth of the gate electrode where the comb teeth of the source electrode are absent, wherein an overlapping region between the gate electrode and the source electrode or the drain electrode is absent. | 05-23-2013 |
| 20130127539 | CMOS INTEGRATED CIRCUIT AND AMPLIFYING CIRCUIT - There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit. | 05-23-2013 |
| 20130135051 | SWITCH WITH REDUCED INSERTION LOSS - A circuit includes an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well. The input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor. | 05-30-2013 |
| 20130229232 | Amplifier Bandwidth Extension for High-Speed Tranceivers - There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit. | 09-05-2013 |
| 20130234797 | Broadband Transistor Bias Network - An amplifying circuit for use in, for example, broadband transceivers is described. A bias filter is connected between an amplifying transistor and a power supply to block a wide range of frequencies associated with amplified RF input signals from reaching the power supply, while permitting DC power to reach the transistor. | 09-12-2013 |
| 20130234798 | AMPLIFIER AND AMPLIFICATION METHOD - An amplifier includes a transformer including a primary coil whose one end is connected to an input port and whose other end is connected to reference potential and a secondary coil magnetically-coupled with the primary coil, and a transistor including a source connected to one end of the secondary coil and a gate connected to other end of the secondary coil and a drain connected to an output port side. | 09-12-2013 |
| 20130257539 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A compound semiconductor device includes a substrate; a buffer layer formed on the substrate; an electron transit layer and an electron donating layer formed on the buffer layer; a gate electrode, a source electrode, and a drain electrode formed on the electron donating layer; and an embedded electrode to which a potential independent of the gate electrode, the source electrode, and the drain electrode is supplied to control a potential of the buffer layer. | 10-03-2013 |
| 20130321082 | SEMICONDUCTOR APPARATUS COMPRISED OF TWO TYPES OF TRANSISTORS - A semiconductor apparatus that includes two types of transistors is disclosed. The first semiconductor chip includes the first semiconductor device of a type of GaAs-HEMT, while, the second semiconductor chip includes the second semiconductor device of another type of GaN-HEMT. The second semiconductor device is formed in a SiC substrate, and the first semiconductor chip is mounted in an inactive region of the SiC substrate. | 12-05-2013 |
| 20140015608 | COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING THE SAME, POWER-SUPPLY UNIT, AND HIGH-FREQUENCY AMPLIFIER - A compound semiconductor device includes: a compound semiconductor multilayer structure including a first buffer layer composed of AlN; and a second buffer layer composed of AlGaN and formed above the first buffer layer, wherein the second buffer layer contains carbon, and wherein the concentration of carbon in the second buffer layer increases with increasing distance from a lower surface of the second buffer layer toward an upper surface of the second buffer layer. | 01-16-2014 |
| 20140015609 | WIDE BANDWIDTH RADIO FREQUENCY AMPLIER HAVING DUAL GATE TRANSISTORS - A wide bandwidth radio frequency amplifier is disclosed. The wide bandwidth radio frequency amplifier has a first signal path having a first input and a first output along with a first dual gate field effect transistor having a first-first gate coupled to the first input and a first drain coupled to the first output. The wide bandwidth radio frequency amplifier also includes a second signal path having a second input and a second output and a second dual gate field effect transistor having a second-first gate coupled to the second input and a second drain coupled to the second output. | 01-16-2014 |
| 20140043100 | OPERATIONAL AMPLIFIER WITH IMPROVED FREQUENCY COMPENSATION - An operational amplifier includes an operational amplifier circuit having at least one output node and an output stage coupled to the output node, the output stage containing an output and first MOS transistor employed in a common source amplifier mode, a frequency compensation capacitor coupled between the output of the output stage and the gate of the first transistor circuit by means of a second MOS transistor employed in a common gate amplifier mode. The other node of the capacitor and the output of the output stage are coupled to the amplifier output node with a resistor. | 02-13-2014 |
| 20140043101 | Method and Apparatus for a Class-E Load Tuned Beamforming 60 GHz Transmitter - The class-E amplifier can be tuned to pass only the fundamental frequency to the antenna by optimizing the second harmonics at the drain of the final PA driver transistor. A CPW in series with a capacitor between the PA transistor and the load forms a band pass filter that only allows the fundamental frequency to pass to the load of the antenna. A supply inductor to couple the drain of the final PA driver transistor to the power supply is tuned at the second harmonic with the parasitic capacitance of the drain of the PA transistor. A load capacitance is adjusted at the fundamental frequency to insure that the current waveform and voltage waveforms at the drain of the PA driver transistor do not overlap, thereby minimizing the parasitic power dissipation and allowing maximum energy to be applied to the antenna. | 02-13-2014 |
| 20140049320 | POWER AMPLIFIER CIRCUIT - A power amplifier circuit, comprising: a final stage, comprising first and second amplifying elements for amplifying an input signal; and a driver stage, for providing the input signal to the final stage. The circuit is characterized by a first capacitor coupled between an input of the first amplifying element and an output of the second amplifying element; and a second capacitor coupled between an input of the second amplifying element and an output of the first amplifying element. | 02-20-2014 |
| 20140062598 | INPUT/OUTPUT SENSE AMPLIFIER - An input/output sense amplifier includes: a data input unit configured to amplify data using a driving voltage and to output the amplified data, and a latch unit configured to latch and output an output signal of the data input unit to an output terminal. | 03-06-2014 |
| 20140070888 | Buffering Apparatus and Method - The output impedance of an amplifier is substantially matched to an input impedance of a receiver using a buffer circuit. The buffer circuit includes a primary transistor and a secondary transistor. A first back gate terminal of the primary transistor is coupled to a second back gate terminal of the secondary transistor and the primary transistor is configured to have an output for the buffer circuit. An input signal is received from the amplifier at a gate terminal of the secondary transistor. The first back gate terminal of the primary transistor is responsively driven independently from the output of the buffer circuit to effectively adjust a transconductance of the primary transistor and substantially match an output impedance of the amplifier with an input impedance of the receiver. | 03-13-2014 |
| 20140077881 | Power Amplifier with Stabilising Network - A power amplifier circuit comprising a transistor for receiving a signal to be amplified at an input and for outputting an amplified signal at an output; a modulated power supply connected to the transistor output; and a resistive element connected at the transistor output such that a low impedance is maintained at the transistor output across a range of operational frequencies. | 03-20-2014 |
| 20140097900 | CIRCUIT AND METHOD FOR BIASING A GALLIUM ARSENIDE (GaAs) POWER AMPLIFIER - A circuit for biasing a gallium arsenide (GaAs) power amplifier includes a reference voltage generator circuit implemented in a gallium arsenide (GaAs) material system, a field effect transistor (FET) bias circuit implemented in the gallium arsenide material system and adapted to receive an output of the reference voltage generator circuit and adapted to provide an output to a radio frequency (RF) amplifier stage. | 04-10-2014 |
| 20140104003 | OPERATIONAL AMPLIFIER CIRCUIT AND METHOD IMPLEMENTING THE SAME - The disclosure provides an operational amplifier circuit, in which a power supply of an amplifying circuit is coupled to a first voltage clamping circuit, and the first voltage clamping circuit clamps a supply voltage of the amplifying circuit when the supply voltage exceeds a normal-operation allowable voltage of the amplifying circuit. The disclosure also provides a method for implementing the operational amplifier circuit. According to the disclosure, the operational circuit may be avoided from subject to an excessive supply voltage, which may damage devices in the amplifying circuit of the operational amplifier. | 04-17-2014 |
| 20140167853 | POWER AMPLIFIER - A first amplifier is connected between an input terminal and an output terminal. A first junction point is located between the input terminal and an input of the first amplifier. A second junction point is located between the output terminal and an output of the first amplifier. A second amplifier is connected in parallel with the first amplifier, between the first junction point and the second junction point. A third junction point is located between an output of the second amplifier and the second junction point. A first capacitor and a switch are connected in series between the third junction point and ground. The second junction point is the lowest impedance point along a power amplification path that includes the input terminal, the first amplifier, and the output terminal. The switch is turned off/on when the second/first amplifier is turned on. | 06-19-2014 |
| 20140176242 | DRIVER AMPLIFIER WITH ASYMMETRICAL T-COIL MATCHING NETWORK - A driver amplifier with asymmetrical T-coil matching network is disclosed. In an exemplary embodiment, an apparatus includes a first inductor configured to receive an input signal at an input terminal and to provide an output signal at an output terminal that is matched to a resistive load. The apparatus also includes a second inductor connected to the first inductor and coupled to the first inductor by a coupling coefficient, the second inductor having a first terminal connected to a supply voltage. | 06-26-2014 |
| 20140197889 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, POWER SUPPLY DEVICE, AND HIGH-FREQUENCY AMPLIFIER - A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; a first insulating film covering the surface of the compound semiconductor stack structure; and a conductive film provided on the surface of the first insulating film. | 07-17-2014 |
| 20140203876 | AMPLIFIER CIRCUIT - An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain terminal of the third field effect transistor; and a control circuit coupled to the gate of the fourth field effect transistor configured to control the source drain voltage of the fourth field effect transistor by means of the gate of the fourth field effect transistor to be equal to a reference voltage. | 07-24-2014 |
| 20140210551 | VARIABLE-CLASS AMPLIFIER, SYSTEM, AND METHOD - A method and generator for modifying interactions between a load and the generator are described. The method includes applying output power to the load using a power amplifier, controlling a level of the output power responsive to a power control setting, and adjusting a conduction angle of the power amplifier to reduce a level of sensitivity of the power amplifier to variations of an impedance of the load. The generator includes a compensation subsystem coupled to the power amplifier that controls a conduction angle of the power amplifier to enable a sensitivity of the power amplifier to be adjusted. | 07-31-2014 |
| 20140253239 | LOW-NOISE SIGNAL AMPLIFYING CIRCUIT AND METHOD THEREOF - A signal amplifying circuit includes: a first transistor having a first connecting terminal coupled to an input signal, and a controlling terminal coupled to a first reference voltage; an adjustable resistive circuit having a first terminal coupled to a second connecting terminal of the first transistor; and a second transistor having a first connecting terminal coupled to a second terminal of the adjustable resistive circuit, a controlling terminal coupled to a second reference voltage, and a second connecting terminal for outputting an output signal corresponding to the input signal; wherein a resistance of the adjustable resistive circuit is adjusted to make an input impedance looking into the first transistor from the first connecting terminal equal a predetermined impedance. | 09-11-2014 |
| 20140253240 | CIRCUIT OF OPERATIONAL AMPLIFIER - A circuit of an operational amplifier includes an operational main circuit, a plurality of current sources, and at least one clamp circuit. The current sources are configured to connect the operational main circuit to a high voltage source or a ground voltage source. The clamp circuit is connected between the operational main circuit and at least one of the current sources. Here, a transistor device connected to the clamp circuit has a crossing-voltage endurance level which is lower than a preset crossing-voltage endurance level of the operational main circuit. | 09-11-2014 |
| 20140253241 | HIGH ELECTRON MOBILITY TRANSISTOR DEVICE - A high electron mobility transistor (HEMT) device includes a buffer layer on a substrate; a face-inversion layer on a part of the buffer layer; a plurality of semiconductor layers on the face-inversion layer and on the buffer layer; and a source electrode, a drain electrode, and a gate electrode on the plurality of semiconductor layers. The HMT device has a stable, normally Off characteristic. | 09-11-2014 |
| 20140266450 | METHOD AND APPARATUS FOR IMPLEMENTING WIDE DATA RANGE AND WIDE COMMON-MODE RECEIVERS - Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency. | 09-18-2014 |
| 20140306761 | POWER AMPLIFIER - A power amplifier includes: first and second bias terminals to which bias voltages are respectively supplied; a first transistor having a first control terminal connected to the first bias terminal, a first terminal that is grounded, and a second terminal; a second transistor having a second control terminal connected to the second bias terminal, a third terminal connected to the second terminal, and a fourth terminal; a capacitor connected between the second control terminal and a grounding point; and a variable resistor connected in series with the capacitor, between the second control terminal and the grounding point. | 10-16-2014 |
| 20140312973 | LOW NOISE AMPLIFIER - Provided is a low noise amplifier. The low noise amplifier includes an input transistor receiving and amplifying a signal, an output transistor amplifying the signal amplified by the input transistor, and an inverting unit inverting the signal which is amplified by the input transistor and applying the inverted signal to a gate of the output transistor. | 10-23-2014 |
| 20140340152 | ADAPTIVE POWER AMPLIFIER AND METHODS OF MAKING SAME - An exemplary embodiment of the present invention provides an adaptive power amplifier comprising a transistor, a resistive load, and a tuning circuit. The transistor has a drain, a source, and a gate. The resistive load can be electrically coupled to the drain. The tuning circuit can be electrically coupled to the drain in parallel with the transistor. The tuning circuit can comprise an inductor and a capacitive element. The inductor and capacitive element can be in series connection. | 11-20-2014 |
| 20150015335 | SENSE AMPLIFIER LAYOUT FOR FINFET TECHNOLOGY - A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier. | 01-15-2015 |
| 20150015336 | CMOS CASCODE POWER CELLS - A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well. | 01-15-2015 |
| 20150015337 | MODULAR APPROACH FOR REDUCING FLICKER NOISE OF MOSFETS - In one example implementation, the present disclosure provides a modular approach to reducing flicker noise in metal-oxide semiconductor field-effect transistors (MOSFETs) in a device. First, a circuit designer may select one or more surface channel MOSFETs in a device. Then, the one or more surface channel MOSFETs are converted to one or more buried channel MOSFETs to reduce flicker noise. One or more masks may be applied to the channel(s) of the one or more surface channel MOSFETs. The technique maybe used at the input(s) of operational amplifiers, and more particularly, rail-to-rail operational amplifiers, as well as other analog and digital circuits such a mixers, ring oscillators, current mirrors, etc. | 01-15-2015 |
| 20150015338 | POWER AMPLIFIER - There is provided a power amplifier capable of readily reducing odd-order harmonic waves even in high frequencies. This power amplifier includes n current sources (where “n” is a natural number equal to or greater than 3) that cause predetermined currents to flow; n switches that open and close current paths of the n current sources, respectively; and a signal generating section that generates n timing signals for turning on/off the n switches, respectively. In the power amplifier, the n timing signals are signals that have an identical duty ratio and that are different in phase; and the power amplifier outputs a signal amplified in power based on the currents flowing through the n current sources. | 01-15-2015 |
| 20150035599 | POWER AMPLIFIER AND DISTRIBUTED FILTER - A system comprises a power amplifier configured to amplify an input signal, a splitter configured to split the amplified input signal into a plurality of output signals, a plurality of filters configured to filter the plurality of output signals, respectively, to produce a plurality of filtered output signals, and a combiner configured to combine the filtered output signals to produce a combined output signal. | 02-05-2015 |
| 20150035600 | AMPLIFIERS WITH CONFIGURABLE MUTUALLY-COUPLED SOURCE DEGENERATION INDUCTORS - Amplifiers with configurable mutually-coupled source degeneration inductors are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) includes a gain transistor and a plurality of inductors, which may implement an amplifier. The gain transistor receives an input signal and provides an amplified signal. The plurality of inductors are mutually coupled, are coupled to the gain transistor, and provide a programmable source degeneration inductance for the gain transistor. The inductors may have a positive coupling coefficient and may provide a larger source degeneration inductance. Alternatively, the inductors may have a negative coupling coefficient and may provide a smaller source degeneration inductance. | 02-05-2015 |
| 20150035601 | SPLIT BIASED RADIO FREQUENCY POWER AMPLIFIER WITH ENHANCED LINEARITY - A radio frequency (RF) power amplifier (PA) may include a first transistor and a second transistor. A first power cell may be coupled with the first transistor, and a second power cell may be coupled with the second transistor. In embodiments, the first transistor may be scaled to operate at a first current density, while the second transistor may be scaled to operate at a second current density. | 02-05-2015 |
| 20150054581 | COMBINATION NMOS/PMOS POWER AMPLIFIER - A combination NMOS/PMOS power amplifier is disclosed. In an exemplary embodiment, the amplifier includes a first amplifier section comprising a first NMOS transistor that is configured to provide a first amplified output and a second amplifier section comprising a first PMOS transistor that is configured to provide a second amplified output. The first PMOS transistor is coupled to the first NMOS transistor at a selected node to reduce capacitance variation at the selected node. | 02-26-2015 |
| 20150061768 | HIGH SPEED AMPLIFIER - A circuit may include one or more transistors connected directly to an output, and an inductance network. The inductance network may connect to a source node of at least one of the transistors, to compensate capacitance of the output. Thus, the response time of the circuit may decrease, and a non-dominant frequency response pole frequency of the circuit may increase. | 03-05-2015 |
| 20150084697 | AMPLIFIER - An amplifier is disclosed that avoids an increase in circuit scale and an increase in power consumption, and easily avoids the odd-order harmonics. This amplifier includes a MOS transistor including a plurality of gate fingers or a plurality of MOS transistors each including a single gate finger; a dielectric capacitor that is added to each of the gate fingers; and a variable resistor that is connected between an input terminal to which an AC signal is input, and a gate input terminal. In the amplifier, the variable resistor, gate resistors of the respective gate fingers, and the dielectric capacitors form a plurality of low pass filters having desired frequency characteristics, and the gate fingers are different from each other in width or length from the gate input terminal to an oxide diffusion (OD) area boundary. | 03-26-2015 |
| 20150084698 | POWER AMPLIFIER CIRCUIT - Linearity and power efficiency in a power amplifier circuit are enhanced. The power amplifier circuit includes a first transistor that amplifies a signal input to the base and that outputs the amplified signal from the collector and a first capacitor that is disposed between the base and the collector of the first transistor and that has voltage dependency of a capacitance value lower than that of a base-collector parasitic capacitance value of the first transistor. | 03-26-2015 |
| 20150116036 | AMPLIFIER CIRCUIT - An amplifier circuit includes: first and second nodes configured to receive input of differential signals; third and fourth nodes; a plurality of first inductors configured to be connected in series between the first and second nodes; a plurality of second inductors configured to be connected in series between the third and fourth nodes; a plurality of field effect transistors configured to have gates each configured to be connected between the plurality of first inductors, sources each configured to be connected to a reference potential node, and drains each configured to be connected between the plurality of second inductors; and a synthesizing unit configured to synthesize signals at the third and fourth nodes. | 04-30-2015 |
| 20150145598 | AMPLIFIER CIRCUIT - An amplifier circuit with at least one basic transistor, at least one load transistor, and at least one impedance element, the basic transistor being connected to the impedance element and the load transistor, an amplifier input and output, the amplifier input being connected to the gate contact of the basic transistor and the amplifier output being connected to a source contact of the load transistor. Here the amplifier circuit has at least two combined amplifying cells, with each combined amplifying cell respectively including a basic transistor, a load transistor, and an impedance element, with the basic transistor and the load transistor being non-complementary single-pin transistors, and arranged cooperating with the impedance element, and every combined amplifying cell has an input and an output, which cell input being connected to a gate contact of the basic transistor and which cell output being connected to a contact of the impedance element. | 05-28-2015 |
| 20150340997 | CASCODE AMPLIFIER - A plurality of source-grounded transistors ( | 11-26-2015 |
| 20160013760 | CIRCUITS AND DEVICES RELATED TO FAST TURN-ON OF RADIO-FREQUENCY AMPLIFIERS | 01-14-2016 |
| 20160072450 | SEMICONDUCTOR AMPLIFIER - A semiconductor amplifier includes a semiconductor amplifying element, an output terminal, an output matching circuit, and an output bias circuit. The output matching circuit includes a bonding wire, a first transmission line, and a second transmission line. The other end part of the first transmission line is connected to one end part of the second transmission line. The output bias circuit includes a third transmission line having an electrical length of approximately 90° at a center frequency, a grounded shunt capacitor, and a power supply terminal. The third transmission line includes one end part and the other end part connected to the grounded shunt capacitor. The one end part of the third transmission line is connected to the second transmission line at a position where an electrical length is approximately 45° from the one end part of the second transmission line at the center frequency. | 03-10-2016 |
| 20160079930 | Low Noise Amplifier - A low noise amplifier includes an amplifier transistor having a source, a gate, and a drain. An input node is coupled to the gate. An output node is coupled to the drain. An inductor is coupled between the gate and the drain. | 03-17-2016 |
| 20160087592 | SINGLE-END AMPLIFIER AND NOISE CANCELLING METHOD THEREOF - A single-end amplifier includes: a noise cancelling circuit, coupled to a power supply, configured to receive a power signal and to cancel a part of ripples and noises in the power signal to generate an initial signal; an amplifying circuit, configure to receive the initial signal at a first end of the amplifying signal, and to amplify the initial signal to generate a first signal at a second end; and a first transmitting circuit, configured to receive the power signal and to generate a second signal at the second end of the amplifying circuit. The first signal and the second signal are superimposed and outputted to cancel most part of the ripples and noises in the power signal. The noise cancelling circuit includes a first capacitor and a first choke coil. | 03-24-2016 |
| 20160197605 | GATE DRIVE CIRCUIT | 07-07-2016 |
| 20190149102 | PHEMT SWITCH CIRCUITS WITH ENHANCED LINEARITY PERFORMANCE | 05-16-2019 |
