| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 329304000 | PHASE SHIFT KEYING OR QUADRATURE AMPLITUDE DEMODULATOR | 23 |
| 20080309403 | Modulation Method with Insertion of Semi-Pilot Symbols - Method and device for modulating a signal comprising data symbols and reference symbols, characterized in that it comprises at least one step ( | 12-18-2008 |
| 20090121787 | Harmonic quadrature demodulation apparatus and method thereof - Disclosed herein is a harmonic quadrature demodulation apparatus and method. The harmonic quadrature demodulation apparatus includes an input terminal for externally receiving an input focused signal, a harmonic phase estimation unit for estimating a second-order harmonic phase component from the input focused signal, and a harmonic detection unit for detecting a second-order harmonic component from the input focused signal. The second-order harmonic detection unit includes an in-phase component extractor, a quadrature component extractor, a Hilbert transformer, an adder and a low pass filter. The in-phase component extractor extracts an in-phase component of the input focused signal. The quadrature component extractor extracts a quadrature component of the input focused signal. The Hilbert transformer Hilbert-transforms a signal transmitted from the quadrature component extractor. The adder receives an output signal of the in-phase component extractor and an output signal of the Hilbert transformer, and adds the two received signals to each other. The harmonic detection unit outputs the second-order harmonic component of the input focused signal. The present invention can extract the harmonic components of an input signal through a single transmission/reception procedure without limiting the bandwidth of a transmission signal. | 05-14-2009 |
| 20090206925 | RECEIVING CIRCUIT AND METHOD FOR RECEIVING AN AMPLITUDE SHIFT KEYING SIGNAL - A receiving circuit and method for receiving an amplitude shift keying signal is provided. At least one exponent signal, an exponent-removed in-phase signal, and an exponent-removed quadrature-phase signal are generated from an in-phase input signal and a quadrature-phase input signal. An amplitude is determined as a sum of several summands, whereby the summands are determined from the exponent signal and/or from the exponent-removed in-phase signal and/or from the exponent-removed quadrature-phase signal (Q′), and wherein the amplitude (A) is demodulated. | 08-20-2009 |
| 20090231028 | TWO-STAGE LOW-COMPLEXITY MAX-LOG BIT-LEVEL LLR CALCULATOR AND METHOD - A demodulator and demodulation method includes a bit/symbol hard demodulator configured to obtain hard bit or symbol information from a received signal. At least one lookup table is configured to reference coefficients for computation of log-likelihood ratios (LLRs) from the hard bit or symbol information. A log-likelihood ratio calculation module is configured to compute bit-level LLRs from the coefficients and the received signal. | 09-17-2009 |
| 20090237155 | GENERATING A PHASE VALUE FOR A COMPLEX SIGNAL - A method of generating a phase value representative of a phase of a complex signal that includes an in-phase component and a quadrature-phase component includes determining a first sign for a first value and a second sign for a second value based on a quadrant occupied by the complex signal. The in-phase component is multiplied by the first value with the first sign, thereby generating a first multiplication result. The quadrature-phase component is multiplied by the second value with the second sign, thereby generating a second multiplication result. The first multiplication result, the second multiplication result, and a bias value are added, thereby generating the phase value for the complex signal. | 09-24-2009 |
| 20100090761 | PSK DEMODULATOR USING TIME-TO-DIGITAL CONVERTER - A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified. | 04-15-2010 |
| 20100109766 | Method and Device for Demodulation of Signals - A method and device are provided for demodulation of an output signal from a transducer ( | 05-06-2010 |
| 20100164615 | System And Method For Relative Phase Shift Keying - Disclosed are various embodiments of systems and methods for relative phase shift keying. In one embodiment, an analog waveform is converted to digital signals. A specified frequency range is isolated and the magnitudes of tones corresponding to a channel are measured. The relative phase of a subset of the tones having the greatest magnitude is measured and a relative phase component is generated. At least one symbol is associated with the subset of tones and the relative phase component. | 07-01-2010 |
| 20100182079 | Low Complexity and Low Power Phase Shift Keying Demodulator Structure - A low complexity and low power phase shift keying demodulator structure comprises: a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler; wherein the digitizer digitizes a BPSK signal for an output waveform, the phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal, the binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor, the sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only small capacitance. | 07-22-2010 |
| 20100225386 | QUADRATURE SIGNAL DEMODULATOR CIRCUITRY SUITABLE FOR DOPPLER ULTRASOUND - Quadrature signal demodulator circuitry for demodulating multiple related input signals into respective pairs of quadrature signals for selective combining to provide a composite pair of quadrature signals with a maximized signal-to-noise ratio (SNR). | 09-09-2010 |
| 20110043276 | Demodulators - Disclosed herein is a demodulator, including: a splitting/matching section for carrying out a matching process of making the amplitude and phase of a first modulated signal match respectively the amplitude and phase of a second modulated signal; and a demodulation section for generating a demodulated signal on the basis of the first modulated signal and the second modulated signal, which have been subjected to the matching process carried out by the splitting/matching section, wherein the splitting/matching section has a splitting section, a first matching section, and a second matching section, the first circuit-element constants determining the first input impedance of the first matching section and the second circuit-element constants determining the second input impedance of the second matching section are set at values determined in advance in order to make the first input impedance equal to the second input impedance. | 02-24-2011 |
| 20110133830 | DEMODULATION CIRCUIT - The circuit ( | 06-09-2011 |
| 20120032737 | ON-CHIP MILLIMETER WAVE LANGE COUPLER - A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler. | 02-09-2012 |
| 20120194266 | Reduction of the Sensitivity to the Jitter Demodulation of the Sampling Clock Signal - The invention relates to a method for the demodulation of a radiofrequency signal (Y), that comprises the steps of: providing a synchronous sampling clock signal (HE) of said radiofrequency signal to be demodulated; sampling said radiofrequency signal using said sampling clock signal; and processing the samples thus obtained in order to determine the phase and/or amplitude of said radiofrequency signal; characterized in that it further comprises the step of adjusting the phase, as measured relative to the sampling clock signal, of said signal to be demodulated and/or of a synchronous reference signal (R) relative to which the signal is demodulated in order to minimize the phase and/or amplitude error generated by a jitter of said sampling clock signal. The invention also relates to a demodulator circuit for implementing said method. | 08-02-2012 |
| 20140062588 | SYSTEM AND METHOD TO DEMODULATE A LOAD MODULATED SIGNAL - A method includes demodulating a load modulated signal at an initiator device based at least partially on a phase adjusted comparison value corresponding to the load modulated signal. | 03-06-2014 |
| 329305000 | Including discrete semiconductor device | 1 |
| 20100237935 | LOGARITHMIC DETECTORS - Disclosed is a logarithmic detector comprising: an amplifier element; means for setting a frequency of operation of the detector; and a controller, wherein an input signal to the amplifier element is arranged to cause an oscillation in the amplifier element, and the controller is operable to sense a pre-determined threshold, indicative of oscillation and, in response to sensing said threshold, to interrupt the oscillation of the amplifier such that the frequency of said interruption is proportional to the logarithm of the power of the input signal. | 09-23-2010 |
| 329306000 | Input signal combined with local oscillator or carrier frequency signal | 6 |
| 20110018626 | QUADRATURE AMPLITUDE DEMODULATOR AND DEMODULATION METHOD - A quadrature amplitude demodulator demodulates a modulated signal on which quadrature amplitude modulation is performed. Oscillators generate an in-phase carrier signal having a rectangular wave, a trapezoidal wave or a waveform similar to these, and a quadrature carrier signal, the phase of which is shifted by ¼ cycle relative to the in-phase signal. First and second mixers respectively perform mixing of the modulated signal with the in-phase signal and the quadrature carrier signal. First and second integrators respectively integrate output signals of the first and the second mixers, for a predetermined period in accordance with the cycle of the in-phase carrier signal and the quadrature carrier signal. First and second A/D converters respectively convert outputs of the first and the second integrators into digital values. | 01-27-2011 |
| 20110043277 | QUADRATURE MODULATION DEMODULATION CIRCUIT - A quadrature demodulation circuit includes: first to fourth mixers to receive a modulation signal; a phase shifter to supply to the first and third mixers a first local frequency signal, to supply to the second mixer a second local frequency signal having a designated phase difference relative to the first local frequency signal, and to supply to the fourth mixer a third local frequency signal that is an inverse in phase to the second local frequency signal; a first adder to add a signal output from the first mixer and a signal output from the second mixer and to output a first demodulation signal; and a second adder to add a signal output from the third mixer and a signal output from the fourth mixer and to output a second demodulation signal. | 02-24-2011 |
| 329307000 | Including phase or frequency locked loop | 4 |
| 20090079497 | PHASE TUNING TECHNIQUES - A differential frequency divider includes first and second input terminals each configured to receive a differential input signal. The divider also includes a first output terminal configured to produce a first output signal and a second output terminal configured to produce a second output signal. The divider further includes a third input terminal coupled to the first output terminal and a fourth input terminal coupled to the second output terminal. In addition, the divider includes a first variable current source. Altering a current of the first variable current source causes a change in the phase difference between a first output signal of the first output terminal and a second output signal of the second output terminal. | 03-26-2009 |
| 20090251207 | ENHANCED POLAR MODULATOR FOR TRANSMITTER - Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two pint modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±π/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +π (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics. | 10-08-2009 |
| 20100277234 | Low Power BPSK Demodulator - A low power BPSK demodulator having a simple architecture, compact design and reliable is provided. The BPSK demodulator includes a first branch ( | 11-04-2010 |
| 20130181770 | PLL CIRCUIT - A PLL circuit, for extracting phase error information from a demodulated signal in which a variance of a phase or an amplitude changes depending on a signal-to-noise power ratio, and providing negative feedback control, to thereby suppress a phase error of the demodulated signal, includes: a phase error detector for producing a phase error signal corresponding to a value of the phase error as the phase error information; a limiter circuit for limiting an expression range of the phase error signal to a constant value or less to produce the limited phase error signal; and a loop filter for producing a control signal based on the limited phase error signal to determine frequency characteristics. | 07-18-2013 |
| 329310000 | Including logic element (e.g., logic gate or flip-flop) | 1 |
| 20090256629 | PHASE DETECTOR FOR HALF-RATE BANG-BANG CDR CIRCUIT - A phase detector, including a sampling device, a comparing device, and an output device, is provided. The sampling device samples a data signal according to a plurality of clock signals, so as to provide a plurality of corresponding sampling values. The clock signals have the same frequency and different phases. The comparing device is coupled to the sampling device, and provides a plurality of corresponding comparison values according to comparison results of each of the sampling values comparing with the next sampling value. The output device is coupled to the comparing device, and outputs two of the comparison values in response to edges of the clock signals. The two outputted comparison values serve as a first instruction signal and a second instruction signal respectively. The first and the second instruction signals are referred to in controlling the frequency and the phase of the foregoing clock signals. | 10-15-2009 |
