| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 329300000 | FREQUENCY SHIFT KEYING OR MINIMUM SHIFT KEYING DEMODULATOR | 6 |
| 20090096519 | CONFIGURABLE DEMODULATOR AND DEMODULATION METHOD - A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison. | 04-16-2009 |
| 20090302935 | DEMODULATOR - According to one embodiment, a threshold adjusting apparatus for a clocked comparator, the clocked comparator comparing an input signal with a threshold in accordance with a clock, the threshold adjusting apparatus comprises an output detection module configured to detect an output from the clocked comparator with the threshold while changing the threshold and a setting module configured to set the threshold when the output detection module detects a change in the output from the clocked comparator as an adjusted threshold. | 12-10-2009 |
| 20120032736 | MODULATOR, DEMODULATOR AND MODULATOR-DEMODULATOR - A modulator, a demodulator and a modulator-demodulator are provided. A modulator includes a first intermediate signal processing path adapted to route a first intermediate signal; a second intermediate signal processing path adapted to route a second intermediate signal; a first amplifier coupled into the first intermediate signal processing path; a second amplifier coupled into the second intermediate signal processing path; and a chopper circuit coupled into the first intermediate signal processing path; wherein the chopper circuit is adapted to process the first intermediate signal in dependence on first baseband data; wherein the first amplifier is adapted to amplify the first intermediate signal processed by the chopper circuit in dependence on second baseband data; and wherein the second amplifier is adapted to amplify the second intermediate signal in dependence on the second baseband data. | 02-09-2012 |
| 329301000 | Including discrete semiconductor device | 1 |
| 20100171550 | Frequency Translation Module Data Clamp - An architecture for processing signal communications between a frequency translation module and an integrated receiver decoder. According to an exemplary embodiment, the signal processing apparatus comprises a demodulator for generating a first signal responsive to an FSK signal, said first signal comprising a varying amplitude and a clamping means for generating a second signal, wherein said second signal has a first value when the amplitude of the first signal is above a predetermined value, and wherein said second signal has a second value when the amplitude is below a second predetermined value. | 07-08-2010 |
| 329302000 | Input signal combined with local oscillator or carrier frequency signal | 1 |
| 20090278596 | Method And System For Communicating Via A Spatial Multilink Repeater - Aspects of a method and system for communicating via a spatial multilink repeater are provided. In this regard, a received signal may be frequency shifted to generate a plurality of repeated signals, wherein each repeated signal may be shifted by a different frequency with respect to the received signal. Each repeated signal may comprise one or more signal components and a phase and/or amplitude of each of the components may be controlled to control a directivity of the repeated signals. Each of the repeated signals may be generated by quadrature down-converting said received signal by mixing the received signal with a first LO signal pair, up-converting the down-converted signal by mixing it with a second LO signal pair, and adding or subtracting an in-phase portion and a quadrature-phase portion of the up-converted signal. | 11-12-2009 |
| 329303000 | Including logic element (e.g., logic gate or flip-flop | 1 |
| 20120212290 | FSK DEMODULATOR - An FSK demodulator and a method for detecting an inflection point extract a greater amount of effective inflection points of a frequency detection signal while reducing erroneous detection of the inflection points. The inflection point detector includes an inflection point extraction part to extract the inflection point corresponding to variation of a sample value of an amplitude value of the frequency detection signal, an amplitude determination part to determine if a size between peak values of sample values in front and rear of the inflection point exists in a first predetermined range, a preamble determination part to determine if a difference between initial and final sample values of at least one of a symbol having the extracted inflection point and a right before symbol exists in a second predetermined range, and an AND operation part to determine a normal inflection point. | 08-23-2012 |
