| Entries |
| Document | Title | Date |
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| 20080204123 | SEMICONDUCTOR DEVICE - A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a conductive state brought by a gate substantially connected to the ground voltage to maintain the low voltage to be substantially at the ground voltage until a possibility that the low voltage rises higher than the ground voltage is eliminated. | 08-28-2008 |
| 20080211572 | REFERENCE VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A reference voltage generating circuit comprises: a monitor circuit, including a low threshold voltage PMOS transistor, a low threshold voltage NMOS transistor, and a resistor having a predetermined resistance which are connected in series, for generating a reference voltage at one end; and an additional circuit for supplying a monitor current to the monitor circuit and for controlling the other end of the monitor circuit to be at a constant voltage, wherein a voltage value of the reference voltage is corrected within a range corresponding to a process fluctuation from a predetermined center value, based on the monitor current changing in response to the process fluctuation. | 09-04-2008 |
| 20080218253 | LOW POWER VOLTAGE REFERENCE - A voltage reference includes a first cell configured to receive a first proportional to absolute temperature (PTAT) current and a second cell configured to receive a second PTAT current. The first cell includes a diode-connected stack of insulated-gate field-effect transistors (IGFETs). The diode-connected stack of IGFETs includes a first transistor that is configured to be biased in a triode weak inversion region. The second cell includes a diode-connected stack of IGFETs and a serially coupled resistor. A magnitude of the second PTAT current is based on a drain-to-source voltage of the first transistor and a value of the serially coupled resistor. The voltage reference provides a reference voltage at a reference node of the second cell based on the second PTAT current. | 09-11-2008 |
| 20080252364 | Reference Voltage Generator for Analog-To-Digital Converter Circuit - To mitigate kickback noise effect, the present invention provides a reference voltage generator for an analog-to-digital converter circuit. The reference voltage generator includes a bias generator, a bias converter and an output unit. The bias generator is used for generating a first bias voltage in accordance with a reference voltage. The bias converter is coupled to the bias generator and is used for converting the first bias voltage to a second bias voltage. The output unit is coupled to the bias converter and used for generating a first voltage to a load circuit in accordance with the second bias voltage. | 10-16-2008 |
| 20080278225 | METHOD AND APPARATUS FOR REGULATING POWER IN A FLYBACK CONVERTER - An integrated circuit includes an operational amplifier configured to receive a current sense voltage (V | 11-13-2008 |
| 20080284503 | Charge Pump Start up Circuit and Method Thereof - The present invention discloses a charge pump start up circuit comprising: a start up transistor having one end which is electrically connected with a voltage supply source, and another end which is electrically connected to a voltage node; and a charge pump circuit having an input which is electrically connected with the voltage node, and an output which is electrically with the gate of the start up transistor. | 11-20-2008 |
| 20080297237 | METHOD FOR COMPENSATION OF PROCESS-INDUCED PERFORMANCE VARIATION IN A MOSFET INTEGRATED CIRCUIT - An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing. | 12-04-2008 |
| 20080297238 | CURRENT SOURCE CIRCUIT - A current source circuit is provided. The circuit includes a first transistor and at least one second transistor. A first source/drain terminal of the first transistor is coupled to a bias voltage. A second source/drain terminal of the first transistor is used to receive a current signal, and the second source/drain terminal of the first transistor is coupled to a gate terminal of the first transistor. A first source/drain terminal of the second transistor is grounded. A second source/drain terminal of the second transistor is coupled to a voltage source and outputs a bias current. A gate terminal of the second transistor is coupled to the gate terminal of the first transistor. | 12-04-2008 |
| 20080315942 | Vt Stabilization of TFT's In OLED Backplanes - In a method of reducing or undoing progressive threshold shift in a thin-film-transistor (TFT) circuit, first and second voltages applied to source and gate terminals of a first transistor cause the first transistor to conduct and apply the first voltage to the gate terminal of the second transistor. The first voltage applied to the gate terminal of the second transistor coacts with a reference voltage coupled to the source terminal of the second transistor via an LED element to cause the second transistor to not conduct whereupon the LED element does not receive electrical power. After a first predetermined period of time sufficient to reduce or undo a progressive threshold shift in the second transistor, the application of the first voltage to the gate terminal of the second transistor is terminated. | 12-25-2008 |
| 20090002064 | CHARGE PUMP CIRCUIT - A reversal charge pump circuit generates a negative voltage from an input voltage received from an input terminal, and provides an output terminal with the negative voltage. The charge pump circuit achieves increased voltage stability and avoids breakdown voltage problems, with an uncomplicated structure. The circuit may have first and second capacitors, first through fourth switches, and a voltage control circuit. The voltage control circuit controls the voltage provided to the first capacitor. The switches are on/off controlled by signals from a control circuit. | 01-01-2009 |
| 20090009237 | Boosting circuit and boosting method - A boosting circuit includes a boosting capacitor to which an input voltage is applied; a smoothing capacitor to which a boosted voltage is applied; a discharging MOS transistor configured to connect said boosting capacitor and said smoothing capacitor in a discharging operation during a boosting operation period such that charge stored in said boosting capacitor is discharged to said smoothing capacitor; and a charging MOS transistor configured to apply the input voltage to said boosting capacitor in a charging operation during the boosting operation period to charge up said charging capacitor. A back gate of said charging MOS transistor and a back gate of said discharging MOS transistor are connected to a common node, and said common node is connected to different voltages in the charging operation and the discharging operation. | 01-08-2009 |
| 20090039951 | INTERNAL POWER SUPPLY CIRCUIT - A disclosed invention is an internal power supply circuit, which generates an internal power supply from a first power supply. The circuit comprises a first internal step-down power supply generation unit, which generates a first internal step-down power supply from the first power supply; a normal second internal step-down power supply generation unit, which generates a second internal step-down power supply from the first internal step-down power supply in the normal operating state, and which, at the time of power supply startup, begins operation to generate the second internal step-down power supply at a first timing at which a voltage of the first internal step-down power supply reaches a prescribed reference level; and, a startup power supply load unit, which begins to consume, before the first time, current from the first internal step-down power supply. | 02-12-2009 |
| 20090045870 | Reference voltage circuit - Provided is a reference voltage circuit whose power supply rejection ratio is large even in a case where a power supply voltage is low. Even in a case where the power supply voltage of a power supply terminal ( | 02-19-2009 |
| 20090051419 | Internal voltage compensation circuit - An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals. | 02-26-2009 |
| 20090058513 | CORE VOLTAGE GENERATION CIRCUIT - A core voltage generation circuit includes a comparator configured to perform a differential comparison of a reference voltage and a feedback core voltage. An amplifier is configured to amplify the external power supply voltage in response to an output signal of the comparator to generate the core voltage. A control switch is configured to form a current path of the comparator using different switch units according to a voltage level of an external power supply voltage input to the core voltage generation circuit. | 03-05-2009 |
| 20090058514 | Semiconductor Device of Power Compensation - According to an aspect of an embodiment, a semiconductor device includes: a reference line; a first line provided with a first voltage with respect to the reference line; a second line provided with a second voltage not less than the first voltage with respect to the reference line; a capacitor having a first capacitance arranged between the reference line and second line; a current limiting element arranged between the capacitor and the second line, for charging up the capacitor, the current limiting element limiting current flowing into the capacitor from the second line during charging up; a first switch connected between the first line and the capacitor; and a controller for controlling the first switch to discharge the capacitor. | 03-05-2009 |
| 20090066410 | CORE VOLTAGE GENERATOR - Core voltage generator including a comparison unit configured to compare a reference voltage with a feedback core voltage to output a difference between the reference voltage and the feedback core voltage, an amplification unit configured to output a core voltage by amplifying an external power supply voltage according to an output signal of the comparison unit and a mute unit configured to maintain a voltage level of an output terminal of the amplification unit at a ground voltage level when the output of the core voltage is interrupted. | 03-12-2009 |
| 20090085654 | Biasing Circuit with Fast Response - A biasing circuit includes a reference current source, a first transistor, a second transistor, and a voltage buffer. The first transistor includes a first connection end coupled to the reference current source, a control end, and a second connection end coupled to a system grounding end. The second transistor includes a control end coupled to the control end of the first transistor, a first connection end coupled to a system power supply end, and a second connection end coupled to the system grounding end. The voltage buffer includes an input end coupled to an output end of the reference current source and the first connection end of the first transistor, and an output end coupled to the control ends of the first transistor and the second transistor. The first transistor and the second transistor constitute a current mirror. | 04-02-2009 |
| 20090096511 | METHOD AND APPARATUS FOR HIGH PERFORMANCE SWITCH MODE VOLTAGE REGULATORS - A circuit configuration for a high power switch-mode voltage regulator circuit is disclosed that includes an array of Metal Oxide Semiconductor (MOS) switching transistors electrically coupled to one another at their drains and sources, and a plurality of gate driver circuits. Each gate driver circuit is coupled substantially close to the gate and dedicated to driving only one MOS switching transistor. | 04-16-2009 |
| 20090128231 | CIRCUITS FOR GENERATING REFERENCE CURRENT AND BIAS VOLTAGES, AND BIAS CIRCUIT USING THE SAME - A circuit for generating a reference current comprises: a first current mirror configured to current-mirror based on a second current, so as to generate a first current that is substantially in inverse proportion to a variation of a power supply voltage; a current compensation unit configured to remove a variation of the first current corresponding to the variation of the power supply voltage to form a compensated first current; a second current mirror configured to generate the second current based on the compensated first current, and configured to provide the second current to the first current mirror; and a current output unit configured to output the second current as the reference current. | 05-21-2009 |
| 20090146731 | REFERENCE VOLTAGE GENERATING CIRCUIT AND POWER SUPPLY DEVICE USING THE SAME - A disclosed reference voltage generating circuit for generating a reference voltage includes MOSFETs connected in series or in parallel. At least one of the MOSFETs includes a control gate and a floating gate that is made hole-rich or discharged by ultraviolet irradiation, and the reference voltage generating circuit is configured to output the difference between threshold voltages of a pair of the MOSFETs as the reference voltage. | 06-11-2009 |
| 20090146732 | Constant Current Source Circuit - The present invention discloses a constant current source circuit with energy saving and over voltage protection to provide a constant current source circuit with less elements, simple circuitry, energy saving and over voltage protection. The present invention includes a regulating circuit ( | 06-11-2009 |
| 20090146733 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit provided with: a transistor M | 06-11-2009 |
| 20090160539 | Voltage reference circuit - A voltage reference circuit comprises a current mirror set, a first resistor, a first MOS transistor, and a second MOS transistor. The output end of the current mirror set is coupled to a first resistor, and the node of the current mirror set is coupled to the first MOS transistor, furthermore, the second MOS transistor is coupled to the first MOS transistor, and the first end and the gate of the second MOS transistor are coupled each other, such that a stable voltage reference will be obtained between the first MOS transistor and the second MOS transistor. | 06-25-2009 |
| 20090160540 | POWER-UP CIRCUIT FOR REDUCING A VARIATION IN TRIGGERING VOLTAGE IN A SEMICONDUCTOR INTEGRATED CIRCUIT - A power-up circuit for reducing a variation in triggering voltage in a semiconductor integrated circuit is described. The power-up circuit includes a pull-up resistor unit that is connected to a power voltage source. A pull-up resistance adjusting unit varies the resistance value of the pull-up resistor unit. The power-up circuit also includes a pull-down resistor unit that is connected between the pull-up resistor unit and a ground. Finally, the power-up circuit includes a detector connected to a common node of the pull-up resistor unit and the pull-down resistor unit. | 06-25-2009 |
| 20090167423 | CPU CORE VOLTAGE SUPPLY CIRCUIT - A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage. | 07-02-2009 |
| 20090167424 | CURRENT CELL CIRCUIT IN DIGITAL-ANALOG CONVERTER - Embodiments relate to a current cell circuit in a digital-analog converter. According to embodiments, a current cell circuit in a digital-analog converter may include a current source connected to a power voltage terminal to generate current having a predetermined magnitude, a first current switch transferring current provided from the current source to a first output terminal, a first current generator detecting output voltage from the first output terminal and generating the amount of reduced current from the detected voltage, and a first current supplier supplying the amount of current generated from the first current generator to the first current switch. According to embodiments, current variations at a constant output voltage may be minimized. This may make it possible to obtain more stable frequency characteristics. | 07-02-2009 |
| 20090189683 | CIRCUIT FOR GENERATING A REFERENCE VOLTAGE AND METHOD THEREOF - A circuit for generating a reference voltage at an output node comprises a first branch, a second branch, and a main current source. The first branch is electrically connected between a first terminal and a second terminal of the circuit, and comprises at least one first semiconductor device. Each first semiconductor device comprises a first node and a second node. The second branch is electrically connected between the first terminal and the second terminal of the circuit, and comprises at least one second semiconductor device and a branch current source. Each second semiconductor device comprises a first node and a second node. The branch current source is serially connected to the second transistor. The main current source is electrically connected to one of the first terminal and the second terminal of the circuit. The output node is in the first branch or the second branch. | 07-30-2009 |
| 20090189684 | Apparatus and Method for Waking up a Circuit - A method for waking up a circuit, comprising charging a voltage line of the circuit with a constant wake-up current until the voltage line reaches a predetermined voltage. Also, an apparatus, comprising a circuit portion, a switch configured to selectively couple an input of the circuit portion to a supply voltage, a current source configured to generate a first current, and a control circuit configured to control a state of the switch depending on the first current. | 07-30-2009 |
| 20090195302 | REFERENCE BUFFER - A reference buffer is disclosed. The reference buffer includes a main source follower stage, a replica source follower stage, and a low-pass filter. The main source follower stage provides a first main voltage according to a first driving voltage. The replica source follower stage duplicates the first main voltage to generate a first reference voltage. The low-pass filter is coupled between the main source follower stage and the replica source follower stage. | 08-06-2009 |
| 20090201080 | CURRENT MIRROR CIRCUIT AND DIGITAL-TO-ANALOG CONVERSION CIRCUIT - A first switched capacitor circuit is connected to the source of one MOS transistor of a current mirror pair configured by a pair of MOS transistors and a second switched capacitor circuit is connected to the source of the other MOS transistor. Each of the first and second switched capacitor circuits includes a capacitor and a switch connected in parallel with the capacitor and the switch is on/off-controlled based on a clock signal of a preset cycle. Each of the first and second switched capacitor circuits equivalently functions as a resistor with large resistance and a variation in the output current of the current mirror circuit based on a variation in the threshold voltages of the pair of MOS transistors can be reduced even if the power source voltage is reduced. | 08-13-2009 |
| 20090201081 | Method and Apparatus for MOSFET Drain-Source Leakage Reduction - A method and apparatus is taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS inverter, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. Exemplary body bias voltage sources are further described that can drive one or more gate transistors of different gate circuits. | 08-13-2009 |
| 20090212854 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 08-27-2009 |
| 20090231025 | Method and Apparatus for Extending the Lifetime of a Semiconductor Chip - A circuit and a method for extending the lifetime of a semiconductor chip. The circuit including a voltage reference generator, a voltage switch, a threshold voltage regulator device and a threshold voltage monitor device tunes an automatic internal power supply. The voltage reference generator provides one or more reference voltage levels that are transmitted to the voltage switch. The threshold voltage monitor device monitors the threshold voltage of the device, triggering the voltage switch to select a reference level for use as a voltage reference for the regulator when the threshold voltage of the monitored device exceeds a predetermined value. The regulator then converts the external power supply to an internal supply and holds it at the predetermined reference level. | 09-17-2009 |
| 20090251204 | Temperature Compensated Work Function Based Voltage Reference - A temperature compensated voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference. The transistor widths of two P-MOS transistors are adjusted to minimize voltage variation over a temperature range. | 10-08-2009 |
| 20090256628 | Reference Current Circuit and Low Power Bias Circuit Using the Same - A reference current circuit has an input configured to receive an input current, a first transistor, a second transistor, and an output configured to provide a reference current. The input is directly connected to a control input of the second transistor and a first terminal of the first transistor, and is connected via a first resistor to a control input of the first transistor. The output is connected to a first terminal of the second transistor. A reference node is connected via a second resistor to the control input of the first transistor, directly to a second terminal of the first transistor and via a third resistor to a second terminal of the second transistor. | 10-15-2009 |
| 20090261896 | LEAKAGE CURRENT SUPPRESSING CIRCUIT AND SEMICONDUCTOR CHIP - A leakage current suppressing circuit includes a bias generating unit and a switch unit. The bias generating unit is adapted to be coupled to a power source and an output terminal, and generates a bias voltage substantially equal to a voltage at the power source when the power source is turned on, and substantially equal to a voltage at the output terminal when the power source is turned off. The switch unit includes a first P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal adapted to be coupled to the output terminal, a gate terminal, and a body terminal coupled to the bias generating unit for receiving the bias voltage therefrom. | 10-22-2009 |
| 20090284309 | POWER SUPPLY VOLTAGE DROPPING CIRCUIT IN WHICH NCH (N-CHANNEL) TRANSISTOR IS USED AS OUTPUT STAGE, SEMICONDUCTOR DEVICE, POWER SUPPLY VOLTAGE CIRCUIT, POWER SUPPLY VOLTAGE DROPPING METHOD, AND POWER SUPPLY VOLTAGE OUTPUTTING METHOD - A device includes an N-channel transistor for output, a voltage raising circuit, a voltage dropping circuit, and an amplifier. A power supply voltage that is a first voltage is supplied to one end of the output N-channel transistor, and the other end of the output N-channel transistor functions as an output terminal. The voltage raising circuit raises the first voltage to generate a second voltage higher than the first voltage. The voltage dropping circuit reduces the second voltage to generate a third voltage that is higher than the first voltage and is lower than the second voltage. The amplifier amplifies the difference between a reference voltage and a voltage generated at the output terminal, using the third voltage as a power supply voltage, to generate a fourth voltage, and supplies the fourth voltage to the gate of the N-channel transistor for output. | 11-19-2009 |
| 20090295466 | METHOD TO REDUCE VARIATION IN CMOS DELAY - Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced. | 12-03-2009 |
| 20090315618 | CURRENT MIRROR CIRCUIT - A current mirror circuit includes a first transistor, a plurality of second transistors whose bases are connected to a base of the first transistor, and a compensation transistor having a gate connected to a collector of the first transistor, a source and a back gate connected to the base of the first transistor and the bases of the plurality of second transistors, and a drain connected to a power source. The first transistor and the plurality of second transistors are bipolar transistors. The compensation transistor is a MOS-type transistor. A current corresponding to a current flowing in the first transistor is permitted to flow in the plurality of second transistors. | 12-24-2009 |
| 20090322417 | SEMICONDUCTOR COMPONENT ARRANGEMENT HAVING A COMPONENT WITH A DRIFT ZONE AND A DRIFT CONTROL ZONE - Disclosed is a semiconductor including a component having a drift zone and a drift control zone. A first connection zone is adjacent to the drift zone and is doped more highly than the drift zone. A drift control zone is arranged adjacent to the drift zone and is coupled to the first connection zone. A drift control zone is dielectric arranged between the drift zone and the drift control zone. At least one rectifier element is arranged between the first connection zone and the drift control zone. A charging circuit is connected to the drift control zone. | 12-31-2009 |
| 20100033237 | Multi-functional drMOS - A DrMOS combines a high side power MOSFET, a low side power MOSFET and a driver circuit for driving the power MOSFETs with current balance and thermal balance mechanism and variable phase control circuit on a single chip. | 02-11-2010 |
| 20100045369 | REFERENCE CURRENT GENERATING CIRCUIT USING ON-CHIP CONSTANT RESISTOR - Provided is a reference current generating circuit capable of maintaining a constant output level regardless of a temperature variation by the use of a reference resistor having a constant resistance regardless of the temperature variation. The reference current generating circuit includes a reference voltage circuit supplying a reference voltage having a constant level regardless of a temperature variation, and a reference resistor circuit comprising a resistor having a positive temperature coefficient and a resistor having a negative temperature coefficient that are connected in series, the reference resistor circuit having a constant total resistance regardless of the temperature variation. Herein, a reference current having a constant level regardless of the temperature variation is generated by the reference voltage and the resistance of the reference resistor circuit. | 02-25-2010 |
| 20100060346 | REFERENCE VOLTAGE GENERATION CIRCUIT - According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first transistor having a first gate, a first source and a first drain; a second transistor having a second gate connected to the first gate, a second source connected to the first source and a second drain; a first diode connected between a ground and a V− node; a first resistor connected between the V− node and the first drain; a second diode and a second resistor connected between the ground and a V+ node; a third resistor connected between the V+ node and the first drain; an operational amplifier including input ports connected to the V+ node and the V− node and an output port connected to the first gate and the second gate; and a fourth resistor connected between the ground and the second drain. | 03-11-2010 |
| 20100060347 | BIAS GENERATOR PROVIDING FOR LOW POWER, SELF-BIASED DELAY ELEMENT AND DELAY LINE - An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation. | 03-11-2010 |
| 20100066441 | MOS with reverse current limiting function and a voltage conversion circuit using the same - A MOS with reverse current limiting function and a voltage conversion circuit using the same is disclosed which employs a resistance unit coupled between a base and a first source/drain of a metal oxide semiconductor (MOS). When a reverse current occurs, a reverse current passing through a body diode of the MOS is limited to prevent the MOS from being burned out due to overheating. Moreover, the voltage level of the base is equal to the voltage level of the first source/drain, such that the Rds (on) of the MOS can be reduced. Therefore, a converter with the disclosed MOS may provide a higher conversion efficiency. | 03-18-2010 |
| 20100085115 | SIGNAL GENERATOR - This invention generally relates to signal generation, clock signal generation and ramp signal generation, and trimming the temperature coefficient of a signal. | 04-08-2010 |
| 20100090755 | Current Limiting Load Switch with Dynamically Generated Tracking Reference Voltage - A current limiting load switch for bridging supply Vss and load with a reference voltage VR | 04-15-2010 |
| 20100102875 | SUBSTRATE NOISE PASSIVE CANCELLATION METHOD FOR BUCK CONVERTER - A method for passive cancellation of substrate noise for a buck converter uses an on-chip capacitor to reduce the substrate noise. The capacitor achieves a close-magnitude noise with opposite phase for better noise cancellation effect in the substrate. The capacitor can be realized as a MOS capacitor, NMOS isolation ring n-well capacitor, n-well junction capacitor, isolated p-well junction capacitor, etc. The capacitor is easy to implement. Further, bond wire parasitic inductance in the buck converter is used to reduce substrate noise. | 04-29-2010 |
| 20100109762 | INTERNAL VOLTAGE GENERATOR - An internal voltage generating circuit includes an internal voltage generating unit configured to generate an internal voltage that corresponds to a target voltage level by driving an internal voltage terminal with an external power supply voltage, and current sinking unit configured to adjust leakage current introduced to the internal voltage terminal in response to the external power supply voltage. | 05-06-2010 |
| 20100109763 | STANDARD VOLTAGE GENERATION CIRCUIT - A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state. | 05-06-2010 |
| 20100123516 | PRECISION CURRENT SOURCE - A device for providing a precision current includes a first operational amplifier and multiple path transistors. The first operational amplifier outputs a gate voltage based on reference voltage and input voltages. The path transistors have corresponding gates for receiving the gate voltage from the first operational amplifier. Each path transistor is connected to a first enable transistor configured to selectively connect the path transistor to a reference path and a second enable transistor configured to selectively connect the path transistor to an output path. The first and second enable transistors are separately enabled by first and second enable signals, respectively. At least one path transistor is connected to the reference path through a corresponding first enable transistor to provide the reference current, and least one other path transistor is connected to the output path through a corresponding second enable transistor to provide the precision current based on the reference current. | 05-20-2010 |
| 20100127765 | DEVICE FOR PROVIDING SUBSTANTIALLY CONSTANT CURRENT IN RESPONSE TO VARYING VOLTAGE - A device for providing a substantially constant current includes first and second current mirrors. The first current mirror receives a first amount of a first bias current and provides an output current based on the first amount of the first bias current, the first bias current being based on a fixed voltage. The second current mirror receives a second bias current and a second amount of the first bias current, the second bias current being based on a variable voltage. The second bias current and the second amount of the first bias current vary directly with variations in the variable voltage, and the first amount of the first bias current varies inversely with variations in the variable voltage. The output current remains substantially constant based on the variations in first amount of the first bias current, which counteract effects on the output current by variations in the second voltage. | 05-27-2010 |
| 20100127766 | Semiconductor apparatus - A semiconductor apparatus includes a first internal voltage generator generating a first internal voltage in response to an external power supply voltage, a second internal voltage generator generating a second internal voltage in response to the external power supply voltage, the second internal voltage is larger in absolute value than the first internal voltage, and a preset signal generating circuit responding to a power-on of the external power supply voltage to the semiconductor apparatus and generating first and second preset signals which bring the first and second internal voltage generators into respective initial states, generation of the second preset signal is stopped after stopping generation of the first preset signal, in which the first internal voltage generator is released from its initial state in response to the stopping the generation of the first preset signal to be allowed to generate the first internal voltage, the second internal voltage generator is released from its initial state in response to the stopping the generation of the second preset signal to be allowed to generate the first internal voltage, and the second internal voltage is generated after generation of the first internal voltage. | 05-27-2010 |
| 20100141334 | Bias circuit scheme for improved reliability in high voltage supply with low voltage device - Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage. | 06-10-2010 |
| 20100141335 | CURRENT MIRROR CIRCUIT, IN PARTICULAR FOR A NON-VOLATILE MEMORY DEVICE - A current mirror circuit is provided with a first current mirror including a first and a second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially floating or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by. | 06-10-2010 |
| 20100148858 | BIAS CIRCUIT - A bias circuit is provided in a circuit including an input line and an output line, and is formed on a substrate that supplies dc power to an active component. The input line reaches an input terminal of the active component from a signal line input terminal to which a signal is inputted, and the output line reaches, from an output terminal of the active component, a signal line output terminal that outputs a signal therefrom. This bias circuit includes: a power supply line supplied with the dc power; a bridge-like metal structure subjected to a bending process, which connects the output line and the power supply line to each other; and a capacitive component provided between a ground and a node between the power supply line and the metal structure. | 06-17-2010 |
| 20100156521 | CONSTANT SWITCH VGS CIRCUIT FOR MINIMIZING RFLATNESS AND IMPROVING AUDIO PERFORMANCE - A MOSFET switch is disclosed that is driven on by a circuit that provides a constant gate to source voltage, Vgs, that is independent of the input voltage, the power supply and any logic signals. The constant Vgs is derived from a reference voltage and biases the MOSFET switch such that Ron is constant, or Rflatness is minimized. A minimized Rflatness provides a higher fidelity transfer of audio signals compared to prior art switches where Rflatness is greater. | 06-24-2010 |
| 20100182076 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device achieving an active state in which a high speed operation is performed and an inactive state in which a low leakage state is retained while an internal logical state is retained, and a transition between the two states can be achieved at high speed with low noise and low power. A power control circuit provided between a first power-supply line for providing a first external power-supply voltage and a second power-supply line for providing a second external power-supply voltage includes an output MOSFET. A constant OFF current flows in the MOSFET even if a gate and a source of the output MOSFET are put in the same voltage, and a threshold voltage of the output MOSFET is smaller than that of an internal circuit MOSFET. | 07-22-2010 |
| 20100207687 | CIRCUIT FOR A LOW POWER MODE - A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes. | 08-19-2010 |
| 20100225384 | REFERENCE CURRENT SOURCE CIRCUIT PROVIDED WITH PLURAL POWER SOURCE CIRCUITS HAVING TEMPERATURE CHARACTERISTICS - A reference current source circuit is provided which is capable of outputting a constant reference current even if surrounding environments such as temperature and power source voltage change in a power source circuit that operates in a minute current region in an order of nanoamperes. The reference current source circuit includes an nMOS-configured power source circuit, a pMOS-configured power source circuit, and a current subtracter circuit. The nMOS-configured power source circuit includes a current generating nMOSFET, and generates a first current having temperature characteristics of an output current dependent on an electron mobility. The pMOS-configured power source circuit includes a current generating pMOSFET, and generates a second current having temperature characteristics of an output current dependent on a hole mobility. The current subtracter circuit generates a constant reference current by subtracting the second current from the first current. | 09-09-2010 |
| 20100237932 | Intermediate potential generation circuit - Provided is an intermediate potential generation circuit with a lower power supply potential. The intermediate potential generation circuit includes: a current mirror circuit including a first transistor and a second transistor each having a source input with a power supply potential; a current source circuit including a third transistor having a drain connected to a drain of the first transistor; a grounded source amplifier circuit including a fourth transistor having a gate input with the intermediate potential, and a drain connected to a drain of the second transistor; a parallel connection circuit including a fifth transistor connected in parallel with the first transistor, and a sixth transistor connected in parallel with the second transistor; and a source follower circuit including a seventh transistor and an eighth transistor having gates that are connected in common to each other, and connected with the drains of the second transistor and the sixth transistor. | 09-23-2010 |
| 20100237933 | CURRENT SUPPLY CIRCUIT - A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being respectively connected to the main terminals of the first to Nth transistors, a pulse width of a signal provided to a control terminal of the respective first to Nth switching transistors being set to be constant regardless of a pulse frequency of the signal. | 09-23-2010 |
| 20100244940 | EXTERNAL COMPENSATION FOR INPUT CURRENT SOURCE - An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit. | 09-30-2010 |
| 20100244941 | COMPENSATION METHOD AND CIRCUIT - A circuit and method for compensating for parasitic elements of a transistor. A transistor, a controller, and a compensation element are mounted to a printed circuit board. The transistor includes parasitic drain and source inductors. The compensation element may be a discrete inductor that has an inductance value equal to about the sum of the inductance values of the parasitic drain and source inductors. The magnitudes of the compensation voltage and the sum of the voltages across the parasitic drain and source inductances are substantially equal. Thus, the compensation voltage developed across the compensation inductor is used to adjust a reference voltage within the controller. A drain-to-source voltage is applied to one input of a comparator within the controller and the adjusted reference voltage is applied to another input of the comparator. An output signal of the comparator is input to drive circuitry that drives a gate of the transistor. | 09-30-2010 |
| 20100259317 | HIGH-OUTPUT-IMPEDANCE CURRENT MIRROR - A current mirror with high output impedance for ensuring high accuracy current output comprises a first calibration circuit, a second calibration, a base circuit, a base current mirror, and an output circuit. The first calibration circuit further comprises plural MOS transistors and a first voltage. The second calibration circuit coupled with the first calibration circuit further comprises plural MOS transistors to calibrate the first calibration circuit. The base current mirror comprising two MOS transistors is coupled with both the first and the second calibration circuits via the base circuit. The output circuit with plural MOS transistors is coupled with the base circuit and the first calibration circuit. Upon an input current flows into the current mirror, the current mirror generates an output current which is several times in intensity than that of the input current. | 10-14-2010 |
| 20100271118 | I/O Buffer with Low Voltage Semiconductor Devices - Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively. | 10-28-2010 |
| 20100277230 | TRANSISTOR JUNCTION DIODE CIRCUITRY SYSTEMS AND METHODS - Methods and apparatus for capacitive voltage division are provided, an example apparatus having an input and an output and including a first switched capacitor circuit. In some embodiments, the capacitive voltage divider includes first and second MOSFETs. A first capacitor is coupled between the drain of the first MOSFET and the input to the capacitive voltage divider. A first circuit coupled to the drain of the first MOSFET is configured to pull down the drain of the first MOSFET and thus apply a reverse bias to a first junction diode internal to the first MOSFET between the drain and the bulk of the first MOSFET. A second capacitor is coupled between the source of the first MOSFET and the drain of the second MOSFET. A second circuit is configured to reverse bias a second junction diode between the drain and bulk of the second MOSFET. | 11-04-2010 |
| 20100289563 | Method and Mechanism to Reduce Current Variation in a Current Reference Branch Circuit - A novel and useful system and method of providing a feedback mechanism to reduce current variation observed in a current reference branch circuit by using body voltage control to compensate process, temperature and supply voltage variations. The current reference output voltage, which is proportional to the reference current, is sampled into a feedback loop, which controls the field effect transistor body voltage. The method and mechanism of the present invention uses Corner Robust Current Reference in order to keep the design simple and diminish variation between Process Voltage Temperature (PVT) corners. This method exhibits superior robustness with smaller variation in the reference current magnitude. | 11-18-2010 |
| 20100289564 | ELECTRONIC DEVICE AND A METHOD OF BIASING A MOS TRANSISTOR IN AN INTEGRATED CIRCUIT - An electronic device has at least one integrated circuit with at least one MOS transistor. An adaptive analog biasing unit is configured to provide an adaptive biasing current for the at least one MOS transistor biased in the saturation region. The adaptive analog biasing unit (AAB) may be on the same chip together with the integrated circuit and may comprise a process monitor unit configure to extract a device parameter of the integrated circuits and a calculation unit configured to generate a bias current based on the output of the process monitor unit. The bias current generated by the calculation unit may be inversely proportional to the extracted device parameter. | 11-18-2010 |
| 20100301927 | BOOSTER CIRCUIT - Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or end of capacitor, voltage applied to or end being at least ½ as great as first supply voltage, and control signal generating circuit sets voltage of control signal when first transistor is de-activated to be first voltage of first node, and sets voltage of control signal when first transistor is activated to be voltage, difference between voltage and first voltage being equal to or smaller than value of first supply voltage. | 12-02-2010 |
| 20110001558 | INTEGRATED CIRCUIT COMPRISING A BROADBAND HIGH VOLTAGE BUFFER - The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port. | 01-06-2011 |
| 20110018621 | CURRENT MIRROR CIRCUIT - The invention relates to a current mirror circuit ( | 01-27-2011 |
| 20110032028 | VOLTAGE VARIATION REDUCING CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME - A voltage variation reducing circuit includes a first transistor and a second transistor. The first transistor is connected to a first power source line of a first power source voltage at a source and a second power source line of a second power source voltage at a drain and a gate. The second transistor is connected to a third power source line of a third power source voltage higher than the second power source voltage at a source and the second power source line at a drain gate. | 02-10-2011 |
| 20110050331 | HIGH VOLTAGE CURRENT SOURCE AND VOLTAGE EXPANDER IN LOW VOLTAGE PROCESS - A high voltage current source and a voltage expander implemented in a low voltage semiconductor process. The voltage expander extends the operating voltage range of a stack of transistors to multiple times a supply voltage Vdd at the output node of the stack without exceeding the breakdown voltage of any of the transistors in the stack. The voltage expander uses a diode and a voltage divider to detect the output node voltage changes and generates a plurality of voltages that control the gate voltages for the stack of transistors. A high voltage wide swing current source utilizes a transistor to set the output current and the voltage expander to extend the output voltage range of the current setting transistor. An additional transistor and another current source ensure that the output current is constant throughout the entire output voltage range between about 0 V and multiple times the supply voltage Vdd. | 03-03-2011 |
| 20110074498 | Electronic Devices and Systems, and Methods for Making and Using the Same - A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 03-31-2011 |
| 20110121891 | ELECTRONIC CONTROL MODULE FOR A JFET TRANSISTOR - An electronic control module for a field effect transistor includes a gate, a drain and a source. The electronic control module includes: a control circuit including: a power supply able to provide a fixed potential to the gate of the field effect transistor; and an amplifier stage able to vary the potential of the source of the field effect transistor with relation to the potential of the gate of the field effect transistor; and a field effect transistor whose gate is connected to the fixed potential; and source is connected to the amplifier stage. | 05-26-2011 |
| 20110140768 | INTERNAL VOLTAGE GENERATOR - An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit. | 06-16-2011 |
| 20110140769 | CIRCUIT FOR GENERATING A REFERENCE ELECTRICAL QUANTITY - A circuit for generating a reference electrical quantity, including: a first bipolar transistor and a second bipolar transistor having the base terminals connected to one another and to a common node; a first resistor connected to the emitter terminal of the second bipolar transistor; a first mirror circuit and a second mirror circuit connected to the first and second bipolar transistors, which receive, respectively, a first current and a second current and generate, respectively, a first mirrored current and a second mirrored current; a first output stage, which generates the reference electrical quantity as a function of the first and second mirrored currents; and a second resistor connected to the common node. The first current is a function of the current in the first resistor, whilst the second current is a function of the current in the second resistor. | 06-16-2011 |
| 20110156808 | INTERNAL VOLTAGE GENERATION CIRCUIT - An internal voltage generation circuit includes a first voltage generation unit configured to be operated in response to a first power enable signal to generate a first voltage, a level detection unit configured to detect a level of the first voltage, and a second voltage generation unit configured to be operated in response to a level detection value outputted from the level detection unit to generate a second voltage lower than the first voltage. | 06-30-2011 |
| 20110163800 | POWER SUPPLY CONTROL CIRCUIT - A power supply control circuit comprises an output transistor | 07-07-2011 |
| 20110187447 | MIXED-MODE CIRCUITS AND METHODS OF PRODUCING A REFERENCE CURRENT AND A REFERENCE VOLTAGE - In an embodiment, a circuit includes a first transistor having a first current electrode, a control electrode, and a second current electrode coupled to a power supply terminal. The circuit further includes a resistive element having a first terminal coupled to the control electrode of the first transistor and a second terminal coupled to the power supply terminal. The circuit also includes a feedback circuit for providing a first current to the first control electrode of the first transistor and for preserving substantially the first current related to a voltage at the control electrode of the first transistor, through the resistive element. The feedback circuit includes an output terminal for providing an output signal in response to a voltage at the control electrode of the first transistor. In an embodiment, the first transistor is a floating-gate device with programmable threshold voltage. | 08-04-2011 |
| 20110199154 | AUTOMATIC LEVEL CONTROL - Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage. | 08-18-2011 |
| 20110204964 | LEAKAGE CURRENT CONTROL CIRCUIT - A leakage current control circuit includes a solid state switch that is operable to control a flow of AC to a load. The switch exhibits an AC leakage current in an OFF state. A capacitor is connected in parallel to the load, and is operable to repeatedly charge during a first half cycle of the leakage current and to discharge during a second half cycle of the leakage current. The capacitor charge includes a DC component in response to the leakage current through the solid state switch being greater in a first direction than in a second direction opposite the first direction. A first resistor is connected in parallel to the load. The capacitor and the first resistor prevent a voltage buildup across the load from exceeding a voltage threshold. | 08-25-2011 |
| 20110204965 | Apparatus and Method Pertaining to Facilitating a Measurement with Respect to Field Effect Transistor - These various embodiments pertain to an FET having a plurality of fingers as correspond to the FET's source and drain. A first conductive lead electrically couples to a given one of this plurality of fingers while a second conductive lead electrically couples as well to this same given finger. A measurement component connects to these first and second conductive leads to measure at least one electrical parameter (such as voltage). By one approach, the first and second conductive leads physically connect to opposing ends of the given finger. These teachings will also accommodate providing a control component that is responsive to the measurement component to facilitate automatically controlling at least one operating state of the FET as a function, at least in part, of the measured electrical parameter. | 08-25-2011 |
| 20110204966 | Transistor junction diode circuitry systems and methods - Methods and apparatus for capacitive voltage division are provided, an example apparatus having an input and an output and including a first switched capacitor circuit. In some embodiments, the capacitive voltage divider includes first and second MOSFETs. A first capacitor is coupled between the drain of the first MOSFET and the input to the capacitive voltage divider. A first circuit coupled to the drain of the first MOSFET is configured to pull down the drain of the first MOSFET and thus apply a reverse bias to a first junction diode internal to the first MOSFET between the drain and the bulk of the first MOSFET. A second capacitor is coupled between the source of the first MOSFET and the drain of the second MOSFET. A second circuit is configured to reverse bias a second junction diode between the drain and bulk of the second MOSFET. | 08-25-2011 |
| 20110221517 | REFERENCE CURRENT GENERATING CIRCUIT - A reference current generating circuit has: first and second current mirror circuits and first and second output terminals. The first current mirror circuit has: a first transistor of a first polarity being an input-side transistor; and a first resistor connected between a gate of the first transistor and a power supply terminal. The second current mirror circuit has a second transistor of a second polarity being an input-side transistor. An output node of the first current mirror circuit is connected to an input node of the second current mirror circuit, and an input node of the first current mirror circuit is connected to an output node of the second current mirror circuit. A control voltage applied to the gate of the first transistor is output from the first output terminal. A control voltage applied to a gate of the second transistor is output from the second output terminal. | 09-15-2011 |
| 20110241769 | INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR INTEGRATED CIRCUIT - An internal voltage generator of a semiconductor integrated circuit includes a comparison unit configured to compare a reference voltage with a feedback voltage, a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit, and a feedback unit configured to divide a voltage of the internal voltage terminal according to a division ratio adjustable in response to a control signal and output a division voltage as the feedback voltage. | 10-06-2011 |
| 20110254617 | SEMICONDUCTOR DEVICE - A semiconductor device includes a reduced-power-consumption circuit block which includes first and second power lines, and a first circuit cell. The first circuit cell includes a first functional-element-free region. The first functional-element-free region includes a first driver circuit configured to connect and disconnect the first power line and the second power line. | 10-20-2011 |
| 20110260784 | DECOUPLING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes. | 10-27-2011 |
| 20110279174 | IMPEDANCE TRANSFORMATION WITH TRANSISTOR CIRCUITS - In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit. | 11-17-2011 |
| 20110285457 | Multi-Level Transmitter Circuit Having Substantially Constant Impedance Output - A multi-level transmitter circuit with substantially constant output impedance has a capacitive transducer connected between a voltage input and ground. A first voltage path connects the voltage input to a first positive voltage source. The first voltage path is controlled by a first control signal. A second voltage path connects the voltage input to a second positive voltage source, less than the first positive voltage source. The second voltage path passes through a diode and is controlled by a second control signal. A third voltage path connects the voltage input to a third voltage source, less than ground, and is controlled by the second control signal. The impedance at the voltage input during the first control signal is substantially the same as the impedance at the voltage input during the second control signal. | 11-24-2011 |
| 20110291747 | VOLTAGE GENERATION CIRCUIT - A voltage generation circuit includes: a first and second rectification circuits; and one or more amplification units connected between the first and second rectification circuits and configured to amplify an output of the first rectification circuit and provide the amplified output to the second rectification circuit. The second rectification circuit generates a reference voltage. | 12-01-2011 |
| 20110316620 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 12-29-2011 |
| 20120007665 | CMOS IMAGE SENSOR - A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor. | 01-12-2012 |
| 20120019312 | RECYCLING CHARGES - A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised. | 01-26-2012 |
| 20120062312 | CONSTANT CURRENT CIRCUIT - This package manufacturing method is a method for manufacturing a package using a rivet having a flat plate-shaped head portion and a core portion protruding from a rear surface of the head portion. The package includes: a plurality of substrates that are bonded to each other: a cavity that houses an object to be housed in an airtightly sealed state; the core portion which is disposed in a through hole that penetrates a base substrate and which electrically connects the object to be housed with the outside; and a glass frit that is filled between the through hole and the core portion and is fired to form a seal between the though hole and the core portion. The package manufacturing method includes: a rivet disposing step of inserting the core portion into the through hole until the rear surface of the head portion comes into contact with a first surface of the base substrate; a glass frit filling step of filling the glass frit in a paste form between the through hole and the core portion; and a firing step of integrally fixing the through hole, the rivet and the glass frit by firing the filled glass frit, and sealing between the through hole and the core portion. A gas relief passage, which leads from a base end of the core portion to a side surface or a front surface of the head portion, is formed on the rear surface of the head portion of the rivet. | 03-15-2012 |
| 20120062313 | TRANSISTOR SUBSTRATE DYNAMIC BIASING CIRCUIT - A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage. | 03-15-2012 |
| 20120086503 | CONSTANT CURRENT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a constant current circuit, a drain terminal is connected to an output terminal of a current, and a gate voltage operable in a saturation region is applied to a source-grounded transistor. An increase current generating circuit generates an increase current equivalent to an increase of a current due to a channel length modulation effect of the transistor. A current mirror circuit generates a current having the same value as that of the increase current generated by the increase current generating circuit and supplies the generated current to the drain terminal of the transistor. | 04-12-2012 |
| 20120092064 | Temperature-Stable CMOS Voltage Reference Circuits - A temperature stable comparator circuit, comprised of: a branch C having a first end, a second end, a first type- | 04-19-2012 |
| 20120105142 | SEMICONDUCTOR APPARATUS AND METHOD OF TRIMMING VOLTAGE - A semiconductor apparatus includes: a master chip and at least one slave chip configured to be stacked one on top of another; and a through-silicon via (TSV) configured to penetrate and electrically couple the master chip and the at least one slave chip, wherein the at least one slave chip receives a reference voltage generated from the master chip via the TSV and independently trims the reference voltage and then generates an internal voltage with the trimmed reference voltage. | 05-03-2012 |
| 20120112822 | DIFFERENTIAL INPUT FOR AMBIPOLAR DEVICES - Differential input pairs have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional designs for differential input pairs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transistors, or other ambipolar transistors. Here, a differential input pair has been provided that uses ambipolar transistors, which accounts for the more unusual I-V (drain current to gate-source voltage) characteristics of ambipolar transistors. | 05-10-2012 |
| 20120112823 | METHOD TO MATCH SOI TRANSISTORS USING A LOCAL HEATER ELEMENT - An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. | 05-10-2012 |
| 20120119825 | CIRCUIT FOR NEGATIVE BIAS TEMPERATURE INSTABILITY COMPENSATION - An integrated circuit device includes a first circuit for providing current to a first node, and a degradation compensator including a first compensation circuit coupled to the first node to provide compensation current to the first node. The degradation compensator is operable to estimate a degree of degradation in the first circuit and provide a compensation signal to the first compensation circuit to control the amount of compensation current based on the estimated degree of degradation. | 05-17-2012 |
| 20120119826 | Semiconductor integrated circuit for minimizing a deviation of an internal power supply from a desired value - A semiconductor integrated circuit includes first and second external terminals receiving an external power supply voltage, an internal power supply line coupling to the first and second external terminals, a first transistor coupling between the first external terminal and the internal power supply line, a second transistor that is coupled between the second external terminal and the internal power supply line, a first monitor line coupling to a first node of the internal power supply line, a second monitor line coupling to a second node of the internal power supply line, the second node being different from the first node, and a controller coupling to the first and second monitor lines, the controller outputs a control signal corresponding to potentials of the first and second monitor lines to the first and second transistors. | 05-17-2012 |
| 20120154026 | INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE - An integrated circuit ( | 06-21-2012 |
| 20120154027 | APPARATUS - An impendence tuning apparatus is disclosed. The impendence tuning apparatus includes an operation amplifier, a reference resistor, a tuned resistor, a switching module, a current generator, a current detector and a controller. A first input terminal of the operation amplifier receives a basic voltage and the second terminal of the operation amplifier coupled to a first end. The switching module receives a control and coupled the first end to the tuned resistor or the reference resistor accordingly for generating a tuned current or a reference current separately. The current generator receives and mirrors the reference current or the tuned current to generate a first current and a second current. The current detector receives the first and the second currents and outputs current values the first and the second currents to the controller. The controller tunes an impendence of the tuned resistor according to the first and the second currents. | 06-21-2012 |
| 20120154028 | BIAS CIRCUIT AND ANALOG INTEGRATED CIRCUIT COMPRISING THE SAME - Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time. | 06-21-2012 |
| 20120154029 | PMOS RESISTOR - Provided is a PMOS resistor. The PMOS resistor includes a PMOS transistor pair, a switching unit, and a negative feedback unit. The PMOS transistor pair is symmetrically connected between first and second nodes. The switching unit compares a voltage of the first node and a voltage of the second node to output one of the voltages of the first and second nodes. The negative feedback unit receives an output of the switching unit to control a current which flows in the PMOS transistor pair, for maintaining a constant resistance value. | 06-21-2012 |
| 20120161860 | MULTI-LEVEL CONTROL FOR PASS TRANSISTOR GATE VOLTAGE - A circuit for selectively providing a signal from a source to a sink is provided. The circuit includes a field effect transistor having a conducting state and a non-conducting state, the field effect transistor having a gate, a source, and a drain. The circuit also includes a first comparator configured to provide a first output based on a difference between a source voltage at the source of the field effect transistor and a first reference voltage. Finally, the circuit includes a switching amplifier configured to apply a first gate voltage to the gate of the field effect transistor as a function of the first output of the first comparator. | 06-28-2012 |
| 20120161861 | CAPACITOR CELL SUPPORTING CIRCUIT OPERATION AT HIGHER-VOLTAGES WHILE EMPLOYING CAPACITORS DESIGNED FOR LOWER VOLTAGES - An integrated circuit (IC) includes a functional circuit and a capacitor cell. The functional circuit may operate with one of two power supply voltages. The capacitor cell is used to provide power supply decoupling for the functional circuit, and includes multiple capacitors, each designed to withstand a maximum voltage equal to the lower of the two power supply voltages. When the functional circuit is to operate with the higher of the two power supply voltages, the capacitors in the capacitor cell are coupled in a series arrangement between power supply and ground terminals of the IC. When the functional circuit is to operate with the lower of the two power supply voltages, the capacitors in the capacitor cell are coupled in a parallel arrangement between the power supply and ground terminals. In an embodiment, the functional circuit is an input-output (I/O) circuit powered by 1.8V or 3.3V power supplies. | 06-28-2012 |
| 20120176189 | REDUCED SWING SIGNAL - A circuit includes an inverter. The inverter inverts an input signal having an input low voltage level and an input high voltage level to form an output signal having an output high voltage level and an output low voltage level. Compared to the input high voltage level, the output high voltage level is lowered. Alternatively or additionally, compared to the input low voltage level, the output low voltage level is raised. | 07-12-2012 |
| 20120182065 | RESISTIVE DIVIDER CIRCUIT AND VOLTAGE DETECTION CIRCUIT - A resistive divider circuit capable of preventing an increase in trimming error under a particular condition by eliminating the effects of on resistances of switch elements, and a voltage detection circuit of high precision are provided. The resistive divider circuit includes a plurality of resistance elements connected in series, the resistance elements having weighted resistance values, and switch elements connected in parallel with the respective resistance elements, where it is configured such that ratios between the resistance values of the resistance elements and resistance values of the corresponding switch elements in a shorted state are constant. | 07-19-2012 |
| 20120200345 | INTEGRATED CIRCUIT HAVING POWER GATING FUNCTION AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An integrated circuit includes a logic circuit and a power gating circuit. The logic circuit generates an output signal based on an input signal and a first power supply voltage in a normal operation mode, and maintains a voltage level of the output signal as a stand-by logic level based on a second power supply voltage in a stand-by mode. A magnitude of the second power supply voltage is smaller than a magnitude of the first power supply voltage. The power gating circuit entirely applies the first power supply voltage to the logic circuit based on a power gating signal in the normal operation mode, and partially applies the second power supply voltage to the logic circuit based on the power gating signal in the stand-by mode. | 08-09-2012 |
| 20120206194 | POLARITY SWITCH CIRCUIT FOR CHARGER - A polarity switch circuit for a charger is disclosed. The circuit includes a polarity switch unit and an input control unit. The polarity switch unit includes an input end, an output end, a correct-direction connecting circuit, and a reverse-direction connecting circuit. The correct-direction connecting circuit has a first switch unit and a second switch unit. When the load is plugged correctly, the positive input node is connected to the positive output node by the first switch unit, and the negative input node is connected to the negative output node by the second switch unit. The reverse-direction connecting circuit includes a third switch unit and a fourth switch unit. When the load is plugged reversely, the positive input node is connected to the negative output node by the third switch unit, and the negative input node is connected to the positive output node by the fourth switch unit. | 08-16-2012 |
| 20120223767 | TWO-STAGE POST DRIVER CIRCUIT - A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress. | 09-06-2012 |
| 20120229200 | GATE DRIVE CIRCUIT AND POWER SEMICONDUCTOR MODULE - A gate drive circuit capable of operating at high speed and with low loss without erroneously operating the switching element is provided with a small number of components and a simple and easy circuit configuration. A primary side of a transformer is connected to an output terminal of a low-side gate drive circuit, and a secondary side of the transformer is connected to a gate input side of a high-side switching element. As a positive gate drive voltage is output from the low-side drive circuit, a negative voltage is applied between the gate and source of a high-side switching element, and a gate voltage is suppressed to be equal to or lower than a threshold value. Therefore, the high-side switching element maintains a turn-off state when the low-side switching element is turned on. | 09-13-2012 |
| 20120249227 | VOLTAGE LEVEL GENERATOR CIRCUIT - A voltage level generator circuit comprised of a fixed voltage generator unit for generating a first electrical current in a fixed quantity from a first supply voltage; a first current mirror circuit unit including a first thin-film NMOSFET and a second thin-film NMOSFET and that outputs a second electrical current proportional to the first electrical current; a protective circuit including: a third thin-film NMOSFET and a first thick-film PMOSFET utilized as a grounded gate for protecting the second thin-film NMOSFET, a first diode for preventing inverse current flow to the first supply, and a second diode for preventing the gate-source voltage of the third thin-film NMOSFET from reaching a negative electrical potential; and a second current mirror circuit for outputting a third electrical current proportional to the second electrical current; and a first Zener diode unit for generating a first fixed voltage from a third electrical current. | 10-04-2012 |
| 20120293245 | VOLTAGE REDUCING CIRCUIT - A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage. | 11-22-2012 |
| 20120326772 | Integrated circuit with power gating - An integrated circuit includes a main power rail, a ground power rail as well as a virtual main power rail and a virtual ground power rail. Combinatorial logic circuitry is connected to draw its power from the virtual main power rail and the virtual ground power rail. Signal value storage circuitry is connected to draw its power from one of the main power rail and the ground power rail with the other power connection being to a virtual rail. The integrated circuit has an operational mode, a retention mode and a power off mode. In the retention mode, the voltage difference across the combinatorial logic circuitry is a low power voltage difference insufficient to support data processing operations whereas the voltage difference across the signal value storage circuitry is higher and is sufficient to support signal value retention within the signal value storage circuitry. | 12-27-2012 |
| 20130027123 | Voltage regulation of a virtual power rail - A voltage regulator for regulating a voltage level of a virtual power rail supplying power to logic circuitry in a low power data retention mode is disclosed. The voltage regulator comprises: switching circuitry having a transistor for coupling said virtual power rail to a power supply having a supply voltage level; control circuitry responsive to a signal indicating the logic circuitry is to enter the low data power retention mode to control the switching circuitry to switch to a conductive state in which the transistor is operating in a saturation region of operation and supplying a saturation current from the power supply via the virtual power rail to the logic circuitry; and a leakage power controller for adjusting a voltage level of the virtual power rail to control leakage power. The leakage power controller is configured to supply a bias voltage to the well in which the switching circuitry is formed, the saturation current of the switching circuitry being dependent on a value of the well bias voltage. The leakage power controller is configured to adjust the well bias voltage of the switching circuitry thereby varying the saturation current and the voltage level of the virtual power rail. | 01-31-2013 |
| 20130027124 | ELECTRONIC COMPARISON CIRCUIT - An electronic circuit includes a differential input section, a current mirror section, an operational amplifier, an inverter, and a compensation voltage generator. The differential input section and the current mirror section are coupled together, forming a first common drain node and a second common drain node. The current mirror section has two p-type transistors coupled together at a common gate node. The operational amplifier has a positive input coupled to the first common drain node, a negative input coupled to the compensation voltage generator, and an output coupled to the common gate node. The inverter has an input node coupled to the second common drain node. The compensation voltage generator provides a compensation voltage to replicate a switching threshold voltage of the inverter. | 01-31-2013 |
| 20130049847 | BOOTSTRAPPING TECHNIQUES FOR CONTROL OF CMOS TRANSISTOR SWITCHES - Techniques to provide bootstrap control of a CMOS transistor switch. The techniques may include driving a control terminal of a CMOS transistor switch to a first predetermined voltage to set the CMOS transistor switch to an off-state. The first predetermined voltage may be drained to a discharge voltage and the control terminal may be driven to a second predetermined voltage to set the CMOS transistor switch to an on-state. The control terminal may be driven to the first predetermined voltage to return the CMOS transistor switch to the off-state. | 02-28-2013 |
| 20130057336 | SOLID-STATE IMAGE SENSOR DEVICE AND DIFFERENTIAL INTERFACE THEREOF - A solid-state image sensor device comprises an image sensor section for outputting analog signals of an image being taken; a plurality of AD converter sections, arranged with respect to the column direction of the image sensor section, for converting the analog signals into digital signals; a drive circuit section for controlling the image sensor section and the AD converter sections; and a plurality of differential interface sections for transmitting the digital signals converted by the AD converter sections as differential output signals to an external device. Each of the differential interface sections comprises a current value changeover circuit and offset voltage holding circuit operative when an operation mode changeover is made. | 03-07-2013 |
| 20130069715 | PSRR IN A VOLTAGE REFERENCE CIRCUIT - Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node. | 03-21-2013 |
| 20130088287 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING ANALOG SWITCH - A semiconductor device has an analog switch, in which a P channel transistor and an N channel transistor are connected in parallel between an input terminal and an output terminal; a variable voltage circuit, which variably generates, according to an input voltage applied to the input terminal, potentials of a first gate voltage and first back gate voltage of the P channel transistor and of a second gate voltage and second back gate voltage of the N channel transistor; and a control circuit, which supplies to the variable voltage circuit a control signal controlling the analog switch to be conducting or non-conducting. In response to the control signal causing the analog switch to be conducting, the variable voltage circuit outputs the variable-generated first gate voltage and second gate voltage to the respective gates of the P channel transistor and N channel transistor. | 04-11-2013 |
| 20130147546 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes an internal voltage input buffer configured to determine voltage levels of a pull-up driving node and a pull-down driving node as a result of a comparison between a voltage level of an internal voltage node and a voltage level of a reference voltage node such that the pull-up driving node and the pull-down driving node to maintain a voltage level difference, and an internal voltage driving block configured to pull-up drive the internal voltage node in response to the voltage level of the pull-up driving node and pull-down drive the internal voltage node in response to the voltage level of the pull-down driving node. | 06-13-2013 |
| 20130162342 | REFERENCE VOLTAGE GENERATOR OF SEMICONDUCTOR INTEGRATED CIRCUIT - A reference voltage generation circuit for a semiconductor integrated circuit includes a first reference voltage generation unit configured to generate a reference voltage in mode other than a self-refresh mode, and a second reference voltage generation unit configured to additionally drive an output terminal of the first reference voltage generation unit in an initial reference voltage setting period. | 06-27-2013 |
| 20130194033 | SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, DRIVER CIRCUIT, LEVEL SHIFTER, AND DISPLAY DEVICE - A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off. | 08-01-2013 |
| 20130200944 | VOLTAGE SWITCHING CIRCUITRY, INTEGRATED DEVICE AND INTEGRATED CIRCUIT, AND METHOD OF VOLTAGE SWITCHING - A voltage switching circuitry comprises a switching arrangement with a given number N of switches in series between a first terminal receiving a first voltage and a second terminal receiving a second voltage. The first voltage level is higher than the second voltage level, and N is at least equal to 2. A voltage-by-N divider, having N−1 output taps, is arranged to divide the first voltage by N to a scaled down version of the first voltage having a voltage level below voltage max ratings of the switches. The N−1 output taps of the divider are arranged to respectively output N−1 third voltages having respective levels staged below the first voltage level. N−1 max voltage generators generate N−1 fourth voltages, respectively equal to the maximum of the second voltage and of each of the N−1 third voltages. A switch control unit generates N control signals using the N−1 fourth voltages. These N control signals have respective voltage levels staged between the first voltage level and the second voltage level. In addition, each of the N control signals controls one of the switches of the switching arrangement, respectively. | 08-08-2013 |
| 20130271209 | SEMICONDUCTOR DEVICE - A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously. | 10-17-2013 |
| 20130278328 | POWER TRANSISTOR PARTIAL CURRENT SENSING FOR HIGH PRECISION APPLICATIONS - A power transistor module including a power transistor with a first common power node, and a split control node. A first clip is connected to a portion of a second power node so that current through a first control segment of the control node is directed through a first transistor portion and through the first clip. A second clip is connected to another portion of the second power node so that current through a second control segment is directed through a second transistor portion and through the second clip. A ratio of an area of the first transistor portion to a combined area of the first and second portions is 5 percent to 75 percent. A shunt is coupled in series to the first clip. The shunt may be directly electrically connected to the first portion of the power transistor. | 10-24-2013 |
| 20130321073 | Power Supply Circuit with Positive and Negative Feedback Loops - A circuit includes a gate node, and a bias circuit coupled to the gate node. The bias circuit is configured to, in response to a change in a gate voltage on the gate node, provide a positive feedback to the gate voltage. A power circuit is coupled to the gate node, wherein the power circuit includes a power Metal-Oxide-Semiconductor (MOS) transistor. The power circuit is configured to, in response to a change in the gate voltage, provide a negative feedback to the gate voltage. An output node is coupled to the power circuit. | 12-05-2013 |
| 20130328621 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit is provided. First and second voltage generation units generate a first voltage and a second voltage with respect to a temperature rise, respectively. First and second current generation units generate a first current and a second current having a negative characteristic with respect to a temperature rise in response to a voltage comparison signal, respectively. A voltage comparison unit compares a voltage level of a first current transfer node with a voltage level of a second current transfer node and generates the voltage comparison signal according to the comparison result. A reference voltage output unit is connected in series to the second voltage generation unit and outputs a reference voltage maintaining a set level, without regard to a temperature variation, in proportion to a third current generated in response to the voltage comparison signal. | 12-12-2013 |
| 20130342266 | IMPEDANCE TRANSFORMATION WITH TRANSISTOR CIRCUITS - In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit. | 12-26-2013 |
| 20140070878 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a voltage monitor circuit; a storage circuit storing an output target characteristic value of the voltage monitor circuit; a comparator configured to compare the output characteristic value of the voltage monitor circuit and the target characteristic value; and a switch control circuit configured to control the number of the plurality of turned-on discrete supply switches based on the comparison result of the comparator. | 03-13-2014 |
| 20140070879 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a delay monitor circuit having a delay path whose amount of delay changes in accordance with a change in the voltage value of the local power source, and whose output logical value changes in accordance with the amount of delay of the delay path; and a switch control circuit configured to control the number of the plurality of discrete supply switches based on the output logical value of the delay monitor circuit. | 03-13-2014 |
| 20140077871 | POWER SUPPLY FOR LOCALIZED PORTIONS OF AN INTEGRATED CIRCUIT - System and method system for regulating voltage in a portion of an integrated circuit. An integrated circuit has a voltage input and at least a portion that is less than all of the integrated circuit, which requires a local voltage level. A voltage selector establishes a target voltage for the portion. A first comparator compares the target voltage to the local voltage and generates a pull up control signal when the local voltage is below the target voltage. A second comparator compares the target voltage to the local voltage and generates a pull down control signal when the local voltage is above the target voltage. A pull up device, responsive to the pull up control signal, increases the local voltage according to the pull up control signal. A pull down device, responsive to the pull down control signal, decreases the local voltage level according to the pull down control signal. | 03-20-2014 |
| 20140084994 | Current Limiting Circuitry and Method for Pass Elements and Output Stages - Circuitry ( | 03-27-2014 |
| 20140084995 | ENVELOPE DETECTOR WITH ENHANCED LINEAR RANGE - An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED. | 03-27-2014 |
| 20140097889 | INTERFACE CIRCUIT - An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage. | 04-10-2014 |
| 20140132338 | METHOD FOR PROVIDING A SYSTEM ON CHIP WITH POWER AND BODY BIAS VOLTAGES - Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected. | 05-15-2014 |
| 20140152382 | RECONFIGURABLE SWITCHED-CAPACITOR VOLTAGE CONVERTER CIRCUIT, INTEGRATED CIRCUIT (IC) CHIP INCLUDING THE CIRCUIT AND METHOD OF SWITCHING VOLTAGE ON CHIP - A configurable-voltage converter circuit that may be CMOS and an integrated circuit chip including the converter circuit and method of operating the IC chip and circuit. A transistor totem, e.g., of 6 or more field effect transistors, PFETs and NFETs, connected (PNPNPN) between a first supply (V | 06-05-2014 |
| 20140167839 | NEGATIVE VOLTAGE REGULATION CIRCUIT AND VOLTAGE GENERATION CIRCUIT INCLUDING THE SAME - A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division. | 06-19-2014 |
| 20140184318 | POWER SUPPLY CIRCUITRY - The invention concerns power supply circuitry for controlling a power-up phase of an islet of an integrated circuit, the circuitry having: a switch ( | 07-03-2014 |
| 20140197884 | ON-CHIP PORT CURRENT CONTROL ARRANGEMENT - A port current control arrangement, constituted of: a current source arranged to generate a reference current or a predetermined value; an on-chip reference resistor, the generated reference current arranged to produce a reference voltage across the on-chip reference resistor; an on-chip sense resistor, a port current arranged to flow through the on-chip sense resistor and produce a sense voltage across the on-chip sense resistor, wherein the resistance of the on-chip sense resistor exhibits a predetermined relationship with the resistance of the first on-chip reference resistor; and a current control circuit, a first input of the current control circuit arranged to receive the produced reference voltage and a second input of the current control circuit arranged to receive the sense voltage, wherein the current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage. | 07-17-2014 |
| 20140266414 | INTERNAL VOLTAGE GENERATOR AND CONTACTLESS IC CARD INCLUDING THE SAME - A voltage generator of a contactless integrated circuit (IC) card includes a regulator configured to generate a first internal voltage based on an input voltage and a first reference voltage, the input voltage being received through an antenna of the contactless IC card. The voltage generator includes an internal voltage generator configured to generate a second internal voltage, the second internal voltage being used to operate an internal circuit of the contactless IC card. The voltage generator includes a reference voltage generator configured to generate a second reference voltage based on the first internal voltage, the second reference voltage being generated without regard to a fluctuation component of the first internal voltage. The voltage generator includes a switching unit configured to provide one of the first and second internal voltages as the first reference voltage in response to first and second switching control signals. | 09-18-2014 |
| 20140306752 | DC-DC Converter With Adaptive Phase Compensation Controller - A DC-DC converter for generating an output voltage from input voltage, includes: an output stage for outputting the output voltage; an error amplifier having an input and a reference input for receiving a feedback voltage at the input in accordance with the output voltage and for receiving a reference voltage at the reference input, the error amplifier generating an amplified voltage for driving the output stage, the amplifier voltage corresponding to the difference between the feedback voltage and the reference voltage; a phase compensation unit for generating a phase compensation component to the feedback voltage; and a phase compensation controller for controlling the phase of the phase compensation unit; wherein the feedback voltage determined by the output voltage plus said phase compensation component. | 10-16-2014 |
| 20140312963 | SWITCHABLE CURRENT SOURCE CIRCUIT AND METHOD - a switchable current source in which a reference voltage value to be used in driving the gate of an output transistor is sampled and stored. The reference voltage is derived using a reference current source which feeds a current sensing transistor. The current sensing transistor is turned off when the output transistor is turned off, so that the reference current source then does not consume power. A large reference current Iref can then be used for a short time. | 10-23-2014 |
| 20140333371 | POWER BOOSTING CIRCUIT FOR SEMICONDUCTOR PACKAGING - A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element. | 11-13-2014 |
| 20140361828 | DIGITAL POWER GATING WITH PROGRAMMABLE CONTROL PARAMETER - An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter. | 12-11-2014 |
| 20150028943 | RECONFIGURABLE POWER SWITCH CHAINS FOR EFFICIENT DYNAMIC POWER SAVING - Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode. | 01-29-2015 |
| 20150035591 | Low-Noise Reference Voltages Distribution Circuit - A low-noise reference voltages distribution circuit ( | 02-05-2015 |
| 20150042401 | PASSING HIGH VOLTAGE INPUTS USING A CONTROLLED FLOATING PASS GATE - An input receiver includes a first pass transistor coupled between an input pad and an internal receiver node. The first pass transistor includes a controlled floating gate capacitively coupled to the input pad. A source follower transistor couples between the internal receiver node and a power supply. A gate for the source follower transistor couples to the input pad. | 02-12-2015 |
| 20150097615 | Operating And Manufacturing A DC-DC Converter - Manufacturing a DC-DC converter on a chip includes: providing a die having a p-type top side and an n-type bottom side; removing an interior portion, creating a hole; flipping the interior portion; inserting the interior portion into the hole; fabricating high-side switch cells in the interior portion's top side and low-side switch cells in the exterior portion's top side; sputtering a magnetic material on the entire top side; burrowing tunnels into the magnetic material; and applying conductive material on the magnetic material and within the tunnels, electrically coupling pairs of high-side and low-side switches, with each pair forming a micro-power-switching phase, where the conductive material forms an output node of the phase, and the conductive material in the burrowed tunnels forms, in each phase, a torodial inductor with a single loop coil and, for the plurality of phases, a directly coupled inductor. | 04-09-2015 |
| 20150137881 | High-Voltage-Tolerant Pull-Up Resistor Circuit - A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input/output (I/O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage. | 05-21-2015 |
| 20150295563 | INTERFACE CIRCUIT - An interface circuit comprises a first integrated circuit to transmit or receive data, a second integrated circuit connected to the first integrated circuit by a transmission line to transmit or receive data, and a constant current generating circuit connected to the transmission line so as to output a current of a constant magnitude to the transmission line. The constant current generating circuit adjusts the amount of current outputted to the transmission line by sensing a voltage level of the transmission line. | 10-15-2015 |
| 20150303313 | SEMICONDUCTOR MEMORY DEVICE EMPLOYING A FERROMAGNETIC GATE - A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device. | 10-22-2015 |
| 20150326217 | Integrated Circuit Comprising a Clamping Structure and Method of Adjusting a Threshold Voltage of a Clamping Transistor - An integrated circuit comprises a load transistor including first and second load terminals and a load control terminal. The integrated circuit further comprises a clamping structure. The clamping structure comprises a clamping transistor, the clamping transistor including first and second clamping transistor load terminals and a gate terminal. The clamping transistor is electrically coupled between the load control terminal and the first load terminal and a clamping voltage of the load transistor is determined by a threshold voltage Vth of the clamping transistor. | 11-12-2015 |
| 20150355665 | NEGATIVE REFERENCE VOLTAGE GENERATING CIRCUIT AND NEGATIVE REFERENCE VOLTAGE GENERATING SYSTEM USING THE SAME - A negative reference voltage generating circuit includes a clamp-type reference voltage circuit and a differential amplifier. The clamp-type reference voltage circuit is connected between a node of a first negative voltage which is equal to or lower than the ground voltage and a node of a second negative voltage which is lower than the first negative voltage, and is formed by connecting a first circuit and a second circuit in parallel. The differential amplifier amplifies the difference between a node voltage in the first circuit and a node voltage in the second circuit, and outputs a negative reference voltage. | 12-10-2015 |
| 20150372679 | PVT Compensation Scheme for Output Buffers - In one integrated circuit embodiment, a programmable pull-down output buffer is calibrated by sequentially configuring the buffer at different drive-strength levels and adjusting a source current applied to the buffer until the voltage at an input node of the buffer reaches a reference voltage level. A programmable pull-up output buffer is then calibrated by sequentially configuring a pull-down output buffer based on the pull-down buffer calibration results and adjusting the drive-strength level of the pull-up buffer until the voltage at a common node between the two buffers reaches a reference voltage level. Average calibration results are generated by averaging multiple calibration results for each setting. Output buffers are thereby calibrated to compensate for PVT variations without using any external resistors and without requiring any I/O pins of the integrated circuit. | 12-24-2015 |
| 20160013792 | Circuit and Method for Detection and Compensation of Transistor Mismatch | 01-14-2016 |
| 20160112042 | Gate Leakage Based Low Power Circuits - A low power voltage divider facility using gate leakage characteristics to divide voltage levels of sub-threshold and near-threshold circuits. The divider comprises a gate leakage based divider facility, and, optionally, a capacitive divider facility. | 04-21-2016 |
| 20160141304 | METHOD TO MATCH SOI TRANSISTORS USING A LOCAL HEATER ELEMENT - An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. | 05-19-2016 |
| 20160149486 | INPUT-OUTPUT CIRCUITS - A circuit comprises a first circuit and a second circuit. The first circuit is configured to operate at a first-circuit supply voltage value, and to generate a first reference voltage value based on a voltage rated for transistors in a second circuit. The second circuit is configured to operate at a second-circuit supply voltage value, to receive a first signal and the first reference voltage value, and to clamp an input node of the second circuit based on the first reference voltage value. The second-circuit supply voltage value is less than the first-circuit supply voltage value. The first signal is configured to swing between a low voltage value and a voltage value higher than the second-circuit supply voltage value. | 05-26-2016 |
| 20160170933 | TRACKING CIRCUIT AND METHOD | 06-16-2016 |
| 20160179122 | DISTRIBUTED POWER DELIVERY SCHEME FOR ON-DIE VOLTAGE SCALING | 06-23-2016 |
| 20180026580 | SWITCHED CAPACITOR CIRCUIT STRUCTURE WITH METHOD OF CONTROLLING SOURCE-DRAIN RESISTANCE ACROSS SAME | 01-25-2018 |
