| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327392000 | Delay controlled switch (e.g., fixed, single time of delay control, etc.) | 64 |
| 20080224756 | DIGITAL PULSE-WIDTH MODULATOR BASED ON NON-SYMMETRIC SELF-OSCILLATING CIRCUIT - A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also not characteristic for other architectures. | 09-18-2008 |
| 20090066402 | GATE DRIVE CIRCUIT - A gate drive circuit includes a turn-on side circuit for turning on a gate of a power switching device, the turn-on side circuit including a first turn-on side power supply circuit and a second turn-on side power supply circuit, the first turn-on side power supply circuit including: a first turn-on voltage source for supplying a first turn-on voltage; first turn-on wiring; and a first turn-on switch connected in the first turn-on wiring and controlled by a gate drive signal; and the second turn-on side power supply circuit including: a second turn-on voltage source for supplying a second turn-on voltage applied to the gate of the power switching device to set the power switching device in a steady (on) state; second turn-on wiring; a second turn-on switch connected in the second turn-on wiring; and a turn-on side delay circuit for delaying the gate drive signal and passing it to the second turn-on switch. | 03-12-2009 |
| 20090237141 | Timing Control Apparatus - The present invention discloses a timing control apparatus to control the on/off timing of the voltage sources. The timing control apparatus includes a plurality of delay circuits coupling with the voltage sources, a plurality of discharging circuits coupling with the delay circuits and a plurality of switches coupling with the discharge circuits. | 09-24-2009 |
| 20100156503 | ELECTRONIC CIRCUIT DEVICE - An electric circuit device operable under a power supply includes: a circuit; a first switch connected between the power supply and the circuit; a capacitor tending to produce a first leakage current; a second switch connected between the power supply and the capacitor, the second switch producing a second leakage current when it is cut off, the second leakage current being less than the first leakage current; and a switch controller for turning on the second switch while both the first switch and the second switch are turned off, and after a first time passes for turning on the first switch. | 06-24-2010 |
| 20110068850 | CIRCUIT FOR CONTROLLING TIME SEQUENCE - A circuit for controlling time sequence of an electronic device, the circuit comprises a delay unit to receive a first control signal, a first switch unit connected to the delay unit to receive the first control signal after a rising edge of the first control signal, a second switch unit to promptly receive the first control signal in response to a falling edge of the first control signal, and a voltage output unit connected to the first and second switch units. The voltage output unit is selectively controlled by the first or the second switch unit to output a second or a third control signal to turn on or off the electronic device. | 03-24-2011 |
| 20120044011 | INITIATING FORCED SHUTDOWN OF A DEVICE - A method comprises initiating generation of a feedback signal in response to determining that an input has been selected throughout a first predetermined period of time and initiating a forced shutdown of a device in response to determining that the input has been deselected within a second predetermined period of time after the initiating of the generation of the feedback signal. | 02-23-2012 |
| 20120092059 | LOW SUPPLY NOISE POWER STAGE ARRANGEMENT FOR A SWITCH REGULATOR - In a general aspect, an apparatus can include a first switch configured to be coupled to a power source and configured to switch in response to an edge of a control signal. The apparatus can include delay circuit can be configured to produce a delay signal that has an edge corresponding to the edge of the control signal, the edge of the delay signal being offset from the edge of the control signal. The apparatus can also include a second switch can be configured to be coupled to the power source in parallel with the first switch and configured to switch in response to the edge of the delay signal, the second switch having a size smaller than a size of the first switch. | 04-19-2012 |
| 20120256677 | Controlled large signal capacitor and inductor - An electrical resonance network comprising a first capacitor and a first inductor whose resonance frequency can be tuned by means of a second capacitor and/or a second inductor. The resulting effective capacitor- or inductor value of a network period is controlled by a variable coupling respectively decoupling interval by means of at least one coupling switch. The coupling respectively decoupling interval is synchronized by a sign change of a current and/or voltage in the network. | 10-11-2012 |
| 327393000 | With variable or multiple adjustable time of delay control (e.g., variable charge-discharge, on-delay/off-delay control, etc.) | 14 |
| 20090085643 | Power Distribution Current Limiting Switch Including A Current Limit Blanking Period Providing A Burst of Current - A method for operating a current limit power switch for supplying power to a load include activating the power switch to start supplying power to the load; limiting the current drawn by the power switch to a first current limit for a first, fixed duration; after the first, fixed duration, limiting the current drawn by the power switch to a second current limit for a second duration where the second current limit is less than the first current limit; and after the second duration, limiting the current drawn by the power switch to a third current limit where the third current limit is less than the second current limit. | 04-02-2009 |
| 20150035585 | REVERSE CONDUCTION MODE SELF TURN-OFF GATE DRIVER - An apparatus includes a switch module, a sense circuit coupled to the switch module and configured to indicate an operating conduction mode of the switch module, and a drive circuit operatively coupled to the switch module to enable and disable forward conducting mode of the switch module. Once the switch module is in forward conducting mode, the drive circuit is configured to maintain enablement of the forward conducting mode even if the sense circuit indicates reverse conduction mode. | 02-05-2015 |
| 20150318849 | GATE DRIVING CIRCUIT AND DRIVING METHOD THEREOF - A gate driving circuit and a driving method thereof are provided. The gate driving circuit includes a control signal generator and at least one gate channel set, each of the at least one gate channel set includes a plurality of gate channels, and the plurality of gate channels share a level shifter. The driving method includes generating a plurality of first control signals and a plurality of second control signals according to a gate driver start pulse, and determining that one of the gate channels uses the level shifter during a time period according to the plurality of first control signals and the plurality of second control signals. Therefore, the number of the level shifters can be decreased. | 11-05-2015 |
| 327394000 | With field-effect device | 8 |
| 20090085644 | Integrated Circuit - An integrated circuit includes an input terminal for applying an input signal, a further input terminal for applying a further input signal having a level differing from the level of the initial input signal, an output terminal for providing an output signal, a switching unit having a controllable switch, which is arranged between the input terminal and the output terminal, and a further switching unit, which is arranged between the further input terminal and the output terminal. The integrated circuit is operated in a first and subsequent second operating state. The controllable switch of the switching unit is controlled to be conductive in the first and second operating state. In the first operating state, the output signal is provided in dependence on the level of the input signal, and in the second operating state in dependence on the level of the second input signal. | 04-02-2009 |
| 20090278589 | Method and Apparatus for Propagation Delay and EMI Control - An output switch driving capability booster which may effectively reduce a propagation delay in an output switch with an independently controllable output transition change rate. A delay controller coupled to the output switch may be used to control the propagation delay. The delay controller may have a switch which may be switched on and off approximately simultaneously with the output switch, and a resistance device which may be adjusted to reduce the propagation delay. | 11-12-2009 |
| 20130009689 | Circuit and Method For Dynamic Biasing of an Output Stage - A circuit includes a delay circuit, a transition detector, a pre-driver circuit, and a controller. The delay circuit includes an input for receiving a signal and an output for providing a delayed version of the signal. The transition detector is coupled to the input of the delay circuit to detect a transition within the signal and to provide a look ahead signal to a detector output. The pre-driver circuit includes an input coupled to the output of the delay circuit, a control input, at least one signal output, and a plurality of a bias outputs. The controller is coupled to the detector output and to the control input of the pre-driver circuit and is configured to control bias signals on a plurality of bias outputs to selectively increase a driving strength of signals and biases applied to an output stage in response to the look ahead signal. | 01-10-2013 |
| 20130162323 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a clear period, transistors NT | 06-27-2013 |
| 20140118052 | SHIFT REGISTER AND GATE DRIVING CIRCUIT THEREOF - An Nth shift register includes a pull up unit, a driving unit, a first pull down unit, a second pull down unit, and a third pull down unit. The pull up unit is used for providing a first pull up signal according to a first clock signal, a second clock signal, and a starting pulse. The driving unit is used for providing a driving signal according to the first pull up signal and providing a gate signal according to the first clock signal and the driving signal. The first pull down unit is used for pulling down the first pull up signal according to the first clock signal. The second pull down unit is used for pulling down the driving signal according to a second pull up signal. The third pull down unit is used for pulling down the gate signal according to the second clock signal. | 05-01-2014 |
| 20150015321 | Circuit and Method for Controlling Charge Injection in Radio Frequency Switches - A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated. | 01-15-2015 |
| 20150048876 | SEMICONDUCTOR CIRCUIT - Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal corresponding to the clock signal while a signal level of at least one of the enable signal and the sense enable signal is at the first level, when the semiconductor circuit is in a low-voltage mode. | 02-19-2015 |
| 20150102851 | METHOD, CONTROL UNIT AND SWITCHING DEVICE FOR SWITCHING A CYCLE IN A POWER TRANSISTOR CIRCUIT - A method for switching a cycle in a power transistor circuit is created, especially in a parallel circuit of power transistors. The method includes the step of specifying a switching time difference and the switching of the power transistors of two switching times which are separate from one another by use of the switching time difference. | 04-16-2015 |
| 327396000 | With plural switching elements (e.g., sequential, etc.) | 3 |
| 20080224757 | METHOD AND APPARATUS FOR REDUCING SIMULTANEOUS SWITCHING OUTPUTS - The disclosure provides a method for reducing an amount of simultaneous switching outputs (SSO) of a device. The method of reducing the amount of simultaneous switching outputs can include driving outputs of the device to a first set of values, scrambling a second set of values to reduce an amount of simultaneous switching outputs resulting from the switching of the first to the second set of values, and driving the outputs of the device to the scrambled second set of values. Further, the method can include descrambling the scrambled second set of values back to the second set of values. | 09-18-2008 |
| 20100148847 | HIGH-POWER SWITCHING MODULE AND METHOD FOR THE GENERATION OF SWITCHING SYNCHRONISM IN A HIGH-POWER SWITCHING MODULE - A high-power switching module for directly feeding pulse energy to a load includes a plurality of series-connected switching stages. Each switching stage includes a semiconductor switch; a snubber capacitor and a synchronizing resistor; and a control network configured to act on the semiconductor switch and to be supplied with auxiliary power and switching pulses from a pulse driver so as to influence a switching of the semiconductor switch. The control network includes at least one control resistor, a control diode, an auxiliary diode, an auxiliary capacitor configured to decouple and store the auxiliary power so as to maintain an offset voltage at the semiconductor switch, and an adjustable time-delay element series connected to the control diode and connected in parallel with the control resistor. The adjustable time-delay element is configured to variably set the offset voltage for the semiconductor switch that determines the switching of the semiconductor switch. | 06-17-2010 |
| 20130285734 | DELAY COMPENSATION CIRCUIT | 10-31-2013 |
| 327398000 | For predetermined time period | 15 |
| 20080218245 | SOLID-STATE SWITCH - A solid state switch that employs a controller driven input and MOSFET power switching devices is disclosed. The controller can test for a short-circuit on the load side of the MOSFET power switching devices before putting the switch in a sustained conductive state. | 09-11-2008 |
| 20080265976 | COMPUTER APPARATUS AND SWITCH CONTROL METHOD THEREOF - A computer apparatus includes a switch, a signal generating part which generates a signal corresponding to a position of the switch, a system part which receives the generated signal and operates, and a controller to control the signal generating part so that the signal generated in the signal generating part can be prevented from being applied to the system part for a predetermined period of time, if the switch moves from a first position to a second position. | 10-30-2008 |
| 20080278215 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention is a semiconductor device for driving and controlling a power device in the high-potential side of two power devices connected in series between a main power source potential of a high potential and a main power source potential of a low potential, and is equipped with a pulse generating circuit for generating first and second pulse signals corresponding to the level transition to first and second states of input signals having a first state showing the conduction of the power device in the high-potential side and a second state showing the non-conduction of the power device in the high-potential side, respectively; a level shift circuit for obtaining first and second level-shifted pulse signals by level-shifting the first and second pulse signals to the high-potential side; an SR-type flip-flop circuit inputting the first level-shifted pulse signals from set input terminal and the second level-shifted pulse signals from reset input terminal; and a delay circuit for delaying the output of the SR-type flip-flop circuit by at least the pulse width of the first and second pulse signals. | 11-13-2008 |
| 20090066403 | EMC PROTECTION CIRCUIT - A protection circuit for protecting an electronic circuit against EMC disturbances and/or negative transient overvoltage pulses comprises a switch in series between a power supply and the electronic circuit to be protected; a comparator for comparing a first operating parameter with a second operating parameter and producing a comparison signal, the comparison signal being used as a control signal for controlling opening and closing of the switch; and a delay circuit adapted for delaying closing of the switch. A corresponding method is also provided. | 03-12-2009 |
| 20090091371 | TOUCH SENSOR CONTROLLED SWITCH WITH INTELLIGENT USER INTERFACE - A module for controlling power supply to a load in a product which includes a microchip, and an electromechanical switch and a proximity/touch sensor connected to the microchip, preferably to the same input. The switch is primarily used to activate or deactivate the load and the proximity/touch sensor to vary the effect of operating the switch, or to control additional functions such as the activation of a signal, typically a light signal, which helps to locate the product, particularly in the dark, and to vary the duration of an automatic time-out period at the end of which the load is deactivated. | 04-09-2009 |
| 20090153224 | CIRCUIT FOR TURNING ON MOTHERBOARD - An exemplary circuit for turning on a motherboard comprises a first switch module comprising a first terminal arranged to receive a standby power and connected to a sixth terminal of a computer front panel header, a second terminal arranged to receive the standby power, and a control terminal; a timing circuit charged by a system power; and a second switch module comprising a first terminal connected to the control terminal of the first switch module via the timing circuit, a second terminal arranged to receive the standby power, and a control terminal arranged to receive the system power, wherein, when the system power is lost, the second switch module discharges the timing circuit for turning on the first switch module after a discharge time, and the motherboard is turned on when the first switch module is turned on to ground the sixth terminal of the computer front panel header. | 06-18-2009 |
| 20100219877 | POWER CONVERTER - Provided is a power converter having a switching circuit wherein a surge voltage of a plurality of switching elements connected in series is suppressed and loss is not concentrated to a specific switching element. The switching circuit is provided with: a non-latching type switching element having two main terminals and one control terminal; a voltage detecting means which detects a voltage applied between the main terminals of the switching element; a control current supply for supplying the control terminal with a control signal corresponding to the voltage detected by the voltage detector; and a delay device for delaying the control signal. | 09-02-2010 |
| 20100321087 | ELECTRONIC DEVICE WITH OPTICAL MODULE - An electronic device includes an optical module, a power source module powering the optical module, a processor, a controller, and a switch module. The processor generates and maintains a delay signal for a first predetermined time in response to determination that the power source module is powered on. The processor further generates a driving signal upon determination that the first predetermined time has elapsed. The controller generates and maintains a control signal for a second predetermined time in response to determination that the power source module is powered on. The switch module is turned on to establish an electrical connection between the power source module and the optical module according to the driving signal, and turned off to cut off the electrical connection according to the control signal. | 12-23-2010 |
| 20120086496 | ELECTRONIC DEVICE WITH SWITCHING ELEMENT DRIVEN BY CONTROL VOLTAGE - In an electronic device with a switching element, a control circuit controls the voltage at the control terminal of the switching element and drives the switching element, by controlling an ON-drive switching element and an OFF-drive switching element based on an inputted drive signal to the control circuit. The control circuit is configured to turn OFF a switching element using a switching circuit other than the OFF-drive switching element after an elapse of a predetermined period of time from a timing at which the drive signal switches from an ON instruction thereof to an OFF instruction thereof, the ON instruction giving an instruction to turn ON the switching element, the OFF instruction giving an instruction to turn OFF the switching element. | 04-12-2012 |
| 20120119814 | POWER OFF CIRCUIT AND ELECTRONIC DEVICE - A power off circuit includes a switching unit, a detecting unit, a power management unit, a delay unit, and a control unit. The switching unit is connected to a power source. The detecting unit detects whether the switching unit is turned off and generates a detecting signal when detecting that the switching unit is turned off. The power management unit receives a supply voltage from the power source and provides an operating voltage to at least one functional module. The control unit signals the at least one functional module to be ready for being powered off according to the detecting signal. The delay unit generates a control signal after a predetermined time period from a time point when the switching unit is turned off, the power management unit stops providing the operating voltage to the at least one functional module according to the control signal. | 05-17-2012 |
| 20120249213 | ALTERNATE POWER GATING ENABLEMENT - Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches. | 10-04-2012 |
| 20150022258 | TRANSISTOR SWITCH INCLUDING INDEPENDENT CONTROL OF TURN-ON AND SLEW RATE - The disclosed transistor switching methodology enables independent control of transistor turn-on delay and slew rate, including charging, during a pre-charge period, a transistor control input to a threshold voltage V | 01-22-2015 |
| 20150061749 | GATE DRIVER - A gate driver is provided. The gate driver amplifies an input control signal to drive gates of high and low side transistors. A high side driving chip amplifies a high side control signal for controlling the high side transistor and outputs the amplified high side control signal to the gate of the high side transistor. A low side driving chip amplifies a low side control signal and outputs the amplified low side control signal to the gate of the low side transistor. An emitter terminal of the gate of the high side transistor is connected to a collector terminal of the low side transistor. The high side driving chip is separately prepared from the low side driving chip. | 03-05-2015 |
| 20150109046 | Semiconductor Integrated Circuit Device - An NBTI malfunction of a P-channel MOS transistor is prevented. A semiconductor integrated circuit device includes a reset pulse control unit RPC. The reset pulse control unit RPC generates a reset pulse RP for recovery from degradation caused by NBTI of a MOS transistor that receives a negative voltage at the gate of the transistor in a standby status. After the generated reset pulse RP is inputted to the gate of the MOS transistor, an action control signal ACC for activating the MOS transistor is inputted to the gate of the MOS transistor to activate the transistor. | 04-23-2015 |
| 20160020756 | Delay Line System and Switching Apparatus with Embedded Attenuators - Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators. | 01-21-2016 |
| 327399000 | With field-effect device | 14 |
| 20100001782 | POWER SWITCH CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A power switch circuit that ensures suppression of an increase in a transient current. The power switch circuit includes a first transistor, which generates an output voltage in response to a control signal, and a time difference generation circuit, which delays the control signal by performing a logical process with the output voltage of the first transistor and the control signal. | 01-07-2010 |
| 20110204955 | CONTROL PIN POWERED ANALOG SWITCH - An apparatus comprises at least one input connection, at least one output connection, and at least one control connection, and at least one switch circuit coupled to the input, the output, and the control connections. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by a control signal received at the control connection. Power to the switch circuit is provided via the control connection. | 08-25-2011 |
| 20110273221 | Driving circuits, power devices and electronic devices including the same - A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal. | 11-10-2011 |
| 20120176176 | Resonant Gate Drive Circuit For A Power Switching Device In A High Frequency Power Converter - A resonant gate drive circuit for a power switching device, having a gate-emitter capacitance, is adapted for use with a high frequency power converter. The resonant gate drive circuit comprises a signal input source, a power supply and a resonant inductor. An electrical isolator is connected between the signal input source and a switching node. The electrical isolator is connected to the power supply. A first bidirectional switch is connected between the resonant inductor and the power switching device and includes a first switch control circuit connected to the node to be controlled by a signal from the signal input source. A second bidirectional switch is connected between the power supply and the power switching device and includes a second switch control circuit connected to the node to be controlled by the signal from the input source. The first and second control circuits are adapted to control the first bidirectional switch to provide a first charge path during a resonant period from the resonant inductor to the gate-emitter capacitance defining a quick resonant charge path and to control the second bidirectional switch to provide a second charge path defining a voltage equalization charge path subsequent to the resonant period. | 07-12-2012 |
| 20120176177 | SWITCH WITH IMPROVED EDGE RATE CONTROL - This documents discusses, among other things, apparatus and methods for a switch circuit including a break-before-make delay and a gradual turn-on. In an example, a switch circuit can include a switch transistor having a control node and coupled to a first node and a second node, a delay circuit configured to receive control information and to provide the control information after a delay interval, and a gradual turn-on circuit configured to receive the delayed control information from the delay circuit and to transition the transistor from the off-state to the on-state over a ramp interval in response to the delayed control information. | 07-12-2012 |
| 20140203861 | CONTROL CIRCUIT FOR CONTROLLING A PUSH-PULL CIRCUIT AND METHOD THEREOF - A control circuit for generating a first control signal and a second control signal includes: an inverter, used for generating an inverted clock according to an input clock; a first delay circuit, used for generating a first delay control signal; a second delay circuit, used for generating a second delay control signal; a first mask circuit, used for generating a first mask signal according to the input clock; a second mask circuit, used for generating a second mask signal according to the inverted input clock; a first logic determining circuit, used for generating the first control signal to the first delay circuit according to the second mask signal and the input clock; and a second logic determining circuit, used for generating the second control signal to the second delay circuit according to the first mask signal and the inverted clock. | 07-24-2014 |
| 20140266396 | INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWITCH LOGIC - Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal. | 09-18-2014 |
| 20140300405 | INRUSH CURRENT CONTROL CIRCUIT - A control circuit includes a control module, a delay module, and an electronic switch. The control module is connected between a power supply and a load. The delay module is connected to the control module and the electronic switch. A first terminal of the electronic switch is connected to the control module and the delay module. A second terminal of the electronic switch is connected to the power supply. A third terminal of the electronic switch is connected to the load. | 10-09-2014 |
| 20140300406 | INRUSH CURRENT CONTROL CIRCUIT - A control circuit includes a control module, a delay module, and an electronic switch. The control module is connected between a power supply and a load. The delay module is connected to the control module and the electronic switch. A first terminal of the electronic switch is connected to the control module and the delay module. A second terminal of the electronic switch is connected to the power supply. A third terminal of the electronic switch is connected to the load. | 10-09-2014 |
| 20140354346 | POWER MANAGEMENT DURING WAKEUP - A circuit comprises a first set of first transistors and a second set of transistors. The first transistors are configured to be turned on in a sequential manner. The second transistors are configured to be turned on in a sequential manner after the first transistors are turned on. A transistor of the first set of first transistors corresponds to a first time delay. The first set of first transistors corresponds to a second time delay that is a multiple of the first time delay. | 12-04-2014 |
| 20150109047 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) INVERTER CIRCUIT DEVICE - There is provided a CMOS inverter circuit device. The CMOS inverter circuit device includes a delay circuit unit configured to generate different charge and discharge paths of each gate node of a PMOS transistor and an NMOS transistor respectively at the time that an input signal transitions between high and low levels. Therefore, the present examples minimize or erase generation of a short circuit current made at the time that the input signal transition. The examples may simplify circuit architecture, and may make a magnitude of a CMOS inverter circuit device smaller. | 04-23-2015 |
| 20160049930 | INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWITCH LOGIC - Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal. | 02-18-2016 |
| 20160105166 | BIDIRECTIONAL DELAY CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal. | 04-14-2016 |
| 20160191042 | CONTROL OF REVERSE-CONDUCTING IGBT - A method and an arrangement of controlling a reverse-conducting IGBT (RC-IGBT) component in a circuit comprising a series connection of controllable switch components where at least one of the controllable switch components is an RC-IGBT and the other component is to be controlled to a conductive state. The method comprising applying a pre-trigger pulse to the gate electrode of the RC-IGBT during reverse conduction of the RC-IGBT at a first time instant (t | 06-30-2016 |
| 327400000 | Propagation through plural delay devices or paths | 3 |
| 20120007653 | DATA TRANSMISSION DEVICE AND IMAGE SENSOR SYSTEM USING THE SAME - A data transmission device includes a control unit and a delay chain unit. The control unit outputs a first control signal through an nth control signal, where n is a natural number. The delay chain unit includes a first switching element through an nth switching element. The switching elements receive a first data signal through an nth data signal and perform pipelining operations on the first through nth data signals based upon the first through nth control signals, respectively, to output the pipelined data signals as at least one data stream. The switching elements are connected to each other to form at least one data delay chain. | 01-12-2012 |
| 20140247084 | SPECIFICATIONS SUPPORT ENABLEMENT - Several circuits and methods that may be implemented to enable specification support of a plurality of interface components in an IC are disclosed. In an embodiment, a circuit includes a plurality of multiplexer circuits and a control circuit. The plurality of multiplexer circuits are configured to provide a plurality of data paths and a plurality of outputs according to a set of selection signals. The plurality of data paths is configurable for at least a first mode of operation or a second mode of operation based on the set of selection signals. The first mode of operation and the second mode of operation are associated with complimentary specifications. The control circuit is coupled with the plurality of multiplexer circuits in order to control the set of selection signals of the plurality of multiplexer circuits to thereby select one of the first mode and the second mode of operation. | 09-04-2014 |
| 20140300407 | Power Switch Acceleration Scheme for Fast Wakeup - A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup. | 10-09-2014 |
| 327401000 | With plural switching elements (e.g., sequential, etc.) | 10 |
| 20090096502 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device includes arms formed by two semiconductor elements, a map memory device which stores therein a correlation map between a control value for each of the arms and an optimized dead time to be set for the control value or is capable of storing the same therein, drive control value acquiring means for acquiring a drive control value of each of the arms, and a dead time generating circuit for extracting the optimized dead time corresponding to the drive control value from the correlation map. The time taken until the other of the semiconductor elements is turned on after one thereof has received a command to turn off the same is the optimized dead time extracted by the dead time generating circuit. | 04-16-2009 |
| 20100052766 | INTELLIGENT EMBEDDED POWER RAIL AND CONTROL SIGNAL SEQUENCER - A power sequencing method may use a state machine in a programmable sequencer to program relative timing of signals to activate different power rails attached to an integrated circuit. Input lines may specify the sequencing program. Alternatively, the programmable sequencer may use an EEPROM or other computer-readable medium to program itself with a particular image of the sequencing program. The programmable sequencer may be implemented by a Field Programmable Gate Array (FPGA). | 03-04-2010 |
| 20100060340 | Switching System with Reduced EMI - Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time. | 03-11-2010 |
| 20100253413 | INRUSH CURRENT LIMITING CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - An inrush limiting circuit is connected between an external power source and a plurality of capacitors, and includes a delay trigger signal generator, a plurality of reversing circuits and a plurality of transmission gates. The delay trigger signal generator is connected to the external power source, to receive external power signals and generate a plurality of delay trigger signals. The reversing circuits are connected to the delay trigger signal generator, to reverse the delay trigger signals and output a plurality of the reversed delay trigger signals. The transmission gates are correspondingly connected to the delay trigger signal generator, the reversing circuits and the capacitors, to turn on respectively at different times based on the delay trigger signals and the reversed delay trigger signals, to cause the external power source to charge the capacitors at the different times so as to avoid an inrush current. | 10-07-2010 |
| 20120112814 | PWM TIMER FOR POWER SUPPLY - A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds. | 05-10-2012 |
| 20120188000 | POWER GATING FOR IN-RUSH CURRENT MITIGATION - The invention discloses a power gating for in-rush current mitigation. Firstly the circuit uses small power switch cells at first stage, such that those power switch cells run in saturation region. Secondly a delay unit delays a switch signal to control the dwell time of current to reduce the peak value of the current. Thirdly large power switch cells are used at the rest, such that those power switch cells operate in linear region. | 07-26-2012 |
| 20120218023 | SYSTEMS AND METHODS FOR INITIALIZING A VOLTAGE BUS AND MEDICAL DEVICES INCORPORATING SAME - Systems, apparatus, and methods are provided for initializing a voltage bus. An exemplary system includes an input interface, a voltage bus, discharge circuitry coupled to the voltage bus, connection circuitry coupled between the voltage bus and the input interface, and a control module coupled to the connection circuitry and the discharge circuitry. The control module activates the discharge circuitry prior to activating the connection circuitry. | 08-30-2012 |
| 20130088278 | CONNECTION DEVICE - A connection device for connecting a load to a power supply, comprising at least first and second current control devices arranged in parallel between the power supply and the load, and a controller arranged to switch the current control devices on in sequence for temporally overlapping on periods. | 04-11-2013 |
| 20130088279 | Power Converter - The present invention provides a power converter including a power semiconductor device, a driver circuit section that outputs a driving signal for driving the power semiconductor device, a buffer circuit section that includes a PNP transistor and an NPN transistor and that outputs a gate voltage for driving the power semiconductor device, a first delay circuit section that receives the driving signal and that generates a first delay signal on the basis of the received driving signal, a first MOSFET that has a drain electrode connected with the output of the buffer circuit section and that is driven on the basis of the first delay signal. A current flows through the buffer circuit section and the first MOSFET on the basis of the received driving signal, the first delay circuit section outputs the first delay signal after the buffer circuit section exits the transient state and turns on, and the gate voltage is applied to the power semiconductor device from the buffer circuit section to turn the power semiconductor device on by the switching operation of the first MOSFET based on the first delay signal. | 04-11-2013 |
| 20140266397 | DIGITAL SOFT START WITH CONTINUOUS RAMP-UP - A soft-start generation system is configured to generate a soft-start voltage. The soft-start generation system includes sawtooth circuitry configured to generate current having a sawtooth waveform and staircase circuitry configured to generate current having an ascending staircase waveform. A ramp-up current may be generated that is a combination of the sawtooth current and the staircase current. The ramp-up current may continuously ramp up to a predetermined current level. The soft-start voltage may be generated based on the ramp-up current. | 09-18-2014 |
