| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327360000 | Quotient | 15 |
| 20090121773 | SAMPLING CIRCUIT - The sampling circuit of the present invention includes a latch circuit | 05-14-2009 |
| 20090160526 | DIGITAL DIVIDER FOR LOW VOLTAGE LOGEN - Digital divider for low voltage LOGEN. LOGEN is a local oscillator generator. One implementation presented herein provides for a pseudo-complementary metal-oxide-semiconductor (CMOS), in that, it is not a true CMOS type circuitry that has no DC current dissipation, but nevertheless does operate well at relatively high frequencies and relatively low power supply voltage levels. Appropriately placed p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs) and n-channel MOSFETs (e.g., N-MOSFETs) are employed to provide for an all digital divider circuitry. In some embodiments, four active circuitry element levels are stacked between a power supply voltage and ground voltage level. In other embodiments, three active circuitry element levels are stacked between a power supply voltage and ground voltage level. The three active circuitry element levels embodiment provides for a greater area savings (e.g., because of the fewer elements) and also provides reduced input capacitance than the four active circuitry element levels embodiment. | 06-25-2009 |
| 20100271106 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a 1/2-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal. | 10-28-2010 |
| 20110140760 | Local Oscillator With Injection Pulling Suppression and Spurious Products Filtering - A single sideband mixer circuit includes a voltage controlled oscillator operable a tunable frequency f1. The mixer circuit outputs a frequency signal at a frequency f1±f2. A tracking filter operates to filter the frequency signal and generate a first output signal at the frequency f1±f2. A resonance frequency fr of the tracking filter is tunable to substantially match the frequency f1±f2 of the frequency signal. The output signal of the tracking filter may be processed by a phase lock loop circuit to generate a control signal for controlling the setting of the tunable frequency f1 and resonance frequency fr. Alternatively, the output signal of the tracking filter may be divided and the divided signal processed by a phase lock loop circuit to generate the control signal for controlling setting of the tunable frequency f1 and resonance frequency fr. | 06-16-2011 |
| 20110260771 | POWER COMBINER/DISTRIBUTOR AND TRANSMITTER USING THE POWER COMBINER/DISTRIBUTOR - The power combiner/distributor for performing one of power combination and power division, includes: a first branch circuit ( | 10-27-2011 |
| 20110285451 | PRECISION VOLTAGE DIVIDER - A circuit for producing a quotient of two input voltages, Vy and Vx has a resistor across which said two input voltages are selectively successively applied. An operational amplifier has a reference potential (Vref) applied to one input, and a tap selectively connectable at one side to various points of the resistor is connected at its other side to the other input of the operational amplifier. The tap also provides a voltage output node of the circuit. After the tap has been configured with input voltage Vy applied across the resistor so that a voltage on the output node is substantially equal to the reference potential (Vref), when the input voltage Vx is applied across the resistor, a voltage on the output node represents a quotient of the input voltages Vy and Vx. | 11-24-2011 |
| 20110304378 | PERFORMING MULTIPLICATION USING AN ANALOG-TO-DIGITAL CONVERTER - A multiplier circuit to multiply a first signal with a second signal includes an analog-to-digital converter that has a first input and a second input. The first input is to receive the first signal. The multiplier circuit also has an inverting circuit having an input to receive the second signal, and an output connected to the second input of the analog-to-digital converter. An output value produced by a combination of the analog-to-digital converter and the inverting circuit is approximately a multiplication of the first signal and the second signal. | 12-15-2011 |
| 20120081170 | DIVIDER AND MIXER CIRCUIT HAVING THE SAME - A divider has a clock generation circuit which combines a first trigger clock and a second trigger clock having a first phase difference, so as to generate a third clock having pulse edges corresponding to pulse edges of the first trigger clock and the second trigger clock; an output dividing circuit which divides the frequency of the third clock in half so as to generate a first differential output clock and a second differential output clock having a duty ratio corresponding to the first phase difference; and a phase correction circuit which detects a phase of the first output clock or the second output clock at a timing of the pulse edge of the first trigger clock or the second trigger clock, so as to generate a phase correction signal for resetting the output dividing circuit when the detected phase is not a normal phase. | 04-05-2012 |
| 20120280743 | SIGNAL PROCESSING ARRANGEMENT AND SIGNAL PROCESSING METHOD, PARTICULARLY FOR ELECTRONIC CIRCUITS - A signal processing arrangement including a signal processing stage that divides an input signal (Vin) applied to a signal input (In) of the signal processing stage into at least two subsignals (Vin_a, Vin_b) as a function of a signal amplitude (A) of the input signal (Vin), wherein the signal processing stage is designed for parallel signal processing of the subsignals (Vin_a, Vin_b), and a reconstruction stage connected to the signal processing stage and provides an output signal (Vout) by weighting and combining the at least two processed subsignals (Vin_a, Vin_b). | 11-08-2012 |
| 20120293235 | DOWNCONVERTER, DOWNCONVERTER IC, AND METHOD FOR CONTROLLING THE DOWNCONVERTER - A downconverter capable of being normally operated even in the case where a universal dual downconverter is made up by use of multiple downconverter circuits. The downconverter includes first and second downconverter circuits, and an amplification unit having at least a first amplifier LNA for receiving a horizontally polarized wave signal, and a second amplifier LNA for receiving a vertically polarized wave signal. If a Tone/Pola signal is a signal indicating a power-saving mode, a control circuit of the first downconverter circuit causes both a local oscillator and a frequency converter to be in a non-operating state, controlling a bias circuit such that power is supplied to the first amplifier LNA. | 11-22-2012 |
| 20130027111 | MULTIPLE-MODULUS DIVIDER AND ASSOCIATED CONTROL METHOD - A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals. | 01-31-2013 |
| 20130194023 | ADJUSTABLE POWER SPLITTER AND CORRESPONDING METHODS & APPARATUS - An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; and a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output. | 08-01-2013 |
| 20130314143 | ADJUSTABLE POWER SPLITTER AND CORRESPONDING METHODS & APPARATUS - An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the first and second adjustable phase shifters and attenuation levels to be applied by the first and second adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the first and second adjustable phase shifters and the first and second adjustable attenuators. | 11-28-2013 |
| 20140152372 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATING THE SAME - A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits. | 06-05-2014 |
| 20140197875 | CIRCUITS AND METHODS FOR SIGNAL INTERFERENCE MITIGATION - Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit. | 07-17-2014 |
