| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327346000 | Exponential | 15 |
| 20080315939 | ANTI-LOGARITHMIC AMPLIFIER DESIGNS - An anti-exponential amplifier produces an output signal that is an exponential/anti-logarithmic function of an input signal. The amplifier includes three function generators and a low-pass filter. The first function generator produces a periodic exponential waveform based upon a resistor-capacitor time constant, with the magnitude of the periodic exponential waveform exponentially increasing to a maximum value in each period. A second function generator produces a ramp waveform from the exponential waveform. The ramp waveform has a period and maximum amplitude substantially equal to those of the exponential signal. The third function generator produces a hybrid waveform with a first portion and a second portion, with the duration of the first period determined in response to the ramp waveform. A low pass filter produces the anti-logarithmic output signal as a function of the hybrid waveform. The resulting amplifier could be useful in a brightness or other parameter control for a display. | 12-25-2008 |
| 20100079188 | SYSTEMS AND METHODS FOR PROVIDING PROGRAMMABLE ANALOG CLASSIFIERS - The present invention describes systems and methods to provide programmable analog classifiers. An exemplary embodiment of the present invention provides an analog classifier circuit comprising a bump circuit enabled to store a template vector, wherein the template vector can model a probability distribution with exponential behavior. Furthermore, the bump circuit is enabled to generate an output corresponding to a comparison between an input vector received by the bump circuit and the template vector stored by the bump circuit. Additionally, the analog classifier circuit includes a variable gain amplifier in communication with the bump circuit, and the variable gain amplifier can be adjusted to modify the variance of the template vector. | 04-01-2010 |
| 20120081168 | Implementing a piecewise-polynomial-continuous function in a translinear circuit - Implementing a piecewise-polynomial-continuous function in a translinear circuit generally involves translinear elements that form translinear loops that are linked by a clamp transistor. A first translinear loop controls a first portion of the piecewise-polynomial-continuous function in a first area of operation. A second translinear loop controls a second portion of the piecewise-polynomial-continuous function in a second area of operation. When activated in the second area of operation, the clamp transistor draws current through one of the translinear elements without drawing current away from another translinear element of the translinear circuit. | 04-05-2012 |
| 20130147538 | DIGITAL PRE-DISTORTION DEVICE AND PRE-DISTORTION METHOD THEREOF - Disclosed is a digital pre-distortion device which includes a pre-compensation lookup table which outputs a first input value and a second input value adjacent to an input signal, a first distortion value corresponding to the first input value, and a second distortion value corresponding to the second input value; and a function generator which generates a pre-distortion function based on the first and second input values and the first and second distortion values and generates a pre-distortion value corresponding to the input signal from the pre-distortion function. | 06-13-2013 |
| 327347000 | Square root | 5 |
| 20150123724 | CMOS CURRENT-MODE SQUARE-ROOT CIRCUIT - A CMOS current-mode square-root circuit includes a square-root circuit configured to compensate for the errors due to the carrier mobility reduction by employing a plurality of MOSFETs in Translinear Loop (MTL). The plurality of MOSFETs are configured to operate in the strong inversion region. The CMOS current-mode square-root circuit is configured to receive an input current and a biasing current, and is further configured to produce an output current based on the input current and the biasing current. The output current based on the input current and the biasing current is described by a first square-root relation and a second square-root relation. | 05-07-2015 |
| 327348000 | RMS | 4 |
| 20090284300 | RMS Detector with Automatic Gain Control - Embodiments of the present invention provide systems, devices and methods for detecting the RMS value of a signal. The RMS detector uses multiple variable-gain stages and internal gain control to generate an RMS output signal based on an arbitrary signal input. This RMS detector significantly reduces the signal swings seen on a squarer within prior art RMS detectors and reduces the detector's dependency on DC offsets at low signal levels and overload errors at high signal levels. The embodiments of the present invention also improve the accuracy of the RMS detector within large dynamic signal ranges by obviating the operation of a squarer in saturation or out of the squaring region. Accordingly, embodiments of the present invention are able to more accurately detect RMS values on a signal, operate over relatively higher signal ranges, and better function within different signal modulation schemes, particularly those with large peak-to-average ratios. | 11-19-2009 |
| 20100194461 | EXTENDED RANGE RMS-DC CONVERTER - Described herein is technology for, among other things, reducing offset errors in RMS-to-DC converters. The technology involves generating first and second feedback signals with first and second feedback paths respectively. A multiplier is then employed to receive first and second signals and provide a third signal based on multiplying the first signal and the second signal. The first signal is based on an input signal and the first feedback signal, and the second signal is based on the input signal and the second feedback signal. A chopper is then employed to receive an output signal, which is based on the third signal, and a chopping signal, and in turn provide a fourth signal based on multiplying the output signal with the chopping signal. As a consequence, the fourth signal represents the output signal shifted to a frequency different than that of low-frequency noise components of the first and second signals. | 08-05-2010 |
| 20140118050 | HIGHLY ACCURATE TRUE RMS POWER DETECTOR FOR CELLULAR APPLICATIONS - New devices and methods capable of detecting a true Root-Mean-Square (RMS) power level of an analog input signal are disclosed. For example, an electronic circuit can include a squaring circuit that receives the analog input signal and processes the analog input signal so as to produce a squared-output of the analog input signal using an analog transfer function of the squaring circuit, and a square-root circuit that receives the squared-output and processes the squared-output using an analog transfer function of the square-root circuit so as to produce an analog RMS output signal representing the true RMS power level of the analog input signal. | 05-01-2014 |
| 20140285249 | METHOD TO IMPROVE RESPONSE SPEED OF RMS DETECTORS - A root-mean-square (RMS) detector includes detection circuitry having as an input a radio frequency signal, target voltage and a set voltage and a RMS signal as an output, and a gain stage within the detection circuitry to produce the RMS signal as an output. The gain stage provides for faster settling times of the detector. | 09-25-2014 |
| 327349000 | Square function | 6 |
| 20090045865 | SQUARE-FUNCTION CIRCUIT - A square-function circuit includes an input field-effect transistor (FET) having a gate that is driven by an input voltage and is configured to conduct an output current. The circuit also includes a feedback circuit coupled to a source of the input FET, the feedback circuit being configured to drive a source of the input FET based on the output current to set a magnitude of the output current to be substantially equal to a square of the input voltage. | 02-19-2009 |
| 20100127754 | POWER MEASUREMENT CIRCUIT - A power measurement circuit comprises: a transconductance rectifier arrangement including an input and configured to receive a sinusoidal input voltage signal; and an averaging filter for producing a time averaged DC output signal proportional to the mean square of the voltage at the input of the transconductance rectifier arrangement and representative of the average power of the input voltage signal within a range of voltages at the input. | 05-27-2010 |
| 20100127755 | POWER MEASUREMENT CIRCUIT - A power measurement circuit and method are described. The circuit comprises: a transconductance rectifier arrangement including an input and configured to receive a periodically varying input voltage signal having an approximate 50% duty cycle; and an averaging filter for producing a time averaged DC output signal proportional to the mean square of the voltage at the input of the transconductance rectifier arrangement and representative of the average power of the input voltage signal within a range of voltages at the input. | 05-27-2010 |
| 20130234775 | DYNAMIC IMPROVEMENT IN RMS TO DC CONVERTERS - A circuit for providing a DC output equal to the RMS value of a time-varying input signal, the circuit including: (i) an RMS-to-DC converter for producing the DC output and (ii) a high-order low-pass filter comprising at least first and second low-pass filters connected in series to cooperatively reduce at least one of ripple in the DC output, ripple in an denominator feedback loop, or DC error in the DC output. | 09-12-2013 |
| 20140084987 | SQUARING CIRCUIT, INTEGRATED CIRCUIT, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A squaring circuit has current mode triplet metal oxide semiconductor (MOS) devices, including a first MOS device, a second MOS device and a third MOS device each having a source operably coupled to a first current source; and a fourth MOS device, a fifth MOS device and a sixth MOS device each having a source operably coupled to a second current source. The drain of first and fourth MOS device is operably coupled to a first supply, the drain of second and fifth MOS device is operably coupled to a first differential output port and the drain of third and sixth MOS device is operably coupled to a second differential output port. The gate of first, second and sixth MOS device is connected to a first differential input port, and the gate of third, fourth and fifth MOS device is connected to a second differential input port. | 03-27-2014 |
| 20160004887 | CHOPPER-STABILIZED SQUARE CELLS - An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier. | 01-07-2016 |
