Class / Patent application number | Description | Number of patent applications / Date published |
327331000 | Maintaining constant level output | 28 |
20080218239 | Interface circuit and signal output adjusting method - The problem to be solved by of this claimed application is solved by providing an interface circuit and a signal output adjusting method that are capable of adjusting amplitude of a transmission-side signal by taking attenuation of a transmission path into consideration. In a transmission-side circuit part of an interface circuit | 09-11-2008 |
20090085634 | METHOD FOR OPTIMIZING OF COMMUNICATION SIGNAL - A transceiver that reduces power consumption when data is transferred between devices in different modes. The transceiver is arranged in a first node and in a second node, which communicate between each other. A first control unit generates a first signal transmitted from the first node in predetermined time intervals during a first period that establishes an environment for communication between the first node and the second node. The second node transmits a second signal transmitted in response to the first signal. The first control unit generates a third signal upon detection of the second signal. A second control unit gradually decreases amplitude of the first signal based on the third signal to set the amplitude of the first signal to a predetermined amplitude so that the second node is receivable of the first signal. | 04-02-2009 |
20090195290 | METHOD AND APPARATUS FOR OVERSHOOT AND UNDERSHOOT ERRORS CORRECTION IN ANALOG LOW DROPOUT REGULATORS - The present invention provides a method and apparatus for dynamically correcting overshoot and undershoot errors in an analog integrated circuit by improving the reaction time (Δt) of the analog integrated circuit. Equivalently, an error correction circuit is disclosed present invention is only activated to reduce overshoot and undershoot errors by increasing the bandwidth of the integrated circuit when either undershoot or overshoot errors are detected. | 08-06-2009 |
20090251192 | SELF-CALIBRATION CIRCUIT FOR USB CHIPS AND METHOD THEREOF - A USB chip having a self-calibration circuit is provided. The USB chip includes a comparing circuit, a digital circuit and an adjustable current output device. A close-loop structure is provided to monitor an output voltage level of the USB chip and then an output current is dynamically adjusted to calibrate the output voltage level. | 10-08-2009 |
20090273385 | OUTPUT CIRCUIT OF SEMICONDUCTOR DEVICE - An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals. | 11-05-2009 |
20100123504 | ADAPTIVE LOW NOISE OFFSET SUBTRACTION FOR IMAGERS WITH LONG INTEGRATION TIMES - An adaptive low noise offset subtraction pixel and method for adaptive low noise offset subtraction is disclosed. The pixel has a photosensitive element, a current offset memorization circuit and a current subtraction circuit. The current subtraction circuit coupled to the current offset memorization circuit, and comprises a transistor selected from a group consisting of a junction gate field-effect transistor, a bipolar transistor, a MOSFET transistor with a spiral channel, and a MOSFET transistor with a buried channel. The transistor configured to receive an offset current from the current offset memorization circuit and subtract the offset current from an output signal current received from the photosensitive element to provide an offset-free signal current and a shot noise limited subtraction current. | 05-20-2010 |
20110068846 | INTEGRATED CIRCUIT AND ELECTRONIC DEVICE COMPRISING THRESHOLD GENERATION CIRCUITRY AND METHOD THEREFOR - An integrated circuit comprises a threshold generation circuitry for generating at least one differential voltage signal. The threshold generation circuitry comprises at least one common mode current generation circuit arranged to generate at least one common mode current signal, whereby said at least one common mode current signal is combined with at least one input current signal to produce a combined current signal comprising a combined signal common mode component. Conversion circuitry is arranged to receive the combined current signal and convert the combined current signal into the at least one differential voltage signal for use within the comparator circuit. The threshold generation circuitry further comprises feedback circuitry arranged to receive an indication of the combined signal common mode component, compare the received indication to a reference value, and regulate the at least one common mode current signal based at least partly on the comparison results. | 03-24-2011 |
20120218019 | INTERNAL VOLTAGE GENERATING CIRCUIT AND TESTING METHOD OF INTEGRATED CIRCUIT USING THE SAME - An internal voltage generating circuit of a semiconductor device includes a normal reference voltage generating unit configured to generate a normal reference voltage having a constant voltage level without regard to PVT variations, a test reference voltage generating unit configured to generate a test reference voltage by dividing a voltage level between an external power supply voltage and the normal reference voltage at a set ratio, an operation reference voltage generating unit configured to generate an operation reference voltage by selecting one of the normal reference voltage and the test reference voltage in response to a test signal, and an internal voltage generating unit configured to generate an internal voltage whose voltage level is determined based on the level of the operation reference voltage. | 08-30-2012 |
20120319756 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 12-20-2012 |
20130106484 | REGULATED POWER SUPPLY VOLTAGE FOR DIGITAL CIRCUITS | 05-02-2013 |
20130321058 | INPUT INTERFACE FOR A TRANSMIT/RECEIVE STATION AND STATION COMPRISING SAME - The input interface for a transmit/receive radio station includes an input for receiving a signal either with a variable voltage over a pre-determined voltage range, or an open collector signal having a voltage (0V) corresponding to the low logic state; a first output for the variable voltage signal, and a second open collector output. The first and second outputs are connected to the same input and the input is connected to a reference potential through a first voltage divider bridge, the middle point of which is connected to the positive terminal of an open loop comparator, the output of which is connected to the second output. | 12-05-2013 |
20140253207 | Calibration of Single-Ended High-Speed Interfaces - A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage. | 09-11-2014 |
20140253208 | Calibration of Single-Ended High-Speed Interfaces - A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage. | 09-11-2014 |
20160191018 | APPARATUS FOR ATTENUATION USING FINE TUNING FUNCTION - Provided is a digital attenuation apparatus using a fine tuning function of an attenuation value, which includes: a plurality of digital attenuators connected in series; and an integrated attenuator finely attenuating the attenuation value when output values of the plurality of digital attenuators are input. | 06-30-2016 |
327332000 | With feedback | 14 |
20080258797 | NON-RESISTIVE LOAD DRIVER - Embodiments of the invention relate to a method and apparatus to drive non-resistive loads. The non-resistive load driver may include two or more drivers, such as a high-drive circuit and a low-drive circuit, to drive rail-to-rail output voltages and to stabilize the output voltages at a substantially constant level. The high-drive circuit may drive the output voltage of the non-resistive load driver to a threshold level, whereas the low-drive circuit may modify the output voltage of the non-resistive load driver to approximate an input voltage of the non-resistive load driver, and compensate any leakage associated with the non-resistive loads to provide a substantially constant output voltage. The low-drive circuit consumes less current than the high-drive circuit. The non-resistive load driver consumes less power and use less chip space. Alternatively, the non-resistive load driver may be implemented using a single driver with multiple modes, such as a low-drive mode and a high-drive mode, by changing a bias current of the non-resistive load driver between a high current mode and a low current mode. | 10-23-2008 |
20080265969 | Receiver for a Differential Data Bus - The invention relates to a receiver for a differential bus with a switch control logic ( | 10-30-2008 |
20090091366 | VOLTAGE GENERATOR OF SEMICONDUCTOR INTEGRATED CIRCUIT - A voltage generator includes a detector for outputting a driving signal according to comparison results of a reference voltage and a pumping voltage, an oscillator for generating an oscillation signal in response to the driving signal and varying a period of the oscillation signal according to a level of the pumping voltage, and a pump for pumping an external voltage in response to the oscillation signal to generate the pumping voltage. The voltage generator can quickly increase a pumping voltage up to the target level and improve the efficiency of the pumping voltage by minimizing the ripple components of the pumping voltage. | 04-09-2009 |
20090128214 | DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT - A data receiver includes a plurality of amplifiers for receiving data in response to clock signals having a predetermined phase difference, and amplifying the received data by performing an equalization function based on feedback data, thereby outputting amplification signals, and a plurality of latches for latching output of the amplifiers, respectively. One amplifier receives the amplification signal, as feedback data, from another amplifier receiving a clock signal having a phase more advanced than a phase of a clock signal received in the one amplifier. | 05-21-2009 |
20090322401 | METHOD AND APPARATUS FOR AN EVENT TOLERANT STORAGE CIRCUIT - An apparatus for an event tolerant circuit including a latch. The event tolerant circuit may maintain correct data values even after the occurrence of an event such as a soft error. The event tolerant circuit may introduce a delay in a feedback loop, thereby passing the glitch value to an element in the feedback loop at different times, thus preventing the propagation of the glitch through the event tolerant circuit. | 12-31-2009 |
20110057706 | PEAK-DETECT-AND-HOLD CIRCUIT AND METHOD THEREOF USING RAMP SAMPLING TECHNIQUE - A peak detect-and-hold circuit and method thereof using ramp sampling technique includes utilizing two sampling signals of different slopes to sample an input voltage for respective tracking voltages; comparing the held tracking voltage sampled with the sampling signal of a smaller slope and the input voltage to determine whether the input voltage is rising or falling, and if the input voltage starts falling, the held tracking voltage sampled with the sampling signal of a larger slope is taken as the peak. The peak detect-and-hold circuit using ramp sampling technique controls respective tracking voltages by comparing the input voltage with the sampling signals rather than the feedback tracking voltage. Also, it uses the input voltage directly rather than an operational transconductance amplifier to charge holding capacitors for the tracking voltages. Therefore, the errors of peak detecting and holding, namely the pedestal voltage, overshoot voltage and voltage droop are reduced. | 03-10-2011 |
20110057707 | Detection and compensation of multiplexer leakage current - A multiplexed input/output (I/O) system detects leakage currents on a selected input channel. The system includes a leakage detection multiplexer connected to provide an output selected from one of a plurality of input channels. In addition, the leakage detection multiplexer provides as part of the output measured leakage currents associated with the selected input channel. Based on the detected leakage currents, a determination can made regarding whether the detected leakage currents have compromised the integrity of the multiplexer output. In addition, the detected leakage current can be used to compensate the output provided by the multiplexer to account for the presence of leakage currents on the selected channel. | 03-10-2011 |
20110181337 | SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC DEVICE - AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data. | 07-28-2011 |
20110234290 | SWITCHED-CAPACITOR CURRENT REFERENCE WITH REDUCED OUTPUT RIPPLE - A switched-capacitor current reference contains an amplifier, a current mirror circuit and a feedback circuit. In an embodiment, the feedback circuit receives a time-varying voltage waveform at a node connected to a switched-capacitor block used within the current mirror circuit, and is operated to provide a constant voltage waveform on an input terminal of the amplifier. Ripple in the output reference current provided by the switched-capacitor current reference is minimized or eliminated. | 09-29-2011 |
20110241753 | MIXER CIRCUIT AND METHOD FOR ADJUSTING COMMON VOLTAGE OF MIXER CIRCUIT - A mixer circuit includes: a mixer circuit including a first transistor pair to output a first differential input signal and a second transistor pair to output a second differential input signal by inversing the first differential signal; a local signal supply circuit to supply a pair of local signals to gates of the first transistor pair and the second transistor pair; an operational amplifier including an input pair coupled to an output pair of the mixer circuit and an output pair coupled to the input pair via feedback resistors, the operational amplifier to amplify the first differential input signal and output a differential output signal; a common mode feedback circuit to control a center voltage of the differential output signal so that the center voltage maintains a common voltage; and a common voltage generator circuit to generate the common voltage according to an amplitude of the local signal. | 10-06-2011 |
20120212278 | Pseudo Digital Gain Control for Broadband Tuner - A digital level control circuit, such as an Automatic Gain Control, includes a plurality of digitally selectable signal levels with transitions between levels gradually varied to avoid signal output level discontinuities. An up/down counter may be used to incrementally stepwise transition an output signal between the digitally selectable output levels. Stepwise application of a control signal to the appropriate switching elements (e.g., FETs) forming an attenuator circuit may be implemented to moderate a switching time of the switching elements to provide a more gradual transition between element operating states. A deglitch circuit may be employed to latch the switching elements to achieve the desired state at the end of a desired switching transition period. | 08-23-2012 |
20130038374 | BUFFER CIRCUIT WITH REGULATING FUNCTION AND REGULATING CIRCUIT THEREOF - A regulating circuit is used with a buffer circuit. The buffer circuit at least includes a metal-oxide-semiconductor transistor and a voltage output terminal. The voltage output terminal is connected to a drain terminal of the metal-oxide-semiconductor transistor of the buffer circuit. The regulating circuit includes a first metal-oxide-semiconductor transistor and a second metal-oxide-semiconductor transistor. The first metal-oxide-semiconductor transistor has a source terminal and a drain terminal connected to a voltage source and a connecting node, respectively. The connecting node is electrically connected to a substrate of the metal-oxide-semiconductor transistor of the buffer circuit. The second metal-oxide-semiconductor transistor has a drain terminal and a source terminal connected to the connecting node and the voltage output terminal, respectively. A substrate of the second metal-oxide-semiconductor transistor is electrically connected to the connecting node. | 02-14-2013 |
20140375371 | SEMICONDUCTOR DEVICE FOR OFFSET COMPENSATION OF REFERENCE CURRENT - A semiconductor device includes a reference current generator suitable for generating a reference current, a current-voltage converter suitable for generating a first reference voltage and a second reference voltage in response to the reference current, and an analog-digital converter suitable for generating a digital code value based on a voltage difference between the first and second reference voltages, wherein the reference current generator includes a current control unit for controlling the reference current in response to the digital code value. | 12-25-2014 |
20150091631 | Method and Apparatus for Reference Voltage Calibration in a Single-Ended Receiver - According to at least one example embodiment, a method and corresponding system, or circuit, for calibrating a reference voltage of a single-ended receiver, include applying a clock signal and a reference voltage signal as inputs to the differential amplifier of the single-ended receiver. The differential amplifier provides an output signal, the output signal is processed, and an indication of a duty cycle associated with an output signal of the amplifier is evaluated. Based on the evaluated indication of the duty cycle, a control logic module, or circuit, adjusts a level of the reference voltage signal. The process of evaluating the indication of the duty cycle and adjusting the reference voltage level is repeated for a number of iterations. | 04-02-2015 |