| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327327000 | Using only transistor active elements | 23 |
| 20100253410 | CLAMP PROTECTION CIRCUIT AND A PFC CONTROL CIRCUIT EMPLOYING SUCH CLAMP PROTECTION CIRCUIT - The present invention relates to clamp protection circuit and a PFC control circuit employing such clamp protection circuit. Said clamp protection circuit comprises a high voltage isolation module used for receiving power from a high voltage power supply; a voltage clamp module used for receiving an output low voltage from the high voltage isolation module and realizing a clamp protection; and a low voltage bias module used for providing bias voltage to the high voltage isolation module and the voltage clamp module. By employing the clamp protection circuit, the precision of the clamp voltage is improved, the design is simplified and the silicon area is reduced. Meanwhile, the transient response is enhanced. Moreover, when the clamp protection circuit is applied in a PFC control circuit, the design of the whole PFC control circuit is simplified and the silicon area is reduced, and the precision and transient response of the clamp voltage of the clamp protection circuit inside the PFC control circuit are improved. | 10-07-2010 |
| 20110089989 | LIMITER CIRCUIT - The limiter circuit of this invention is a limiter circuit which, by switching action of a pair of transistors, allows passage of only signal voltage components of an input signal voltage included in ranges of an upper limit signal voltage and a lower limit signal voltage. With this construction, the pair of transistors carry out comparisons between the input signal voltage and threshold signal voltages and line switching at the same time. Therefore, there is no influence of propagation delay speed, and no switching noise occurs at times of line switching. Since diodes are not used, a high-speed limiter circuit can be manufactured. | 04-21-2011 |
| 20160049864 | POWER SUPPLYING CIRCUIT AND SOFT-START CIRCUIT OF THE SAME - The soft-start circuit includes a first charging transistor, a first capacitor, a second charging transistor, a second capacitor and a clamping p-type transistor. The first charging transistor is conducted in response to activating pulses to charge the first capacitor through a first output node such that a first output voltage at the first output node gradually increases. The second charging transistor is conducted in response to the first output voltage to charge the second capacitor through a second output node such that a second output voltage at the second output node gradually increases. The clamping p-type transistor includes a source terminal electrically connected to a clamping node, a drain terminal connected to a ground terminal and a gate electrically connected to the second output node, and is conducted when a voltage at the clamping node exceeds a clamping threshold value to pull low the voltage at the clamping node. | 02-18-2016 |
| 327328000 | Field-effect type device | 20 |
| 20090066395 | ACTIVE CLAMP FOR SEMICONDUCTOR DEVICE - An active clamp circuit for avalanching and clamping voltage at a gate terminal of a first transistor connected to a power source. The active clamp circuit includes a second transistor for turning ON the first transistor; a third transistor having EPI breakdown voltage less than that of the first transistor; a resistor coupled between a node and source and gate terminals of the third transistor; and an amplifier for comparing voltage on the resistor to a reference voltage and providing an output signal to control the second transistor, wherein, when the third transistor avalanches and the voltage across the resistor exceeds the reference voltage, the output signal turns ON the second transistor thereby clamping the gate terminal of the first transistor, wherein the active clamp circuit tracks the channel characteristic of the first transistor. | 03-12-2009 |
| 20090121770 | METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND - A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio. | 05-14-2009 |
| 20090195289 | Process-Variation Tolerant Diode, Standard Cells Including the Same, Tags and Sensors Containing the Same, and Methods for Manufacturing the Same - Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (V | 08-06-2009 |
| 20100073064 | VOLTAGE CLAMP - An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage. | 03-25-2010 |
| 20100097115 | DEVICE AND SYSTEM FOR REDUCING NOISE INDUCED ERRORS - A method and a device for reducing noise induced errors. The device includes: a latch that includes a latch input node; a voltage limiting transfer circuit connected between a first input node and between the latch; wherein the voltage limiting transfer circuit is adapted to selectively transfer an input signal from the first input node to the latch during transfer mode; and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range. | 04-22-2010 |
| 20110057705 | SEMICONDUCTOR APPARATUS AND BREAKDOWN VOLTAGE CONTROL METHOD OF THE SAME - A semiconductor apparatus operates based on a first voltage, a second voltage lower than the first voltage, and a third voltage in between the first and second voltages, and includes an output circuit including at least one transistor where a signal having an amplitude ranging from the second to first voltages is input to a gate, and a control circuit that generates a first control signal controlling a gate voltage of a transistor included in the output circuit, a second control signal controlling a voltage in a back-gate region of the transistor, and a third control signal controlling a voltage in a deep well region. The control circuit sets a voltage difference between the first and second control signals to be equal to or smaller than the larger one of a voltage difference between the first and third voltages and a voltage difference between the second and third voltages. | 03-10-2011 |
| 20110063011 | APPARATUS AND METHOD FOR TRANSMIT/RECEIVE SWITCHING - Apparatus and methods are disclosed, such as those involving an electronic device. One such apparatus includes a transmitter; a receiver; and a transmit/receive switch configured to electrically block the receiver from the transmitter during a transmit period. The transmit/receive switch includes one or more MOSFETs coupled between an input node and an output node, the input node being electrically coupled to the transmitter, the output node being electrically coupled to the receiver. The one or more MOSFETs are configured to be off during the transmit period. The transmit/receive switch further includes a clamp circuit configured to couple the output node to ground during the transmit period. This configuration effectively protects the receiver while minimizing switching artifacts. | 03-17-2011 |
| 20110234289 | Process-Variation Tolerant Diode, Standard Cells Including the Same, Tags and Sensors Containing the Same, and Methods for Manufacturing the Same - Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (V | 09-29-2011 |
| 20110273218 | Attenuator - An attenuator includes a first terminal, a second terminal, a first circuit coupled between the first and second terminals and including a field effect transistor including a gate terminal coupled to a resistor, a second circuit coupled between the first circuit and the second terminal and coupled to the first circuit via a node, and a third circuit coupled to the node. | 11-10-2011 |
| 20110304377 | SEMICONDUCTOR INTEGRATED CIRCUIT - A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state. | 12-15-2011 |
| 20120007649 | METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND - A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio. | 01-12-2012 |
| 20120223759 | RECEIVER CIRCUIT - A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal. | 09-06-2012 |
| 20120268187 | LEVEL SHIFTING CIRCUIT - A level shifter shifts the level of an input signal from a second voltage domain to a first voltage domain. To accommodate different input signal levels (e.g., including sub-threshold input signal levels) that may arise due to changes in the supply voltage for the second voltage domain, current for a latch circuit of the level shifter is limited based on the supply voltage for the second voltage domain. In this way, a drive circuit of the level shifter that controls the latch circuit based on the input signal is able to initiate a change of state of the latch circuit over a wide range of input signal levels. | 10-25-2012 |
| 20140266383 | Self-Activating Adjustable Power Limiter - A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE | 09-18-2014 |
| 20140300402 | SIGNAL PROCESSING CIRCUIT - A signal processing circuit includes a detection circuit detecting a high frequency signal being input; and an output signal adjustment circuit which is provided in a rear end of the detection circuit and includes a first field effect transistor and a second field effect transistor. The first field effect transistor has a drain connected to an output end of the detection circuit, a source connected to a gate of the second field effect transistor, and a gate connected to a drain of the second field effect transistor. The second field effect transistor has a source connected to a ground. An output signal is output from the source of the first field effect transistor. When an input level of the high frequency signal is equal to or higher than a predetermined level, a magnitude of the output signal is maintained at a predetermined magnitude. | 10-09-2014 |
| 20140306747 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING VOLTAGE STABILIZING CIRCUIT - A semiconductor integrated circuit includes a first voltage supply unit, a second voltage supply unit configured to supply a voltage with a level different from that of the first voltage supply unit, and a voltage stabilizing unit connected between the first and second voltage supply units, and including at least one discharge path that includes a clamping section configured to temporarily drop a level of a voltage introduced from the first or second voltage supply unit, and a discharge section configured to discharge the voltage having passed through the clamping section to the second or first voltage supply unit. | 10-16-2014 |
| 20140375370 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 12-25-2014 |
| 20150048874 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage. | 02-19-2015 |
| 20170237417 | Integrated Switch and Self-Activating Adjustable Power Limiter | 08-17-2017 |
| 20170237418 | Self-Activating Adjustable Power Limiter | 08-17-2017 |
