| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327318000 | In input or output circuit | 44 |
| 20080258796 | CIRCUIT ARRANGEMENT AND METHOD FOR LIMITING A SIGNAL VOLTAGE - The present invention relates to the field of signal processing. It is an object of the invention to provide a circuit arrangement (VL) and a method for limiting a signal voltage upstream of a processing stage (A) of a signal processing device, by means of which circuit arrangement and method it becomes possible to reduce signal interference. It is provided a voltage comparison (OPAMP | 10-23-2008 |
| 20090231011 | CIRCUIT ASSEMBLY FOR DISTRIBUTING AN INPUT SIGNAL - The invention relates to a circuit arrangement for distorting an audio signal, which is used when a “distorted” signal is to be formed from the clear signal for example of an electric guitar. The circuit simulates the distortion of a vacuum tube circuit. The circuit includes changing the waveform and compressing the signal, which otherwise take place by means of tube circuits. | 09-17-2009 |
| 20110140756 | ANALOG CIRCUIT HAVING IMPROVED RESPONSE TIME - There is provided an analog circuit having improved response time. An analog circuit having improved response time may include: a low level limiter converting a signal having a lower level than a predetermined reference level into a signal having a predetermined non-low level higher than the predetermined reference level; and an analog circuit section amplifying the signal from the low level limiter into a signal having a predetermined level. | 06-16-2011 |
| 20110199144 | CIRCUIT ARRANGEMENT FOR DISTORTING AN INPUT SIGNAL - The invention relates to a circuit arrangement for distorting an audio signal, which is used when a “distorted” signal is to be formed from the clear signal for example of an electric guitar. The circuit simulates the distortion of a vacuum tube circuit. The circuit includes changing the waveform and compressing the signal, which otherwise take place by means of tube circuits. The intensity of the distortion is determined by the amplification of the circuit itself, and a simple amplifier stage arranged upstream of the control voltage. An increase in the supplied signal by the upstream amplifier results in a higher distortion. By means of an optional adjustable amplifier which can be inserted between the output of the circuit and the input of the circuit part responsible for clipping, the intensity of the clipping can furthermore be adjusted without having to increase the input signal. A sound regulation and volume adjustment may be arranged downstream if necessary. | 08-18-2011 |
| 20120025890 | Circuitry and method for preventing base-emitter junction reverse bias in comparator differential input transistor pair - A differential input circuit ( | 02-02-2012 |
| 20120025891 | Bipolar transistor anti-saturation clamp using auxiliary bipolar stage, and method - An output stage ( | 02-02-2012 |
| 20120286843 | PROTECTION CIRCUIT - A P-channel MOS transistor MP | 11-15-2012 |
| 20140028370 | Crest Factor Reduction Applied To Shaping Table To Increase Power Amplifier Efficiency Of Envelope Tracking Amplifier - There is disclosed a method of controlling an input to an envelope modulated power supply of an envelope tracking amplification stage, comprising: generating an envelope signal representing the envelope of a signal to be amplified; applying a shaping function to the envelope signal to generate a shaped envelope signal, including: clipping the shaped envelope signal at high input envelope values; and providing the shaped envelope signal as an input signal to the envelope modulated power supply. | 01-30-2014 |
| 20140152368 | RECEIVING CIRCUITS FOR CORE CIRCUITS - A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer. | 06-05-2014 |
| 20140176219 | POWER CIRCUIT AND WIRELESS NETWORK ADAPTER - The present invention provides a power circuit, including a current-limiting chip, a current-limiting value setting circuit, and a baseband chip. A current setting port of the current-limiting chip is connected to a general-purpose input/output port of the baseband chip through the current-limiting value setting circuit. The general-purpose input/output port is configured to generate a first signal in a first time sequence period of timeslot transmitting of the baseband chip so that the current-limiting value setting circuit sets a current-limiting value of the current-limiting chip as a first current-limiting value. In the other time sequence periods of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a second signal so that the current-limiting value setting circuit sets the current-limiting value of the current-limiting chip as a second current-limiting value. The first current-limiting value is greater than the second current-limiting value. | 06-26-2014 |
| 20160043719 | HIGH VOLTAGE FAIL-SAFE IO DESIGN USING THIN OXIDE DEVICES - A high-voltage fail-safe input/output (I/O) interface circuit includes a voltage-divider circuit coupled to an I/O pad of the I/O interface circuit, and a selector circuit configured to couple, to a power supply line of the I/O interface circuit one of an output of the voltage-divider circuit or and I/O supply voltage. The voltage-divider circuit and the selector circuit are implemented on the same chip with the I/O interface circuit. | 02-11-2016 |
| 20160149560 | VOLTAGE CLAMP - A voltage clamp circuit which operates using a voltage controlled current source where the change of the polarity of the voltage controlled current source controls whether it is clamping or not. While clamping, the stability of the control loop uses the capacitance of the output to create and single pole roll-off of the loop gain and while not clamping, uses the capacitance of the circuit which sets the clamping voltage to produce the roll-off. The circuit operates in a linear fashion both while clamping and not clamping, which allows for a faster response when clamping is needed. | 05-26-2016 |
| 327319000 | For interstage coupling | 13 |
| 20110175662 | OPEN CIRCUIT VOLTAGE PROTECTION SYSTEM AND METHOD - A method to clamp an open circuit voltage in a photovoltaic module is proposed. The method include coupling a load resistor across an inverter module, initiating the inverter module and loading the inverter module via the load resistor, and coupling the loaded inverter module to the photovoltaic module. The method further include dissipating power via the load resistor to clamp the open circuit voltage of the photovoltaic module, synchronizing an output voltage of the inverter module with a voltage of a grid and then coupling the inverter module to the grid and de-coupling the load resistor across the inverter module. | 07-21-2011 |
| 20110241752 | Mixed-voltage I/O buffer - A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level. | 10-06-2011 |
| 20130249616 | SWITCHING ARRANGEMENT, INTEGRATED CIRCUIT COMPRISING SAME, METHOD OF CONTROLLING A SWITCHING ARRANGEMENT, AND RELATED COMPUTER PRORAM PRODUCT - There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant. | 09-26-2013 |
| 20130249617 | LEVEL SHIFT CIRCUIT - Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of BCD process and prevent damages to the high-voltage device due to the excessively high gate voltage. | 09-26-2013 |
| 20130293277 | Sensor Connection Circuit - A circuit for converting the state of a sensor into a signal interpretable by an electronic circuit, including: a comparator of the voltage level of an input terminal with respect to a reference level, the sensor being intended to be connected between a terminal of application of a first power supply voltage and the input terminal; a current-limiting element between said input terminal and the ground; and a switching element in series with the current source and intended to be controlled by a pulse train. | 11-07-2013 |
| 20130321057 | INTEGRATED CIRCUIT COMPRISING AT LEAST ONE DIGITAL OUTPUT PORT HAVING AN ADJUSTABLE IMPEDANCE, AND CORRESPONDING ADJUSTMENT METHOD - An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors. | 12-05-2013 |
| 20140049307 | CIRCUITS AND METHODS FOR SHARING BIAS CURRENT - The present disclosure includes systems and methods for sharing bias current. In one embodiment, shared bias current passes through a first level device to one or more second level devices along a bias current path. Multiple active devices may share bias current along a bias current path and process signal along the same or different signal paths. In one embodiment, bias current from one device is split among multiple devices. In another embodiment, bias current is combined from multiple devices into a device. Embodiments may include an interstage circuit along a signal path that improves stability of the circuit. | 02-20-2014 |
| 20140132328 | HIGH VOLTAGE TOLERANT INPUT/OUTPUT CIRCUIT - A high voltage tolerant I/O circuit of an electronic device is disclosed, including a voltage reducing circuit, a first node, a first transistor, a second transistor, and a control logic. The voltage reducing circuit is coupled with a signal pad and utilized for generating a reduced voltage according to an external voltage. When an internal voltage generated by an internal circuit of the electronic device is greater than the reduced voltage, the first node outputs the internal voltage as a first voltage. When the internal voltage is less than the reduced voltage, the first node outputs the reduced voltage as the first voltage. The first transistor is coupled with the signal pad and the first node. The second transistor is coupled with a second terminal of the first transistor and a fixed-voltage terminal. The control logic operates according to the first voltage to control switching operations of the second transistor. | 05-15-2014 |
| 20140368252 | INPUT AND OUTPUT DEVICE AND SYSTEM INCLUDING THE SAME - An I/O device comprises a driving unit coupled between a first voltage and a second voltage, and configured to receive a first signal so as to drive a second signal for swing with a second swing range narrower than a first swing range between the first voltage and the second voltage and supply the second signal to a transmission line. The driving unit includes a first stabilizer coupled between the first voltage and the transmission line and a second stabilizer coupled between the second voltage and the transmission line. | 12-18-2014 |
| 20150102848 | CMOS INPUT BUFFER CIRCUIT - A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer. | 04-16-2015 |
| 20150311895 | HIGH PERFORMANCE RECONFIGURABLE VOLTAGE BUFFERS - In this disclosure, new structures for high-performance voltage buffers (source followers and emitter followers) are described. The structures achieve high performance (linearity) and reduce power consumption. In addition, they are reconfigurable to optimize the performance and power consumption depending on the input frequency range. | 10-29-2015 |
| 20150381180 | INTERFACE CIRCUIT - An interface circuit receives an input signal IN having a first voltage amplitude from a first circuit, and outputs an output signal OUT having a second voltage amplitude to a second circuit. A level shifter comprises a first CMOS inverter and a second CMOS inverter which are cross-coupled, and a current limiting circuit that limits a current that flows through the first CMOS inverter and the second CMOS inverter, and converts the input signal IN into an intermediate signal INT which is a differential signal. A latch circuit receives the intermediate signal INT from the level shifter, and switches its state according to the positive signal and the negative signal of the intermediate signal INT. | 12-31-2015 |
| 327320000 | Using diode | 1 |
| 20160179121 | TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS | 06-23-2016 |
| 327321000 | Clamping of output to voltage level | 17 |
| 20080252354 | OUTPUT CIRCUIT - An output circuit includes an output block and a predrive block for driving the output block based on an input signal. The predrive block has a clamp unit connected between the gate terminal of a first output transistor and the gate terminal of a second output transistor to limit the potential of the gate terminal of the first output transistor to a value of not more than a first potential and limit the potential of the gate terminal of the second output transistor to a value of not less than a second potential. | 10-16-2008 |
| 20090153217 | Active Clamp Switching Circuit - An active clamp switching circuit includes a transformer having a primary winding and a secondary winding, a first switch, a capacitor, an impedance device, a second switch and a rectifier. The capacitor, the impedance device and the second switch form a reset loop for the primary winding so that the impedance device lowers the electric current going through the second switch, preventing burnout of the second switch. | 06-18-2009 |
| 20090195288 | SERIAL LINK TRANSMITTER - The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver. | 08-06-2009 |
| 20100052762 | Sensor Node Voltage Clamping Circuit and Method - A voltage clamping circuit includes a current source having a fixed current source and a variable current source and a variable resistor receiving current from the current source. The variable resistor varies its resistance in response to an environmental operating condition. The voltage clamping circuit also includes an amplifier configured to compare a sensor node voltage with a reference voltage, the sensor node voltage being in communication with the voltage drop across the variable resistor. The amplifier is configured and connected to provide a control output to control the variable current source to modify current output from the variable current source to at least in part prevent the sensor node voltage from exceeding a reference voltage when certain operating conditions are present. | 03-04-2010 |
| 20110115540 | SELF-POWERED DETECTION DEVICE WITH A NON-VOLATILE MEMORY - The self-powered detection device comprises a Non-Volatile Memory (NVM) unit ( | 05-19-2011 |
| 20110181336 | Output Buffer Circuit and Method for Avoiding Voltage Overshoot - An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage. | 07-28-2011 |
| 20110309872 | Voltage Spike Protection for Power DMOS Devices - A power device includes a power transistor, a capacitor with a first plate coupled to a ground node and a second plate separated from the first plate by an insulator, a first plurality of wires coupling a drain node of the power transistor to the second plate of the capacitor, a second plurality of wires coupling the second plate of the capacitor to a DC supply node, and a voltage clamping device coupled in parallel with the capacitor. The voltage clamping device is operable to limit the voltage at the second plate of the capacitor to a value below a breakdown voltage of the power transistor. | 12-22-2011 |
| 20120007648 | High voltage tolerant, small footprint BJT-CMOS active clamp - In an active clamp implemented in a 5V complementary BiCMOS process, the footprint of the active clamp, which includes at least one NMOS clamp stack, is reduced by introducing a BJT into the circuit to allow the number of NMOS clamp stacks to be reduced. | 01-12-2012 |
| 20120013384 | CLAMP CIRCUIT USING PMOS and NMOS DEVICES - A MOS-type semiconductor clamping circuit is disclosed. The clamping circuit comprises a pmos device coupled to a nmos device in series to form the clamping circuit to selectively clamp a signal to a reference voltage, the signal configured to swing between a first voltage and a second voltage about the reference voltage. When the signal is swung between the first voltage and the second voltage, the pmos device and the nmos device are subjected to a voltage swing less than the voltage swing between the first voltage and the second voltage. | 01-19-2012 |
| 20130154710 | ADAPTIVE CASCODE CIRCUIT USING MOS TRANSISTORS - The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors. | 06-20-2013 |
| 20130285730 | CLAMP CIRCUIT AND METHOD FOR CLAMPING VOLTAGE - The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to V | 10-31-2013 |
| 20140055188 | TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS - A transmission channel configured to transmit high-voltage pulses and to receive echos of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit. | 02-27-2014 |
| 20140266382 | LOW-POWER INTERFACE AND METHOD OF OPERATION - In a particular embodiment, a method includes modifying an output impedance associated with the input receiver. In response to modifying the output impedance, the method restricts an output voltage at an output node of the input receiver. Particular embodiments of an input receiver circuit are also disclosed. | 09-18-2014 |
| 20150145583 | SEMICONDUCTOR DEVICE - The semiconductor device includes a power transistor that is disposed between a first signal line, which is coupled to a first external terminal, and a second signal line, which is coupled to a second external terminal. A gate electrode of the power transistor is coupled to a third signal line. The semiconductor device further includes a clamp circuit that clamps a voltage between the first signal line and the third signal line, a first resistive element that is disposed between the third signal line and the second signal line, and a monitoring section that monitors a voltage between the third signal line and the second signal line. The clamp circuit is configured so that a clamp voltage can be changed. The monitoring section exercises control to decrease the clamp voltage when the voltage between the third signal line and the second signal line exceeds a predefined threshold value. | 05-28-2015 |
| 20160004269 | CIRCUITS AND METHODS FOR TRIMMING AN OUTPUT PARAMETER - Methods and circuits for adjusting the output parameter of a device wherein the output parameter is temperature dependent are disclosed herein. An example of a method includes: adjusting the output parameter to a target level at a first temperature; adjusting a linear temperature-dependent variable related to the output parameter to zero at the first temperature; adjusting a nonlinear temperature-dependent variable related to the output parameter to zero at the first temperature; adjusting the output parameter to the target level at a second temperature using the linear-dependent variable; adjusting the nonlinear temperature-dependent variable to zero at the second temperature; and adjusting the output parameter to the target level at a third temperature by adjusting the nonlinear variable. | 01-07-2016 |
| 20160126940 | SPEED BOOSTER FOR COMPARATOR - Representative implementations of devices and techniques provide a speed increase to a comparator circuit. An active clamp device may be positioned between an input stage and an output stage of the comparator, limiting the voltage range of the output of the first stage. | 05-05-2016 |
| 20160173072 | SUBTHRESHOLD METAL OXIDE SEMICONDUCTOR FOR LARGE RESISTANCE | 06-16-2016 |
| 327322000 | Of output current | 2 |
| 20080238521 | LOW DIFFERENTIAL OUTPUT VOLTAGE CIRCUIT - A low differential output voltage circuit having a voltage generator and a differential output unit is provided. The voltage generator includes a first PMOS transistor, a first amplifier circuit, a unit gain stage, a first NMOS transistor, a second NMOS transistor. The differential output unit includes a first controlled current source, a second controlled current source, a common voltage circuit, a first switch, a second switch, a third switch, and a fourth switch. Due to the voltage generator directly provides a common mode voltage to the differential output unit, and the first amplifier circuit and the unit gain stage could overcome a channel modulation effect of MOS transistors and enhance the driving ability of the common mode voltage respectively. Thus, a response time of the invention is decreased, and an output current of the differential output unit is in a proportion to the reference current received by the voltage generator. | 10-02-2008 |
| 20110032018 | IN-RUSH/OUT-RUSH CURRENT LIMITING CIRCUIT AND DEVICES CONTAINING SAME - An in-rush or out-rush current limiting circuit employs a low number of components to effect in-rush current limiting and may be employed in dongles or on-chip (in the case of serving as an out-rush current limiting circuit). The in-rush current limiting circuit may be employed, for example, in USB dongles, Display Port (DP) dongles, or any other suitable connector as desired. Alternatively, the circuit may be integrated onto a circuit board or within an integrated circuit as desired. Among other advantages, a lower cost, low complexity solution may be provided. In addition, bulk capacitance can be increased such as by employing a trickle resistor or other suitable limiting structure. | 02-10-2011 |
